sigma delta pll.pdf

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 2, FEBRUARY 2008 497

PLL Transmitter With a Loop-BandwidthCalibration System

Yukinori Akamine, Manabu Kawabe, Kazuyuki Hori, Takao Okazaki, Masumi Kasahara, andSatoshi Tanaka, Member, IEEE

AbstractWe developed a PLL transmitter with a linearcharge pump and a new loop-bandwidth calibration system thatcan calibrate loop bandwidth accurately in a very short time.The calibration system uses a double integration technique thatintegrates the transient signal at the voltage-controlled oscillatoroutput during the response to a step wave input to the divider.In our PLL transmitter for GSM phones, the calibrationsystem keeps the loop bandwidth within 2% and the calibrationtime is about 25 s. To improve the GSM spectrum, we developeda charge pump that reduces a spike noise and the asymmetryof the charge and discharge characteristics. The phase error ofmodulation in the PLL transmitter with the charge pumpand calibration system was kept within 2 degrees rms, and aftercalibration the 400-kHz offset noise level of the spectrum maskwas 64 dBc.

Index Terms PLL, fractional- PLL, GSM, loop band-width.

I. INTRODUCTION

LOW NOISE and low power consumption are the mostimportant features of radio frequency integrated circuits(RF-ICs) used in mobile phones. Offset PLL transmitters havebeen widely used in GSM phones because of their low noiseperformance, and PLL transmitters have been studiedbecause they can provide the same noise performance whileusing less power [1], [2]. PLL transmitters, however, aresensitive to variation of loop bandwidth or loop gain. When theloop bandwidth is smaller than designed, the phase error of themodulation is degraded because less of the spectrum can beused for the signal. When the loop bandwidth is greater than thedesigned bandwidth, on the other hand, the noise performance(e.g., the 400-kHz and the 20-MHz offset noise performance)is degraded because the phase noise and the quantization noiseincrease. Loop-bandwidth calibration methods for PLLtransmitters have therefore been studied extensively [4][10].Loop bandwidth varies because of variations in process, tem-perature, voltage, and carrier frequency. The frequency of thevoltage-controlled oscillator (VCO) in a GSM phone needs tobe changed for frequency hopping. Since the sensitivity of aVCO depends on the control voltage, it is generally differentat different frequencies. Because the loop bandwidth thus

Manuscript received March 12, 2007; revised September 20, 2007.Y. Akamine, M. Kawabe, K. Hori, T. Okazaki, and S. Tanaka are with Hitachi,

Ltd., Kokubunji, Tokyo 185-8601, Japan (e-mail: [email protected]).

M. Kasahara is with the Renesas Technology Corp., Kokubunji, Tokyo 185-8601 Japan.

Digital Object Identifier 10.1109/JSSC.2007.914325

Fig. 1. PLL transmitter.

varies in every transmission burst, we have developed aPLL transmitter that has an improved charge-pump circuit andcan correct the loop bandwidth in the short time before everytransmission burst.

This paper is organized as follows. Section II introducesPLL transmitters, Section III describes our loop-bandwidth cal-ibration system and its operation sequence, and Section IV de-scribes our new charge-pump circuit that eliminates the deadzone for small phase differences and ensures that the charge anddischarge currents are symmetrical. Section V presents the re-sults we obtained when evaluating a prototype of our newPLL transmitter, and Section VI concludes the paper with a briefsummary.

II. PLL TRANSMITTERS

The PLL transmitter (Fig. 1) has been studied extensivelybecause of its low noise performance and low power require-ments. Binary digital data from baseband LSIs is lead to theGaussian filter that generates the frequency signal for GMSKmodulation. That signal is input to the modulator, whichgenerates the value of the divide ratio of a fractional- PLL.Then the VCO of the fractional- PLL generates the GMSK-modulated signal when the divide ratio is changed by themodulator.

Because the PLL transmitter requires only one VCO, itscurrent consumption is low and its chip size is small. Its loopbandwidth, however, must be about 100 kHz because the phasenoise level of the PLL is almost impossible to achieve at lessthan the GSM standard 400-kHz offset noise level. ThePLL transmitter is also sensitive to the variation of loop band-widthwhich changes with voltage, process, temperature, andfrequency hoppingbecause the loop bandwidth is smaller thanthe modulation signal bandwidth. We therefore developed a newloop-bandwidth calibration method.

0018-9200/$25.00 2008 IEEE

498 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 2, FEBRUARY 2008

Fig. 2. Simulated phase error.

III. LOOP-BANDWIDTH CALIBRATION SYSTEM

A. Impact of Loop Gain Error on PLL TransmittersFig. 2 shows the simulated result of the phase error of the

modulation signal at GSM standard [3] when the loop gain ofthe PLL error is at the designed value. The horizontal axisin Fig. 2 is the loop gain error at the designed value, and thevertical axis is the rms phase error of the modulated signal. Thephase error specified in the GSM standard [3] is less than 5 de-grees rms. The simulated phase error shown in Fig. 2, however,includes only the effects of the phase noise of the modu-lator and loop gain error but should include the effects of otherfactors such as jitter and thermal noise. To compensate for theseeffects, the specified phase error should be less than one degreerms. Therefore, the loop gain error should be less than 5% forour specifications. Because the loop gain error due to processvariation is generally more than 5%, a loop-bandwidth calibra-tion system is necessary.

B. Factors Causing Loop Gain VariationThe loop gain of a PLL can be expressed as follows:

(1)

where is the transfer function of the loop filter, is thedivide ratio, is the charge-pump current, and is theVCO sensitivity. When the third-order lag-lead filter shown inFig. 3 is used, the transfer function of the loop filter can be ex-pressed as shown in (2) at the bottom of the page,where

, , and . The fre-quency characteristics of are shown in Fig. 4. The pointat which the -versus-frequency curve crosses the axisis well known as the unity-gain frequency and in general PLLdesign is the same as the loop bandwidth. The variation factorsin are , , , and the resistance and capacitancevalues determining (Fig. 5). Since in , , ,

Fig. 3. Third order loop filter.

Fig. 4. Impact of N , Kv, Icp and Ct variation.

Fig. 5. Variation factors on PLL transmitter.

and always appear together as a product independent of thefrequency, we can minimize the variation due to , , , and

by changing only one of these factors. The variation in ,, , and makes the curve in Fig. 4 shift in the vertical

direction.In our calibration system, we can reduce the variation of loop

gain by optimizing only . In general, the integrated resis-tances and capacitances have almost the same variation ratio.That is, the variation of resistance and capacitance shifts the

(2)

AKAMINE et al.: PLL TRANSMITTER WITH A LOOP-BANDWIDTH CALIBRATION SYSTEM 499

Fig. 6. Step response wave form of closed PLL.

poles and zeros of and shifts the curve in Fig. 4 in thehorizontal direction. Our calibration system optimizing canshift the -versus-frequency curve only vertically, but thisis sufficient for calibrating the loop bandwidth.

C. Step Response of a PLLThe proposed loop-bandwidth calibration system uses the

step response of a closed PLL. The response of the VCO whenthe step wave is input to the divider in the PLL is shown inFig. 6. The step response of the VCO is fast and some ringingoccurs when the gain of the PLL is high, but the step response isslow when the gain of the PLL is low. The proposed calibrationsystem uses those characteristics. The conceptual sequence isas follows.

In the lock state of PLL, the frequency of the VCO is inte-grated over time. After the lock state, a step input for calibra-tion is applied and the frequency of the VCO is integrated overtime. The difference between these integrations during the lockstate and step-input state is shown in Fig. 6 as a shaded area.The shaded area has a difference between high loop gain andlow loop gain. The integration period should be enough long toyield a large difference between the low and high loop gains.

The integrated values under the lock and step-input states arethen integrated once more over time. This is a double integrationover time. Finally our calibration system calculates the doubleintegration difference between the lock and step-input states.The double integration yields a difference between the high andlow loop gains that is larger than that yielded by the first inte-gration, so we can determine the loop gain more accurately byusing the double-integration technique. Another advantage ofdouble integration is that the calculated double integration re-sults have a linear relationship to 1/(loop gain) that makes thelogic of detecting the loop gain easier.

D. Relation Between Loop Gain and Accumulation Result

When we use the third-order lag-lead filter, the closed-looptransfer function of a PLL can be expressed as shown in(3) at the bottom of the page, where ,

, and . When we consider theimpulse or step response of a PLL, the effects of the third-orderand fourth-order terms in the denominator of (3) are so smallthat they can be ignored. We then get the following equation:

(4)

where , , and. When we consider the impulse

response, we should use the Laplace transform. By Laplacetransformation of (4), we get the impulse response of (4) as thefollowing equation:

(5)

To calculate a step response we can use the convolutionbetween the impulse response and the step. We get the fol-lowing equation as the convolution between (5) and thestep. To step the VCO output by , the divider should bestepped by . So a step is used in (6) shown at thebottom of the next page, where ,

, , and step. Now, we can get the (6) as the

frequency step at the VCO output, when the step for calibra-tion is the input from the divider. In the proposed calibration

(3)


Fig. 7. New loop bandwidth calibration system for PLL transmitter.

system, double integration is used at the VCO output. Thedouble integration of (6) can be expressed as follows:

(7)

where , , and .and can be calculated from the condition in the integration anddouble integration which should be zero at . If the durationof the step input for calibration is long enough, the period ofdouble integration in (7) can be approximated as from zero toinfinity. We then get the following equation:

where(8)

In this equation we can see that the double integration of the stepresponse is proportional to .

E. New Loop-Bandwidth Calibration SystemOur loop-bandwidth calibration system for PLLs is

shown in Fig. 7.

Fig. 8. Transient signal at each part.

The additional blocks of the PLL transmitter for calibra-tion are the register for the step wave, the 16-bit ECL counter atthe VCO output, the 24-bit accumulator, and the control logicfor the charge-pump current. These can be implemented assimple digital circuits. The sequence of the calibration systemis as follows.

First, the PLL should be in the lock state. Then the16-bit ECL counter at the VCO output counts up the valuesof VCO frequency integrated over time. These counted valuesare sampled by the crystal clock at 26 MHz and then thesampled values are integrated by the 24-bit accumulator. Theseintegrated values at the accumulator are the values of VCOfrequency double-integrated over time. The double-integratedvalues are memorized at the resistor as ACC1 (Fig. 8).

Second, the step wave stored in the register is applied to themodulator in the lock state of the PLL. Then, in the

same sequence as in the lock state, the counter and the accu-mulator integrate the VCO output signal. The double-integratedvalue in the step-wave-input state should be stored in the resistoras ACC2 (Fig. 8).

Finally, the control logic for the charge-pump current calcu-lates the difference between the double-integrations of the lockand step-input states (ACC2 ACC1), which depends on theloop gain of the PLL. As described in the Section III-D, the re-lation between ACC2 ACC1 and 1/loop gaini.e., the recip-rocal of (1)is almost linear, so the control logic for the charge-pump current can be implemented by fairly simple circuits.

(6)


Fig. 9. Synchronization of the calibration system.

Fig. 8 shows the waveforms at each part of the calibrationprocess. The waveform of Fig. 8(a) is a step signal that is fedinto the modulator. The waveform shown in Fig. 8(b) indi-cates the VCO-output frequency under the step response. Thewaveforms under the step response differ between high and lowloop gain. When the loop gain is high, the step response is fast.Regarding the step, we should take care of the following twothings.

1) The transient response of step happens in a short time, suchas a few microseconds.

2) The input step should be small to keep the lock and removethe impact of the variation in locking voltage.

The waveform shown in Fig. 8(c) indicates the counter-outputvalue. The counted value is the result of integrating the VCOfrequency over time. If we use the counted value for a calibra-tion, there is a problem in the accuracy to detect the differencebetween low and high loop gain. For example, the step transientis supposed as 10 s and the 1-MHz step is supposed to input in902 MHz at VCO-output. When the counter operates under the902 MHz and 903 MHz at VCO-output for 10 s, the countedvalues are 9020 and 9030 respectively. Then, we can notice thatthe difference between high and low loop gain in step must beless than only 10 ( ).

To improve the accuracy with which the difference betweenlow and high loop gains is determined, an accumulator is addedat the counter output. The waveform shown in Fig. 8(d) is theresult of the double-integration of the VCO output frequencyover time.

In the case of double integration, the accumulator can detectthe transient of the counted value more accurately. As described,the difference of the counted values, which means the integratedresult, is less than only 10. However, the double integration canhave about 10 chances to detect the timing at when the differ-ence of counted values between low and high loop gain hap-pens during the count of around 9000. That is, the accumulatoroutput signal can indicate the difference between low and highloop gains more accurately.

F. Synchronization of Calibration SystemSynchronization is necessary if our calibration system is to

determine the loop gain accurately because the system is sensi-tive to the phase of VCO at the start of the calibration. It is there-fore necessary to synchronize the reference signal to sample the

counted value, the VCO output signal, and the reset signal asshown in Fig. 9.

IV. CHARGE-PUMP CIRCUITWhen a PLL uses an integer divider, the phase detector

and the charge pump operate under conditions in which inthe locking state there is a small phase difference betweenthe divider output and the reference signal. The nonlinearityof a charge pump far from a small phase difference has nosensitivity because it operates only under a small phase error.The nonlinearity around a small phase differencei.e., thedead zone of the phase detector and charge pump is wellknown and causes spurious noise. But because this spuriousnoise can be decreased using a loop filter, nonlinearity of thephase detector or charge pump is basically not an issue with aninteger PLL.

When we use a PLL or fractional PLL, however, thephase of the divider output alternatively repeats a little faster andslower than the phase of the reference signal in the lock state.Then nonlinearity of the charge pump around a small phasedifference not only generates spurious noise but also causesphase noise degradation. Phase noise degradation in a PLLdegrades the modulation spectrum, so the phase detector andcharge pump for a PLL must have quite linear characteris-tics around a small phase difference.

Fig. 10 shows the dead zone and asymmetry between thecharge and discharge currents in a charge pump. These phe-nomena degrade the modulation spectrum. According to oursimulation results, if the asymmetry between the charge and dis-charge on the charge pump is 1%, the modulation spectrum ofGSM is degraded by about 10 dB from the ideal spectrum.

The phase-detector and charge-pump generally used areshown in Fig. 11. The phase detector is made up of twoflip-flops and a NAND circuit. The flip-flops are reset by thefeedback signal via the NAND circuit, so the feedback delaymakes the dead zone. And the spike noise at the reset timingcauses phase noise degradation. The spike noise happens be-cause of the delay of resetting the flip-flops, during which delaythe switches for charge and discharge are ON at the same time.

A well known way method to avoid the asymmetry be-tween the charge (pMOS) and discharge (nMOS) operationsis to use same size nMOS for both [13]. Fig. 12(a) showsthe chargepump circuit usually used to make charging and


Fig. 10. No linearity on charge pump.

Fig. 11. Phase detector.

Fig. 12. Known charge-pump circuit.

discharging more symmetrical. The charge current is translatedvia a pMOS current mirror. The current consumption of thiscircuit, however, is twice that of the charge-pump circuit shownin Fig. 11.

Spike noise is usually avoided by using the charge-pump cir-cuit shown in Fig. 12(b) [13][15]. When both P and N switchesare ON, the charge pump outputs the spike noise. In this cir-cuit the slave charge pump can keep the voltage at charge-pumpoutput when both P and N in the master charge pump are ON,

and the spike noise can be reduced by the operational amplifier.The asymmetry, spike noise, and dead-zone problems shouldbe solved at same time, however, to keep the good modulationspectrum of GSM.

We therefore developed the charge-pump circuit shown inFig. 13. When each of the nMOS current sources is the samesize, . Therefore, the charge and dischargeoperations are symmetrical because .

The slave charge pump can reduce the spike noise of the phasedetector at the reset timing. The slave charge pump input is con-nected to the reset of the phase detector. When the reset ofthe phase detector is high level, the slave charge pump enables I2on the nMOS side. Ib should then be the same as I2 because theoperation amplifier decides the bias level of the pMOS. Whenreset is low, the slave charge pump enables I1, and .When , Ib is always the same , except atthe time of switching. The switching of the slave charge pumpat also reset can compensate for the spike noise of the mastercharge pump. Our charge pump can be made using simple cir-cuits on a small chip.

V. PROTOTYPE DEVELOPMENT AND EVALUATION RESULTS

A. PLL TransmitterThe prototype PLL transmitter we made (Fig. 14) con-

sists of a 0.25- m SOI BiCMOS circuits and a FPGA. TheFPGA comprises a GMSK filter, a modulation block, anda calculator to control charge-pump current. The fractional-PLL was fabricated using 0.25- m SOI BiCMOS technology.The operation of the PLL transmitter is as follows.

Data for transmission is supplied to this system in a binarydata format at 270.83 kHz and then filtered by a Gaussianfilter on an FPGA to generate a GMSK-modulated signal.The Gaussian filter output has a 16-bit data structure and thesampling rate is 6.5 MHz. Frequencychannel-selection data isthen added and the signal is fed into the third-order MASHmodulator. The input signal of the modulator is a 24-bitone, and the sampling rate is 26 MHz. The modulatorshapes noise in order to decrease the quantization noise in thesignal band. This shaped signal is given to the divider in afractional- PLL at a sampling rate of 26 MHz. This divider isan A/B-counter type (i.e., a pulseswallow-counter type) andconsists of ECL circuits. The VCO output provides a GSMmodulation spectrum.

The linearity of the charge pump in the fractional- PLLneeds to be good. Our charge pump assures that the charge-current and discharge-current characteristics are symmetrical(within 10%) over the entire range of the charge pumps op-eration voltages (Fig. 15).

The 16-bit ECL counter and 24-bit accumulator for loop-bandwidth calibration are on the BiCMOS chip, and the charge-pump current-control logic and step-wave register are on theFPGA. In this prototype, the third-order loop filter is outsideof the chip.

B. Calibration System Evaluation ResultsThe results of evaluating the double-integration of the loop-

bandwidth calibration system are shown in Fig. 16. The accu-


Fig. 13. New charge pump circuit.

Fig. 14. Block diagram of PLL transmitter with loop bandwidth calibration system.

Fig. 15. Double-Integration evaluation result.

mulator integrates 260 points of counter-output, with a 26-MHzsampling clock, in the lock and step-input states. This systemtakes approximately 25 s for the calibration (excluding thelock-up time of the PLL). The vertical axis in Fig. 16 is thevalue determined by subtracting the double-integrated value inthe lock state from the double-integrated value in the step-inputstate, and the horizontal axis is the reciprocal of the loop gain

Fig. 16. Charge and discharge current under each register value.

normalized by the most suitable value of loop gain (i.e., the de-signed loop gain). The ideal normalized 1/(loop gain) changesapproximately step per step of increased double-inte-gration, and the double-integration result is always withinof the ideal line. This means that 1/(loop gain) can be deter-mined to within 2% accuracy . That is, thecalibration accuracy of loop bandwidth is 2%.


Fig. 17. Dependency on output voltage.

The calibration accuracy depends on the loop bandwidth andthe sampling clock for the double-integration. In this prototype,the designed loop bandwidth is around 100 kHz and the sam-pling clock is 26 MHz. When the loop bandwidth is larger butthe sample clock is the same, the calibration accuracy is de-graded because of the faster PLL response. Therefore, the sam-pling clock should be faster to maintain calibration accuracy.

C. Charge Pump Evaluation ResultsFig. 17 shows the charge pump evaluation result for each

register value. Our charge pump can set the current using a6-bit register. The register decides the Vbias of current sourceof the pMOS in Fig. 12. The charge-pump current can be setfrom 400 A to 1620 A in 20- A steps. The charge and dis-charge currents were measured when the charge pump outputwas 1.4 V.

The dependence of the charge and discharge currents on thecharge-pump output voltage is shown in Fig. 15. In this case, theregister value of the charge pump was 55. The locking voltage atthe output of the charge pump depends on the offset frequencyand of the VCO. Our VCO can select the most suitableoffset frequency automatically. When the VCO is in use, thevoltage at the output of the charge pump in the lock state isalways between 0.8 V and 1.8 V and the error between chargecurrent and discharge current is less than 1%.

The dead zone of the charge pump is problematic with theconventional PLL, and the results of evaluating the dynamicoperation of our charge pump are shown in Fig. 18. Note thatthere is no dead zone and that the charge and discharge charac-teristics are almost symmetrical.

D. GMSK Modulation and Phase ErrorWe adapted our calibration system to the PLL trans-

mitter. Fig. 19 shows the spectrum of GMSK modulation forGSM at the power amplifier (PA) output when the PA outputis 35.1 dBm. The modulation spectrum is measured after theloop-bandwidth calibration. The 400-kHz offset noise level is

64 dBc at a PA output that has 4-dB margins at the GSM stan-dard [3]. But we noticed that the noise of the FPGA, which ison the same board as BiCMOS IC, increases the phase noise ofthe PLL and degrades the 400-kHz offset noise level.

The phase error at GSM standard is sensitive to the loop gain,but our calibration system can choose the most suitable value

Fig. 18. Transient characteristic.

Fig. 19. Spectrum at PA output.

Fig. 20. Charge pump current versus phase error of GMSK modulation.

for the charge-pump current. Fig. 20 shows results of the eval-uation of the rms value of the phase error at the GSM standard[3] when the charge-pump current was changed manually. Thephase error shown in Fig. 20 was measured at the PA outputwhen the power there was 35.1 dBm. The vertical axis in Fig. 20is phase error at the GSM standard. and the horizontal axisis the charge pump current. The charge-pump current can beset from 400 A to 1620 A in 20- A steps. The most suit-able charge-pump current was 1040 A, where the phase errorwas 2.0 degrees rms (Fig. 20). Our loop-bandwidth calibration


Fig. 21. Die photograph.

Fig. 22. Photograph of evaluation board.

system is always able to set the charge-pump current at mostsuitable current after the calibration, and our PLL trans-mitter with the loop-bandwidth calibration system can alwayshold the phase error to 2 degrees rms or less.

E. Evaluation Board

Fig. 21 is a die photograph of BiCMOS IC that we developedas a prototype. It was fabricated using 0.25- m SOI BiCMOStechnology and included a VCO, a divider, a phase detector, acharge pump, a 16-bit ECL counter, and a 24-bit accumulator.The power level at the VCO output was 3 dBm. The currentconsumption was 65 mA (85 mA during calibration) at 2.7 V.

Fig. 22 is a photograph of the evaluation board that includedan FPGA, a power amplifier, and a BiCMOS-IC. The FPGAincluded a GMSK filter ROM, a CIC interpolator, a third-orderMASH, a step register for the calibration, and a charge-pumpcontroller.

TABLE ILOOP BANDWIDTH CALIBRATION SYSTEM

TABLE II PLL TRANSMITTER

VI. CONCLUSION

Because the loop bandwidth in a conventional PLL trans-mitter varies and the characteristics of the charge pump in thattransmitter are nonlinear, we developed a loop-bandwidth cali-bration system and a more linear charge pump. The calibrationsystem used the characteristics of the step response of a PLLand has simple counter and accumulator circuits. The calibra-tion time is only 25 s, and this system can calibrate the mostsuitable bandwidth of a PLL before every transmit burst. Theloop gain is determined to an accuracy within 2%. Our chargepump made the charge and discharge currentvoltage character-istics symmetrical and eliminated the dead zone.

We made a prototype PLL transmitter, with the chargepump and the loop-bandwidth calibration system, for GSM 850,900, DCS 1800 and PCS 1900 mobile phones. After calibrationthe phase error at the GSM standard was less than 2 degrees rms.The 400-kHz offset noise level at the PA output was 64 dBc,that is, 4-dB margins from GSM specification. The 20-MHzoffset level at the VCO output was 162 dBc/Hz.

ACKNOWLEDGMENT

The authors would like to thank to K. Watanabe and S. Tanakaof Renesas Technology Corporation and the RF-IC team ofTakasaki Renesas Technology Corporation.


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[15] I. A. Young, J. K. Greason, and K. L. Wong, A PLL clock generatorwith 5 to 110 MHz of lock range for microprocessors, IEEE J. Solid-State Circuits, vol. 27, no. 11, pp. 15991607, Nov. 1992.

Yukinori Akamine was born in 1974 in Siga Prefec-ture, Japan. He received the B.S. and M.S. degreesfrom Waseda University, Japan, in 1997 and 2000.

He joined the Central Research Laboratory ofHitachi, Ltd., Tokyo, Japan, in 2000 and has beenengaged in the development of mobile phone RF-ICsfor GSM, EDGE, and WCDMA standards. Hiscurrent interest is analog and digital techniques fordigital interface RF-ICs.

Manabu Kawabe was born in Osaka, Japan, in1960. He received the B.E. and M.E. degrees inelectronics engineering from Kobe University, Japan,in 1982 and 1984.

In 1984, he joined the Communication SystemsLaboratories of Oki Electric Industry, Ltd., Tokyo,Japan. In 1997, he joined the Central Research Lab-oratory of Hitachi, Ltd., Tokyo, Japan, and has beenengaged in the development of radio communicationsystems.

Kazuyuki Hori was born in Osaka, Japan, in 1967.He received the B.E. degree in electrical engineeringand the M.E. degree in informatics from the TokyoInstitute of Technology, Japan, in 1990 and 1992.

In 1992, he joined the Central Research Laboratoryof Hitachi, Ltd., Tokyo, Japan, and has been engagedin the development of RF power amplifier linearizers.

Takao Okazaki was born in Hiroshima, Japan, in1957. He received the B.E. and M.E. degrees in me-chanical engineering and the B.S. degree in physicsfrom Tokyo Institute of Technology, Japan, in 1979,1981, and 1984, respectively.

In 1984, he joined Micro Device Division, Hitachi,Ltd., Tokyo, Japan. Since then, he has been engagedin the development of mixed-signal LSIs.

Masumi Kasahara was born in Gunma, Japan.In 1979, he joined Hitachi, Ltd., where he wasengaged in the development of analog mixed LSIs.In 2003, Semiconductor group of Hitachi, Ltd.became Renesas Technology Corporation. Sincethen, he has been engaged in the development of RFcommunication LSIs.

Satoshi Tanaka (M93) was born in 1960 in KyotoPrefecture, Japan. He received B.S. and M.S. degreesfrom Waseda University, Japan, in 1983 and 1985,respectively.

Since 1985, he has worked at the Central Re-search Laboratory of Hitachi, Ltd. He has beenengaged in research and development efforts devotedto mixed analog and digital LSIs for VCRs andTV sets, low-voltage high-frequency analog RFICs for paging receivers, low-noise amplifiers formagneto-optical disks, digital signal processors

for magnetic recording systems, low-voltage low-power logic circuit designtechniques, and GaAs MMICs and PAs for mobile communication systems.From September 1995 to November 1996, he was a visiting researcher at theElectrical Engineering Department, UCLA, where he was engaged in researchon CMOS RF circuit design techniques. Since 1996, he has been developing RFCMOS circuits for paging receivers, RF ID tag systems, and BiCMOS RFICsfor GSM and W-CDMA applications. His current interest is circuit techniquesfor RF power amplifier module and related system design.

Mr. Tanaka was a member of the technical program committee of the IEEEBCTM from 2000 to 2005 and since 2005 has been a member of the technicalcommittee of the IEEE ISSCC. He is a member of the IEEE and IEICE.

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