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FPGAsField Programmable Gate Arrays
1Subhash Iyer
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FPGAsGeneral
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Why choose an FPGA?
3
The choice depends on design
requirements / cost / availability
Excuse the old data please Subhash Iyer
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Understanding the FPGA
Gate Array
Programmable
Field
Field : “in the field”
Programmable : “Re-Configurable” Change Logic Functions
Gate Array : reference to ASIC internal architecture
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What is an FPGA?
Field Programmable Gate Array
(Very) Large Scale Integrated Circuit
Digital Logic
Programmed after manufacture rather than
unchangeable Application Specific Integrated
Circuit ASIC
First appeared in 1980’s.
Standard IC manufacturing process
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Why are they of Interest?
Essential Components in modern Electronics (&
Industry!)
◦ Data Acquisition (Millions Channels)
◦ Triggers
◦ Computer Interfaces
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When to use an FPGA?
Options:
◦ Microcontrollers and processors
When a function is dedicated
When decision making is protocol based
When multiple chips interact between themselves
When NOT to use and FPGA???
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What is an FPGA?
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Field Programmable Gate Array
◦ Configurable (Programmable) General Logic Blocks
◦ Configurable Interconnects
◦ Plus Special Purpose Blocks (Embedded Processors)
◦ Configured (multiple times) to perform variety of tasks
Simple Logic Block ‘Islands’ in a ‘Sea’ of Interconnects
Programmable
interconnect
Programmable
logic blocks
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Little bit of History…
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FPGAs appeared in the 1980’s.
Bridge gap between simple Programmable
Logic and semi custom ASICs (Application
Specific Integration Circuits).
PLDs ASICs
Standard Cell
Full Custom
Gate Arrays
Structured ASICs*
SPLDs
CPLDs
*Not available circa early 1980s
The
GAP
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ASICs
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Large Complex Functions
Customised for Extremes of Speed, Low Power,
Radiation Hard
(Very) Expensive (in small quantities) @ 90 nm ~ $1M
mask set
(Very) Hard to Design.
Long Design cycles.
Not Reprogrammable. High Risk.
Semi Custom Gate Arrays.ASICs
Structured
ASICs
Gate
Arrays
Standard
Cell
Full
Custom
Increasing complexity
(a) Single-column arrays (b) Dual-column arrays
I/O cells/pads
Channels
Basic cells
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FPGAs best of both worlds…
11
Large Complex
Functions
Programmability,
Flexibility.
Massively Parallel
Architecture
Fast Turnaround
Designs
Mass produced. Cheap
Prototype ASICs
Power Hungry
PLDs ASICs
Standard Cell
Full Custom
Gate Arrays
Structured ASICs*
SPLDs
CPLDs
*Not available circa early 1980s
The
GAP
Programmable
interconnect
Programmable
logic blocks
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Common FPGA Characteristics
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Logic Elements
◦ Lookup Table /
AND-OR implementation
◦ Flip Flops
◦ Multiplexers
Memory Resources
◦ SRAM blocks
Routing Resources
◦ Hierarchy Programmable Channels between Logic Elements
Configurable I/O
◦ Interfaces to the real world. Logic Levels. Fast Serial I/O
Massively Parallel Architecture
Clocked Logic Design
CMOS based using SRAM cells for configuration
Programmable
interconnect
Programmable
logic blocks
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Common FPGA Characteristics
Field Programmable Gate Arrays
(FPGA) can handle larger circuits
◦No AND/OR planes
◦ Provide logic blocks, I/O blocks, and
interconnection wires and switches
◦ Logic blocks provide functionality
◦ Interconnection switches allow logic
blocks to be connected to each other
and to the I/O pins
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Structure of an FPGA
The elements of an FPGA structure are:◦ Logical Building Block: ROM type, PLA/PAL type,
LUT type
◦ Interconnect Mechanism: Transistors, fuses, matrix, bus
◦ I/O block: Latched, buffered, additional logic
◦ Other features: RAM
Depends on the manufacturer
Each method has its pros and cons
Can you propose a structure???
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FPGAsHalf-way Through !!!
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FPGAStructure and construction
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Structure of an FPGA
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I/O block
I/O block
I/O b
lock I/
O b
lock
logic block
interconnection
switch
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Structure of an FPGA
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I/O block
I/O block
I/O b
lock I/
O b
lock
logic block
interconnection
switch
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Structure of an FPGA
Closer look
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Structure of an FPGA: Xilinx
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Blo
ck R
AM
s
Blo
ck R
AM
s
Configurable
Logic
Blocks
I/O
Blocks
Block
RAMs
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Xilinx CLBs:
Look Up Tables (LUTs) Logic blocks are
implemented using a lookup table (LUT)
◦ Small number of inputs, one output
◦ Contains storage cells that can be loaded with the desired values
◦ A 2 input LUT uses 3 MUXesto implement any desired functionof 2 variables
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f
0/1
0/1
0/1
0/1
x 1
x 2 Subhash Iyer
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Xilinx CLBs:
Look Up Tables (LUTs) Example 2 Input LUT
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x1 x2 f
0 0 1
0 1 0
1 0 0
1 1 1 f
1
0
0
1
x 1
x 2
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Xilinx CLBs:
Look Up Tables (LUTs) 3 Input LUT
◦ 7 2x1 MUXes and
8 storage cells are
required
◦ Commercial LUTs have
4-5 inputs, and 16-32
storage cells
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f
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
x 2
x 3
x 1
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Xilinx: FPGA CLBs
Making a LUT on an FGPA
Adding a sequential element
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Xilinx: FPGA CLBs
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Making a LUT on an FGPA
Adding a sequential element
Making it programmable
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Xilinx: FPGA CLBs
Newer implementation
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FPGA CLBs: Altera
Uses a Macrocell
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Clk
MUX
Output
MUXQ
F/B
MUX
Inv ert
Control
AND
ARRAY
CLK
pad
8 Product Term
AND-OR Array
+Programmable
MUX's
Programmable polarity
I/O Pin
Seq. LogicBlock
Programmable feedback
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FPGA CLBs: Altera
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Newer implementation
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Structure of an FPGA
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I/O block
I/O block
I/O b
lock I/
O b
lock
logic block
interconnection
switch
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FPGA – CLBs
How they are used!!! CLBs can be configured to
implement Boolean functions
Typically CLBs have between
4-6 inputs
Functions of larger number of
variables use more than one
CLB.
CLB typically contains 1 or 2
FFs for sequential logic.
Large designs are partitioned
and mapped to a number of
CLBs with each CLB
configured (programmed) to
perform a particular function.
CLBs are then interconnected
to implement target design. 30Subhash Iyer
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FPGA – Beyond the CLBs
Interconnects 3 programmable
routing resources:
For flexible
interconnection
of CLBs,
◦ Vertical and
Horizontal
Channels
◦ Connection Boxes
◦ Switch Boxes
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FPGA Interconnects: Channels
Vertical and
horizontal routing
channels
Different length
wires that can be
connected together
if needed.
Run vertically and
horizontally between
columns and rows of
CLBs
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Channel Architecture
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Channeled Routing Structure
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Programmed
Antifuse
Horizontal
Track
Vertical Track
Modules
Unprogrammed
Antifuse
Modules
Horizontal Control
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FPGA Interconnects: Connection
Boxes Programmable
links
Connect input
and output of
the CLBs to
wires of the
vertical or the
horizontal
routing channels.
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FPGA Interconnects: Switch Boxes
Located at intersections of vertical and horizontal channels
Programmable links
Used to connect wire segments in the horizontal and vertical channels
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Programmable Switch Matrix
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programmable switch element
turning the corner, etc.
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FPGA Interconnects: Switch Boxes -
Xilinx
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Interconnect Structure
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Structure of an FPGA
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I/O block
I/O block
I/O b
loc
k I/
O b
lock
logic block
interconnection
switch
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FPGA IO Blocks
Mainly buffers
Can be configured either as input buffers, output buffers or input/output buffers.
Allow pins of the FPGA chip to function either as input pins, output pins or input/output pins
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Basic I/O Block Structure
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D
EC
Q
SR
D
EC
Q
SR
D
EC
Q
SR
Three-StateControl
Output Path
Input Path
Three-State
Output
Clock
Set/Reset
Direct Input
Registered Input
FF Enable
FF Enable
FF Enable
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FPGA IO Block example: Xilinx
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FPGAProgramming
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What to Program???
CLBs: Need to fix the inputs to the LUT /
AND-OR array and the sequential logic
Interconnects: Need to fix the inputs of
the switches which connect the various
elements
IO Blocks: Need to fix the configuration
of the pins as input / output / input-
output or tristate / bistate
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How to Program
A memory element behind every
programmable element
This memory element is set to a
particular value 1/ 0 while programming
The entire memory is made as a serial
shift register
During configuration, a bit stream is sent
to this complete shift register which
becomes the program
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Programmable element
A FET which acts as a switch
A memory element (depicted here as an SRAM cell) for each switch
Input at the switch determines the connection of the lines
1 of the switch means connection is made else not made.
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Programming the CLB
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Connection
Switch
Transmission
Gate
LUT
CLB
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Programming (Configuring) an
FPGA SRAM cells holding
configuration are Volatile Memory
Lose configuration when board power is turned off.
Keep Bit Pattern describes the Logic Functions in non-Volatile Memory e.g. ROM or Compact Flash card
Reprogramming takes ~ secs
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Configuration data in
Configuration data out
= I/O pin/pad
= SRAM cell
SRAM
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Methods
Serial communication
JTAG : Joint Test Action Group – most
commonly adopted standard
Serial port
USB
ISP feature: In-circuit programmable
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FPGAImplementation Example
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Example FPGA: 1
Use an FPGA with 2 input LUTS to
implement the function f = x1x2 + x2'x3
◦ f1 = x1x2
◦ f2 = x2'x3
◦ f = f1 + f2
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0
1
0
0
0
1
1
1
0
0
0
1
x 1
x 2
x 2
x 3
f 1
f 2
f 1 f 2
f
x 1
x 2
x 3 f
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FPGADesign Flow
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Design Steps
• Understand and define design
requirements
• Design description
• Behavioural simulation
(Source code interpretation)
• Synthesis
• Functional or Gate level
simulation
• Implementation
• Fitting
• Place and Route
• Timing or Post layout
simulation
• Programming, Test and Debug
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Design process
55
Design and implement a simple unit permitting to
speed up encryption with RC5-similar cipher with
fixed key set on 8031 microcontroller. Unlike in
the experiment 5, this time your unit has to be able
to perform an encryption algorithm by itself,
executing 32 rounds…..
Library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity RC5_core is
port(
clock, reset, encr_decr: in std_logic;
data_input: in std_logic_vector(31 downto 0);
data_output: out std_logic_vector(31 downto 0);
out_full: in std_logic;
key_input: in std_logic_vector(31 downto 0);
key_read: out std_logic;
);
end AES_core;
Specification (Lab Experiments)
VHDL description (Your Source Files)
Functional simulation
Post-synthesis simulationSynthesis
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Design process
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Implementation
Configuration
Timing simulation
On chip testing
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FPGA Generic Design Flow
Design Entry◦ Create Design Schematic / HDL
Design Implementation◦ Partition
◦ Place
◦ Route
Design Verification◦ Simulation
◦ Physical in-circuit testing Using logic analyser
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Design Implementation
Partitioning
◦ Breaking up the design to fit into the nature of CLBs
◦ In other work making the design into LUTs and FFs
Placement
◦ Choosing the right CLBs to locate the design on
◦ Based on proximity to IOBs, delay constraints, area constraints, etc
◦ Achieve wiring minimization
Routing
◦ Choice of interconnect
◦ Based on timing constraints
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Circuit Compilation
59
LUT
LUT
?
Assign a logical
LUT to a physical
location.
Select wire segments
And switches for
Interconnection.
1. Partitioning / Technology Mapping
2. Placement
3. Routing
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Example
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Programmable Connections
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FPGATechnology Aspects
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Programmable Elements Overview
Antifuse
◦ ONO and Metal-to-Metal (M2M)
◦ Construction
◦ Resistance
SRAM
◦ Structure
◦ Quantity
EEPROM/Flash
Ferroelectric Memory
Summary of Properties
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Antifuse Technology
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ONO Antifuse (Actel)
Poly/ONO/N++
Heavy As doped Poly/N++
Thickness controlled by
CVD nitride
Programs ~ 18V
Typical Toxono ~ 85 Å
Hardened Toxono ~ 95 Å
R = 200 - 500 ohms
thermal oxide
CVD nitride
thermal oxide
FOX
N++
Polysilicon
ONO
Metal-to-Metal Antifuse
(Actel, UTMC, Quicklogic)
‘Pancake’ Stack Between Metal Layers
Used in 3.3V Operation in Sea Of Gates FPGA
Other devices (as shown later)
Program at ~ 10V
Typical thickness ~ 500 - 1000 Å
R = 20 - 100 ohms
Metal - 3 Top Electrode
Amorphous Silicon
Dielectric (optional)
Metal - 2 Bottom Electrode
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Antifuse Cross-Sections
64
Amorphous Silicon
(Vialink)ONO
(Act 1)
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M2M Antifuse in
Multi-layer Metal Process
65
M2M = Metal-to-metal
SX, SX-A, and SX-S Vialink
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Switch Technology
Memory behind the switch could be
◦ SRAM
◦ EEPROM
◦ Flash
66
Read or Write
Data
Configuration Memory Cell
Routing Connections
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Other technologies
EEPROM
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FPGAQuestions???
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WELCOME TO THE FPGA
WORLD
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Example FPGA: 1
Use an FPGA with 2 input LUTS to
implement the function
◦ f1 = x1x2
◦ f2 = x2'x3
◦ f = f1 + f2
1
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S2
f1 = x1x2, f2 = x2'x3, f = f1 + f2
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f1 = x1x2, f2 = x2'x3, f = f1 + f2
x 1
x 2
x 3 f
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f1 = x1x2, f2 = x2'x3, f = f1 + f2
x 1
x 2
x 3 f
x 1
x 2
f
x 2
3
f 1
f 2
f
f
1 2
x
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S5
f1 = x1x2, f2 = x2'x3, f = f1 + f2
x 1
x 2
x 3 f
0 0 0 1
x 1
x 2
f
0 1 0 0
0 1 1 1
x 2
x 3
f 1
f 2
f
f
1 2
S
O
F
T
P
O
L
Y
N
O
M
I
A
L
S6
0 1 0 0
0 1 1 1
0 0 0 1
x 1
x 2
x 2
x 3
f 1
f 2
f 1 f 2
f
x 1
x 2
x 3 f
f1 = x1x2, f2 = x2'x3, f = f1 + f2
S
O
F
T
P
O
L
Y
N
O
M
I
A
L
S7
0 1 0 0
0 1 1 1
0 0 0 1
x 1
x 2
x 2
x 3
f 1
f 2
f 1 f 2
f
x 1
x 2
x 3 f
f1 = x1x2, f2 = x2'x3, f = f1 + f2
S
O
F
T
P
O
L
Y
N
O
M
I
A
L
S8
0 1 0 0
0 1 1 1
0 0 0 1
x 1
x 2
x 2
x 3
f 1
f 2
f 1 f 2
f
x 1
x 2
x 3 f
f1 = x1x2, f2 = x2'x3, f = f1 + f2
S
O
F
T
P
O
L
Y
N
O
M
I
A
L
S9
0 1 0 0
0 1 1 1
0 0 0 1
x 1
x 2
x 2
x 3
f 1
f 2
f 1 f 2
f
x 1
x 2
x 3 f
f1 = x1x2, f2 = x2'x3, f = f1 + f2
S
O
F
T
P
O
L
Y
N
O
M
I
A
L
S10
0 1 0 0
0 1 1 1
0 0 0 1
x 1
x 2
x 2
x 3
f 1
f 2
f 1 f 2
f
x 1
x 2
x 3 f
f1 = x1x2, f2 = x2'x3, f = f1 + f2
S
O
F
T
P
O
L
Y
N
O
M
I
A
L
S11
0 1 0 0
0 1 1 1
0 0 0 1
x 1
x 2
x 2
x 3
f 1
f 2
f 1 f 2
f
x 1
x 2
x 3 f
f1 = x1x2, f2 = x2'x3, f = f1 + f2
S
O
F
T
P
O
L
Y
N
O
M
I
A
L
S12
0 1 0 0
0 1 1 1
0 0 0 1
x 1
x 2
x 2
x 3
f 1
f 2
f 1 f 2
f
x 1
x 2
x 3 f
f1 = x1x2, f2 = x2'x3, f = f1 + f2
Slide 1Subhash Iyer, Program Head, Soft Polynomials (I) Pvt. Ltd
Field Programmable Gate Arrays
A Comparison of available devices
Slide 2Subhash Iyer, Program Head, Soft Polynomials (I) Pvt. Ltd
FPGAs
Consists of uncommitted logic arrays and user
programmable interconnection.
The interconnect programming is done through
programmable switches
The Logic circuits are implemented by partitioning
the logic into blocks and then interconnecting the
blocks with the programmable switches
The architecture of an FPGA varies from device to
device , vendor to vendor it can be based on CPLDs,
EPROMS, EEPROMS, LUT, Buses, PALS
The interconnect is also varied from EPROM, static
RAM, antifuse, EEprom
Slide 3Subhash Iyer, Program Head, Soft Polynomials (I) Pvt. Ltd
FPGA Classification
Implementation
Architecture
Logic
Implementation
Interconnect
Technology
Symmetrical
Array
Row based Array
Hierarchial PLD
Sea of Gates
Look Up table
Multiplexer
based
PLD Block
NAND Gates
Static Ram
Antifuse
E/EPROM
FPGA types
Slide 4Subhash Iyer, Program Head, Soft Polynomials (I) Pvt. Ltd
Classes of Common Commercial FPGAs
Row-basedInterconnect
Logic Block
PLD BlockInterconnectoverlayed on LogicBlocks
Logic Block
Interconnect
Sea-of-GatesHierarchical PLD
Interconnect
Symmetrical Array
Various Block Architecture & Routing Architecture
Slide 5Subhash Iyer, Program Head, Soft Polynomials (I) Pvt. Ltd
ACTEL (Now MicroSemi) FPGA
ACT1 module has three 2:1 Muxs with AND-OR logic
at the select of final MUX and implements all 2 input
functions, most 3 input and many 4 input functions.
Apart from variety of combinational logic functions,
the ACT1 module can implement sequential logic cells
in a flexible and efficient manner. For example an
ACT1 module can be used for a transparent Latch or
two modules for a flip flop.
Slide 6Subhash Iyer, Program Head, Soft Polynomials (I) Pvt. Ltd
General Architecture of Actel FPGAs
I/O Blocks
I/O Blocks
LogicModule Rows
I/O BlocksI/O Blocks
Channel Routing
SAA0 A1
B0 B1 SB
S1
Y
S0
ACT-1 Logic Module
Slide 7Subhash Iyer, Program Head, Soft Polynomials (I) Pvt. Ltd
ACT 1 Programmable Interconnect
Architecture
The basic Architecture of Actel FPGA consists of rows of programmable
block with horizontal routing channels between the rows.
Each routing switch in these FPGAs is implemented by the PLICE Anti fuse.
LMLMLMLMLM
LMLMLMLMLM
Input Segment
Wiring Segment
Anti fuse
Clock Track VerticalTrack
Connections are all and orbut shown only in this section
for clarity
Slide 8Subhash Iyer, Program Head, Soft Polynomials (I) Pvt. Ltd
Slide 9Subhash Iyer, Program Head, Soft Polynomials (I) Pvt. Ltd
Slide 10Subhash Iyer, Program Head, Soft Polynomials (I) Pvt. Ltd
ACT 1 and ACT 3 Logic Modules
ACT1 module is simple logical block. It does not
have built in function to generate a Flip Flop.
Although it can generate a FF if required.
ACT2 and ACT3 that has separate FF module is used
for Sequential Circuits.
Slide 11Subhash Iyer, Program Head, Soft Polynomials (I) Pvt. Ltd
Timing Models and Critical Paths
Exact timing (delays) on any FPGA chip cannot be
estimated until place and routing step has been
performed. This is due to the delay of the interconnect.
A critical path of SE in is shown on the next slide.
Slide 12Subhash Iyer, Program Head, Soft Polynomials (I) Pvt. Ltd
Actel ACT3 Timing Model
Slide 13Subhash Iyer, Program Head, Soft Polynomials (I) Pvt. Ltd
Anti-Fuse (ACTEL)
An anti fuse is normally an open circuit until a programming
current is forced though it (about 5mA).
The two prominent methods are Poly to Diffusion (Actel) and
Metal to Metal (Via Link). In a Poly-diffusion anti fuse the high
current density causes a large power dissipation in a small area.
Anti fuse Polysilicon
n+ Diffusion
Dielectric
2 λ
Anti fuse Polysilicon
Anti fusePolysilicon
Anti fuse
n+ anti fuse diffusion
Contact
The actual anti fuse link is less than 10nm x 10nm
Slide 14Subhash Iyer, Program Head, Soft Polynomials (I) Pvt. Ltd
Anti-Fuse (ACTEL)
This will melt a thin insulating dielectric between polysilicon and diffusion and form
a thin
(about 20nm in diameter) permanent, and resistive silicon link. The programming
process also
drives dopand atoms from the poly and diffusion electrodes. The fabrication process
and
Programming current controls the average resistance of blown anti fuses.
Actel Device # of Anti fuses
A1010 112,000
A1225 250,000
A1280 750,000
To design and program an Actel FPGA, designers iterate between design entry and
simulation when design is verified both by functional and timing tests. Chip is
plugged into a socket on a special programming box that generates the programming
voltage.
250 500 750 1000
Anti fuse Resistance in Ω
% Blown Anti fuses
Slide 15Subhash Iyer, Program Head, Soft Polynomials (I) Pvt. Ltd
Anti-Fuse (ACTEL)
Metal-Metal Anti fuse (Via Link) Same principle as previous slide but different process with 2 main advantages
1) Direct metal to metal eliminating connection between poly and metal or diffusion to
metal thus reducing parasitic capacitance and interconnect space requirement.
2) Lower resistance.
Anti fuse
Routing wiresRouting wires
M3M2
Thin amorphous Si
M3
4λ
M2
4λ
2λ50 80 100
Anti fuse Resistance Ω
% Blown Anti fuses
Slide 16Subhash Iyer, Program Head, Soft Polynomials (I) Pvt. Ltd
EPROM and EEPROM
Altera MAX 5K and Xilinx ELPDs both use UV-erasable “electrically
programmable read-only memory” (EPROM) cells as their programming
technology. The EPROM cell is almost as small as an anti fuse.
GroundS D
G2
G1
S D
G2
G1+Vgs>Vtn
+Vpp
+Vgs>Vtn
Vds
No channel
G2
G1
UV light
Slide 17Subhash Iyer, Program Head, Soft Polynomials (I) Pvt. Ltd
EPROM and EEPROM
Altera MAX 5K and Xilinx ELPDs both use UV-erasable “electrically
programmable read-only memory” (EPROM) cells as their programming
technology. The EPROM cell is almost as small as an anti fuse.
An EPROM looks like a normal transistor except it has a second floating
gate.
(a) Applying a programming voltage Vpp (>12) to the drain of the n-channel,
programs the cell. A high electric field causes electrons flowing towards the
drain to move so fast they “jump” across the insulating gate oxide where
they are trapped on the bottom of the floating gate.
(b) Electrons trapped on the floating gate raise the threshold voltage. Once
programmed an n-channel EPROM remains off even with Vdd applied to the
gate. An unprogrammed n-channel device will turn on as normal with a top-
gate voltage Vdd.
(c) Exposure to an ultra-violet (UV) light will erase the EPROM cell. An
absorbed light quantum gives an electron enough energy to jump for the
floating gate.
Slide 18Subhash Iyer, Program Head, Soft Polynomials (I) Pvt. Ltd
EPROM and EEPROM
EPLD package can be bought in a windowed package
for development, erase it and use it again.
Programming EEPROM transistors is similar to
programming an UV-erasable EPROM transistor, but
the erase mechanism is different.
In an EEPROM transistor and electric field is also
used to remove electrons from the floating gate of a
programmed transistor.
This is faster than the UV-procedure and the chip
doesn’t have to removed from the system.
Slide 19Subhash Iyer, Program Head, Soft Polynomials (I) Pvt. Ltd
EEPROM
Creating a wired-AND with EPROM cells [3]
Structure of a FAMOS transistor [3]
F= A + B + C + D + …….= A . B . C . D . ……..
First Level Polysilicon
Second Level Polysilicon
Field OxideGate Oxide
Slide 20Subhash Iyer, Program Head, Soft Polynomials (I) Pvt. Ltd
General Structure of Altera FPGAs
8-input fracturable look-up table (LUT) with
the Stratix® II family in 2004
At its core is the adaptive logic module (ALM)
with 8 inputs
Can implement a full 6-input LUT (6-LUT) or
select 7-input functions
ALM can also be efficiently partitioned into
independent smaller LUTs
Performance advantage of larger LUTs and
the area efficiency of smaller LUTs
Slide 21Subhash Iyer, Program Head, Soft Polynomials (I) Pvt. Ltd
Logic Fabric
High-performance, area-efficient
architecture is the ALM
Combinational portion has eight inputs
Includes a LUT that can be divided between
two adaptive LUTs (ALUTs)
Entire ALM is needed to implement an
arbitrary six-input function
But because it has eight inputs to the
combinational logic block, one ALM can
implement various combinations of two
functions.
Slide 22Subhash Iyer, Program Head, Soft Polynomials (I) Pvt. Ltd
Logic Fabric
Slide 23Subhash Iyer, Program Head, Soft Polynomials (I) Pvt. Ltd
Adaptive Logic Module
In addition to implementing
a full 6-input LUT, the ALM
can, for example,
implement 2 independent
4-input functions or a 5-
input and a 3-input function
with independent inputs.
Because 2 registers and 2
adders are available, the
ALM has the flexibility to
implement 2.5 logic
elements (LEs) of a classic
4-input LUT (4-LUT)
architecture, consisting of
a 4-LUT, carry logic, and a
register
Slide 24Subhash Iyer, Program Head, Soft Polynomials (I) Pvt. Ltd
ALM Flexibility
Slide 25Subhash Iyer, Program Head, Soft Polynomials (I) Pvt. Ltd
ALM Flexibility
Slide 26Subhash Iyer, Program Head, Soft Polynomials (I) Pvt. Ltd
ALM Flexibility
Slide 27Subhash Iyer, Program Head, Soft Polynomials (I) Pvt. Ltd
ALM Block diagram
Slide 28Subhash Iyer, Program Head, Soft Polynomials (I) Pvt. Ltd
Comparing Stratix-II and Virtex-5
8 input block
supports all 6-
input functions
other
combinations of
smaller functions
6 input block
Smaller additional
logic
Slide 29Subhash Iyer, Program Head, Soft Polynomials (I) Pvt. Ltd
Logic Array Blocks (LAB) and
Interconnects
Slide 30Subhash Iyer, Program Head, Soft Polynomials (I) Pvt. Ltd
FPGA Comparison Table
Slide 31Subhash Iyer, Program Head, Soft Polynomials (I) Pvt. Ltd
FPGA Comparison Table
Company General
Architecture
Logic Block
Type
Programming Technology
Xilinx Symmetrical Array Look-up Table Static RAM
Actel Row-based Multiplexer-Based Anti-fuse
Altera Hierarchical-PLD PLD Block EPROM
Plessey Sea-of-Gates NAND-gate Static RAM
PLUS Hierarchical-PLD PLD Block EPROM
AMD Hierarchical-PLD PLD Block EEPROM
QuickLogic Symmetrical Array Multiplexer-Based Anti-fuse
Algotronix Sea-of-gates Multiplexers & Basic Gate Static RAM
Concurrent Sea-of-gates Multiplexers & Basic Gate Static RAM
Crosspoint Row-based Transistors Pairs &
Multiplexers
Anti-fuse
Slide 32Subhash Iyer, Program Head, Soft Polynomials (I) Pvt. Ltd
Critical Condition !!!
FPGA Overdose
Need a Chai Break
and a NEW Topic
