Upload
tasos1970
View
422
Download
1
Embed Size (px)
Citation preview
1
FPGAs in Digital Communications
Dr Chris DickDSP Chief ArchitectDirector, Signal Processing Engineering
Channelization 2
Digital Comm Examples
• Channelized receiver to support– QAM– OFDM
• Examine– Channelizer implementation– QAM demodulator architecture– OFDM modulator/demodulator
Proceeding of the SDR 03 Technical Conference and Product Exposition. Copyright © 2003 SDR Forum. All Rights Reserved
2
Channelization 3
Passband Polyphase Filters
• In a FDM digital communication system a common requirement is, for each channel:– translate the channel to baseband– shape the channel spectrum– reduce the sample rate to match the channel bandwidth
• This is the function of a channelizer• When the channel spacing is equal a computationally efficient
structure for performing the above functions is the carrier centered polyphase transform
f
( )S f
cf cf cf cfcf
channels
Channelization 4
Baseband Polyphase Filter
0 ( )h n
1( )h n
2 ( )h n
1( )Mh n−
( )x n( )y Mn
0 0
1 1 1 1
1 1 2 1 1
( )( )
( )
M N M
M N M
M M M N
h n h h hh n h h h
h n h h h
−
+ − +
− − − −
==
=
!!
" " " ! "!
Proceeding of the SDR 03 Technical Conference and Product Exposition. Copyright © 2003 SDR Forum. All Rights Reserved
3
Channelization 5
Passband Polyphase Filters
1 2
1 2 1 2( ) ( ) 0, , 1, 0, , 1
Express the filter coefficient set in terms of a course and vernier index and respectively
= =
r rNh n h r Mr r M rM
= + − −… …
Invoke the modulation theorem to convert a prototype baseband filter to its equivalent carrier centered, or spectrally shifted version
00
( ) ( )
( ) ( )
if then
j n
h n Hh n e Hθ
θθ θ
⇔
⇔ −
Channelization 6
Passband Polyphase Filters
0( ) ( )The coefficients of the carrier centered filter are
j ng n h n e θ=
θππ− 0θ
| ( ) |H θ | ( ) |G θ
0 1 2
1
0 1 0 2
( )2 1 2
1 2
( ) ( )
( )
Now perform a polyphase partition on the modulated coefficients
j r Mrr
j r j Mr
g r h r Mr e
h r Mr e e
θ
θ θ
+= +
= +
00Select so that a single period of the series is harmonically
related to
j neM
θθ
Proceeding of the SDR 03 Technical Conference and Product Exposition. Copyright © 2003 SDR Forum. All Rights Reserved
4
Channelization 7
Passband Polyphase Filters
20 1
1
1
0
2
2 1 2
2
1 2
2
( ) ( )
( )
jk Mrj r Mr
jk rM
kM
g r h r Mr e e
h r Mr e
πθ
π
πθ =
= +
= +
0 ( )h n
1( )h n( )x n
( , )y Mn k
1 kje θ
0 kje θ
2 ( )Mh n−
( 2) kj Me θ−
1( )Mh n−
( 1) kj Me θ−
Carrier centered polyphase filterthe one structure
• Translates the channel to baseband• Shapes the signal• Reduces the sample rate
Channelization 8
Passband Polyphase Filters
0 ( )h n
1( )h n
( )x n
( , )y Mn k
1 kje θ
0 kje θ
2 ( )Mh n−
( 2) kj Me θ−
1( )Mh n−
( 1) kj Me θ−
0 ( )h n
1( )h n( ,0)y Mn
2 ( )Mh n−
1( )Mh n−
Recovering 2 channels from FDM spectraThe two sets of filters employ identical coefficientsNote: the two sets of filters contain the same data
Proceeding of the SDR 03 Technical Conference and Product Exposition. Copyright © 2003 SDR Forum. All Rights Reserved
5
Channelization 9
Polyphase Transform
0 ( )h n
1( )h n( )x n
( , 0)y Mn
2 ( )Mh n−
1( )Mh n−
M-PointIDFT
( ,1)y Mn
( , 2)y Mn M −
( , 1)y Mn M −
12 /
0
( )
( ) ( ) 0,1, , 1
Recall that the IDFT of an -point sequence is
M
j nk M
k
M Y k
y n Y k e n Mπ−
=
= = −∑ …
If the phase rotators are sequenced over all of the values of we recognize that this is the same as computing an IDFT
M M k
Channelization 10
Channelizer Filter Bank
-0 .5 0 0.5-80-60-40-20
0
Fre que ncy
dB
-0 .06 -0.04 -0.02 0 0 .02 0 .04 0.06-60
-40
-20
0
Fre que ncy
dB
Proceeding of the SDR 03 Technical Conference and Product Exposition. Copyright © 2003 SDR Forum. All Rights Reserved
6
Channelization 11
Phase Response of Paths in Ten Stage Polyphase Filter
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5-9
-8
-7
-6
-5
-4
-3
-2
-1
0S pectra l P has e Res pons e of Ten P olyphas e Filte rs
Normaled Frequency (f/fs )
Nor
mal
ized
Pha
se ( φ
/2π)
Channelization 12
Group Delay of Paths in Ten-Stage Polyphase Filter
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5-9
-8.8
-8.6
-8.4
-8.2
-8
-7.8
-7.6
-7.4
-7.2
-7Spectra l Group Delay Res pons e of Ten Polyphas e Filters
Normaled Frequency (f/fs )
Nor
mal
ized
Del
ay ( ∆
T/T
s)
Proceeding of the SDR 03 Technical Conference and Product Exposition. Copyright © 2003 SDR Forum. All Rights Reserved
7
Channelization 13
40 Channel Polyphase Receiver
010
2030
4050
6070
8090
100
0
5
10
15
20
25
30
35
40
0
0.2
0.4
0.6
0.8
tim e
c e nte r fre que nc y
mag
nitu
de
Time Series Waterfall from 40-Channel Polyphase Receiver
Channelization 14
Channelized Receiver Example
• Design a channelized receiver
f
( )X f
cf cf cf cfcf
channels
sample rate fs = 100 MHz, 12b samples16 channelsM-ary QAM modulationconcatenated decoder
Filter requirements60 dB stopband ripple0.2 dB passband ripple6.25 MHzcf =
Proceeding of the SDR 03 Technical Conference and Product Exposition. Copyright © 2003 SDR Forum. All Rights Reserved
8
Channelization 15
Polyphase Channelizer
ADC
VCO
0 ( )h n
1( )h n( )x n
2 ( )Mh n−
1( )Mh n−
M-PointIDFT
Receiver 0
Receiver 1
Receiver M-2
Receiver M-1
Matched Filter Equalizer Det FEC
DecPrivacy
DecSource
Dec
Timing Recovery
Carrier Recovery
RS DecViterbiDec Deint.
Receiver n
Channelization 16
Channelizer Filter Design
PdB = 0.2 dB
AdB = 60 dB
f
|H(f)|fs = 100 MHz
• Design the prototype filter
0.0250pf = 0.0375sf =0.0375 0.0250 0.0125f∆ = − =
Filter length approximation due to Prof. fred harrisSan Diego State University
221 60 219
0.0125 22
dBsf ANf
≈ ⋅∆
= ⋅ =
Proceeding of the SDR 03 Technical Conference and Product Exposition. Copyright © 2003 SDR Forum. All Rights Reserved
9
Channelization 17
Channelizer Implementation
ChannelizerInput
Stimulus
Capture data to Matlab workspace for post analysis/display
Channelization 18
System Generator Implementation
1:16 decimator
Polyphase Filter partition
Re-assemble filter outputs onto TDM bus for presentation to FFT
quantize
Physical level module generator is used to produce a highly efficient FPGA implementation of each block
Proceeding of the SDR 03 Technical Conference and Product Exposition. Copyright © 2003 SDR Forum. All Rights Reserved
10
Channelization 19
System Generator Implementation
Channelization 20
System Generator Implementation
Proceeding of the SDR 03 Technical Conference and Product Exposition. Copyright © 2003 SDR Forum. All Rights Reserved
11
Channelization 21
Filter Module
Channelization 22
System Generator Implementation-The Hardware Over-Sampling Rate (folding factor) field of the FIR filter block allows the designer to tradeoff throughput with FPGA area
-The filter throughput is fclk/R where R is the Hardware Over-Samlping Rate and fclk is the filter clock rate … which is not necessarily the same as the filter sample rate
-When R=1 a new filter output is generated on each clock cycle
-For R=2 a new output is generated every second clock cycle
-With this control the designer can realize a filter that best matches the requirements of the system
Proceeding of the SDR 03 Technical Conference and Product Exposition. Copyright © 2003 SDR Forum. All Rights Reserved
12
Channelization 23
System Generator Implementation
• In this design the input sample rate is 100 MHz (12b samples)
• The sample rate presented to each filter in the filter bank is 100e6/16 = 6.25 MHz
• The most efficient implementation for the filters is to employ a folding factor equal to the input sample precision
• The filters will be clocked at a frequency of 12 x 6.25e6 = 75 MHz
• The digital clock manager (DCM) can be used to generate the various clock frequencies
Channelization 24
System Generator Implementation
An FFT Core highly optimized for the FPGA is used in the design
Proceeding of the SDR 03 Technical Conference and Product Exposition. Copyright © 2003 SDR Forum. All Rights Reserved
13
Channelization 25
Implementation Statistics• Distributed arithmetic implementation employed in this
example• Virtex-II Pro 2vp50-7
– Filter Bank: 6500 slices– fclk (max) = 200 MHz
• 448 mpys @ 200 MHz would be required to meet this performance using a MAC FIR approach
• Use right algorithm for the problem• Explore the FPGA/algorithmic design space
$ $ $ $62 16 14 200 90e× × × =
COMPLEX SUB FILTER LENGTHRE-SAMPLING RATIO CLOCKGMACs
Channelization 26
Channelized Receiver Example (2)
• Design a channelized receiver
– sample rate fs = 1 GHz, 12b samples– 16 channels– M-ary QAM modulation– concatenated decoder
f
( )X f
cf cf cf cfcf
channels
Proceeding of the SDR 03 Technical Conference and Product Exposition. Copyright © 2003 SDR Forum. All Rights Reserved
14
Channelization 27
Wide-Band Channelized Receiver
• In this case the challenge is to deliver the samples from the 1 Giga-sample/s ADC to the DSP engine
• Utilize the double data rate (DDR) capability of the Virtex-2 input/output blocks (IOBs)
• Use the DCM to generate the required clocks
Channelization 28
High-Speed 1GHz ADC
Proceeding of the SDR 03 Technical Conference and Product Exposition. Copyright © 2003 SDR Forum. All Rights Reserved
15
Channelization 29
ADC Timing
Channelization 30
1GHz ADC-FPGA Interface
DCM
D Q
D Q
D Q
D Q
ADCP0-P7
A0-A7
D Q
D Q
D Q
D Q
D Q
D Q
D Q
D Q
1 GHzsf =
2÷
DREADY 500 MHz
250 MHz250 MHz
D Q
D Q
D Q
D Q
D Q
D Q
D Q
D Q
125 MHz
DDR IOB
DDR IOB
Virtex-II FPGA
( )x t( 1)x n −
( 3)x n +
( 1)x n +
( 5)x n +
( )x n
( 4)x n +
( 2)x n +
( 6)x n +
P0-P7 = ADC Primary Data PortA0-A7 = ADC AUX Data PortDDR = Double Data Rate
Proceeding of the SDR 03 Technical Conference and Product Exposition. Copyright © 2003 SDR Forum. All Rights Reserved
16
Channelization 31
1 GHz Channelizer
• Each polyphase sub-filter must support a throughput of 1e9/16 = 62.5 Ms/s
• A 1 Giga-sample/s 16-point FFT is required
ADC
0 ( )h n
1( )h n( )x n
2 ( )Mh n−
1( )Mh n−
M-PointIDFT
Receiver 0
Receiver 1
Receiver M-2
Receiver M-1
1 GHzsf =
1 1 9 /16 62.5 MHzsf e= =
Channelization 32
Implementation Statistics• Filter bank arithmetic requirements
– 32 x 14 x 62.5e6 = 28 GMACs• Distributed arithmetic filters used for polyphase filter
bank– Hardware folding factor = 2
• Each subfilter is allocated a 2 clock cycle schedule to execute• Filter bank fclk = 2 x 1e9/16 = 125 MHz• 2vP50-6
– 11,155 slices 47% of the device• Interesting figure of merit: 28e9/11155 = 2.5 MMACs/logic slice
Proceeding of the SDR 03 Technical Conference and Product Exposition. Copyright © 2003 SDR Forum. All Rights Reserved
17
Channelization 33
1 Giga-sample FFT in System Generator
A very high-speed FFT is required for the channelizer1 Giga-samples/sBuilt in System Generator
Channelization 34
1 Gs/s FFT in System GeneratorButterfly network Radix-4 butterfly
4-point FFT kernel
Proceeding of the SDR 03 Technical Conference and Product Exposition. Copyright © 2003 SDR Forum. All Rights Reserved
18
Channelization 35
Implementation Statistics• Vectorized interface
– 1 vector delivered/produced each clock cycle• FPGA utilization
– 1,812 slices– 36 embedded multipliers
• In this design required FFT fclk = 62.5 MHz• One transform every 16 ns• FFT will support fclk = 210 MHz• 8 radix-4 dragonflies
– 64 complex additions• 128 x 210e6 = 26.9 GOPs/sec.
– 9 complex multiplications• 7.56 MMACs/sec.
Channelization 36
Modified Channelizer• Conventional polyphase transform channelizer
produces N maximally decimated output time series• Many comm systems like to operate on multiple
samples/symbol– e.g. many timing recovery loops in QAM demodulators
• Could interpolate each channelizer output time-series• Alternative modify channelizer to embed
(programmable) rate change
Proceeding of the SDR 03 Technical Conference and Product Exposition. Copyright © 2003 SDR Forum. All Rights Reserved
19
Channelization 37
With Arbitrary Uncoupled Selection of ...
fs
(P/Q)fs
(P/Q)fs
(P/Q)fs
(P/Q)fs
Low Pass
Low Pass
Low Pass
Low Pass
P:Q
P:Q
P:Q
P:Q
and channel sample rate
ChannelSpacing
channelbandwidth
On Multichannel Receivers
12 ( / )sj f f ne π
22 ( / )sj f f ne π
32 ( / )sj f f ne π
42 ( / )sj f f ne π
Channelization 38
Conventional Channelizer Application• Channelize• Downsample to Nyquist rate• Interpolate to two times symbol rate
Proceeding of the SDR 03 Technical Conference and Product Exposition. Copyright © 2003 SDR Forum. All Rights Reserved
20
Channelization 39
Enhanced Channelizer Solution
• Replace Interpolator Function With Buffer Addressing
Channelization 40
Performance Specifications for50-Channel Polyphase Channelizer
Proceeding of the SDR 03 Technical Conference and Product Exposition. Copyright © 2003 SDR Forum. All Rights Reserved
21
Channelization 41
Time and Frequency response of Remez Filter Design with Modified End
Points
0 100 200 300 400 500-0.005
0
0.005
0.01
0.015
0.02
0.025Impuls e Res pons e, P rototype Filter
-10 0 10 20 30 40 50 60-5
0
5
10x 10-4 Impuls e Res pons e, Detail
-30 -20 -10 0 10 20 30-80
-70
-60
-50
-40
-30
-20
-10
0
10
Normalized Frequency f/fChanne l
log
mag
nitu
de (d
B)
Frequency Respons e, P rototype Filter
Channelization 42
Commutators for Standard Input Buffer and for Circular Input Buffer
Proceeding of the SDR 03 Technical Conference and Product Exposition. Copyright © 2003 SDR Forum. All Rights Reserved
22
Channelization 43
Standard Polyphase Channelizer and Modified Channelizer with Circular
Buffers
Channelization 44
Shifting Time Origin for Input Data of Polyphase Filter and of Resetting FFT
Proceeding of the SDR 03 Technical Conference and Product Exposition. Copyright © 2003 SDR Forum. All Rights Reserved
23
Channelization 45
Content of 64-Point Circular Input Buffer for Two Successive 48 Point
Input Blocks
Channelization 46
Shifting Time Origin for Input Data of Polyphase Filter and of Resetting FFT
Proceeding of the SDR 03 Technical Conference and Product Exposition. Copyright © 2003 SDR Forum. All Rights Reserved
24
Channelization 47
Contents of Transfer Circular Buffer Aligning Origins for Successive Input Blocks
Channelization 48
Implementation
Proceeding of the SDR 03 Technical Conference and Product Exposition. Copyright © 2003 SDR Forum. All Rights Reserved
25
Channelization 49
Implementation Statistics
• 64 Channel channelizer• Arbitrary re-sampling
– 1000 slices– 5 embedded mpy– 6 block Virtex-II block memories
Proceeding of the SDR 03 Technical Conference and Product Exposition. Copyright © 2003 SDR Forum. All Rights Reserved