Design Examples-Digital System Designs and Practices Using Verilog HDL and FPGAs

Embed Size (px)

DESCRIPTION

Digital System Designs and Practices Using Verilog HDL and FPGAs Describe basic structures of µPsystemsUnderstand the basic operations of bus structures™Understand the essential operations of data transfer

Text of Design Examples-Digital System Designs and Practices Using Verilog HDL and FPGAs

  • Chapter 15: Design Examples

    Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-1

    Chapter 15: Design Examples

    Department of Electronic Engineering

    National Taiwan University of Science and Technology

    Prof. Ming-Bo Lin

  • Chapter 15: Design Examples

    Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-2

    Syllabus

    Objectives Bus Data transfer General-purpose input and output Timers Universal asynchronous receiver and transmitter A simple CPU design

  • Chapter 15: Design Examples

    Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-3

    Objectives

    After completing this chapter, you will be able to: Describe basic structures of P systems Understand the basic operations of bus structures Understand the essential operations of data transfer Understand the design principles of GPIOs Understand the design principles of timers Understand the design principles of UARTs Describe the design principles of CPUs

  • Chapter 15: Design Examples

    Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-4

    Syllabus

    Objectives Bus

    A p system architecture Bus structures Bus arbitration

    Data transfer General-purpose input and output Timers Universal asynchronous receiver and transmitter A simple CPU design

  • Chapter 15: Design Examples

    Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-5

    A Basic P System

  • Chapter 15: Design Examples

    Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-6

    Syllabus

    Objectives Bus

    A p system architecture Bus structures Bus arbitration

    Data transfer General-purpose input and output Timers Universal asynchronous receiver and transmitter A simple CPU design

  • Chapter 15: Design Examples

    Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-7

    Bus Structures

    Tristate bus using tristate buffers often called bus for short

    Multiplexer-based bus using multiplexers

  • Chapter 15: Design Examples

    Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-8

    A Tristate Bus

  • Chapter 15: Design Examples

    Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-9

    A Tristate Bus Example

    // a tristate bus examplemodule tristate_bus (data, enable, qout);parameter N = 2; // define bus widthinput enable;input [N-1:0] data;output [N-1:0] qout;wire [N-1:0] qout;

    // the body of tristate busassign qout = enable ? data : {N{1'bz}};endmodule

  • Chapter 15: Design Examples

    Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-10

    A Bidirectional Bus Example

    // a bidirectional bus examplemodule bidirectional_bus (data_to_bus, send, receive, data_from_bus, qout);parameter N = 2; // define bus widthinput send, receive;input [N-1:0] data_to_bus;output [N-1:0] data_from_bus;inout [N-1:0] qout; // bidirectional buswire [N-1:0] qout, data_from_bus;// the body of tristate busassign data_from_bus = receive ? qout : {N{1'bz}};assign qout = send ? data_to_bus : {N{1'bz}};endmodule

  • Chapter 15: Design Examples

    Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-11

    A Multiplexer-Based Bus

  • Chapter 15: Design Examples

    Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-12

    Syllabus

    Objectives Bus

    A p system architecture Bus structures Bus arbitration

    Data transfer General-purpose input and output Timers Universal asynchronous receiver and transmitter A simple CPU design

  • Chapter 15: Design Examples

    Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-13

    Daisy-Chain Arbitration

    Types of bus arbitration schemes daisy-chain arbitration radial arbitration

  • Chapter 15: Design Examples

    Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-14

    Syllabus

    Objectives Bus Data transfer

    Synchronous transfer mode Asynchronous transfer mode

    General-purpose input and output Timers Universal asynchronous receiver and transmitter A simple CPU design

  • Chapter 15: Design Examples

    Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-15

    Data Transfer Modes

    Data transfer modes synchronous mode asynchronous mode

    The actual data can be transferred in parallel: a bundle of signals in parallel serial: a stream of bits

  • Chapter 15: Design Examples

    Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-16

    Synchronously Parallel Data Transfers

    Each data transfer is synchronous with clock signal Bus master Bus slave

    Two types Single-clock bus cycle Multiple-clock bus cycle

  • Chapter 15: Design Examples

    Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-17

    Synchronously Parallel Data Transfers

  • Chapter 15: Design Examples

    Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-18

    Synchronously Serial Data Transfers

    Explicitly clocking scheme Implicitly clocking scheme

  • Chapter 15: Design Examples

    Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-19

    Synchronously Serial Data Transfers

    Examples

  • Chapter 15: Design Examples

    Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-20

    Syllabus

    Objectives Bus Data transfer

    Synchronous transfer mode Asynchronous transfer mode

    General-purpose input and output Timers Universal asynchronous receiver and transmitter A simple CPU design

  • Chapter 15: Design Examples

    Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-21

    Asynchronous Data Transfers

    Each data transfer occurs at random Control approaches

    strobe scheme handshaking scheme

  • Chapter 15: Design Examples

    Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-22

    Strobe

  • Chapter 15: Design Examples

    Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-23

    Handshaking

    Four events are proceeded in a cycle order ready (request) data valid data acceptance acknowledge

  • Chapter 15: Design Examples

    Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-24

    Handshaking

    Two types source-initiated transfer destination-initiated transfer

  • Chapter 15: Design Examples

    Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-25

    Asynchronously Serial Data Transfers Transmitter Receiver

  • Chapter 15: Design Examples

    Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-26

    Asynchronously Serial Data Transfers

  • Chapter 15: Design Examples

    Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-27

    Syllabus

    Objectives Bus Data transfer General-purpose input and output Timers Universal asynchronous receiver and transmitter A simple CPU design

  • Chapter 15: Design Examples

    Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-28

    General-Purpose Input and Output Devices

    The general-purpose input and output (GPIO) input output bidirectional

  • Chapter 15: Design Examples

    Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-29

    General-Purpose Input and Output Devices

    An example of 8-bit GPIO

  • Chapter 15: Design Examples

    Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-30

    Design Issues of GPIO Devices

    Readback capability of PORT register Group or individual bit control Selection the value of DDR Handshaking control Readback capability of DDR Input latch Input/Output pull-up Drive capability

  • Chapter 15: Design Examples

    Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-31

    General-Purpose Input and Output Devices

    The ith-bit of two GPIO examples

  • Chapter 15: Design Examples

    Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-32

    Syllabus

    Objectives Bus Data transfer General-purpose input and output Timers

    Interface Basic operation modes Advanced operation modes

    Universal asynchronous receiver and transmitter A simple CPU design

  • Chapter 15: Design Examples

    Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-33

    Timers

    Important applications time-delay creation event counting time measurement period measurement pulse-width measurement time-of-day tracking waveform generation periodic interrupt generation

  • Chapter 15: Design Examples

    Digital System Designs and Practices Using V