Seminar 1 - Yonsei Universitytera.yonsei.ac.kr/class/2013_1_2/lecture/sp1_pjh.pdf · Seminar 1 JungHyun Park 2013. 4. 1. ... Low noise enhancement at high frequency ... values for

Seminar 1

JungHyun Park2013. 4. 1.

[email protected]

VLSI SYSTEM LAB, YONSEI UniversitySchool of Electrical & Electronic Engineering

2 YONSEI Univ. School of EEECONFIDENTIAL

Paper Info.

JSSC 2009.Fujitsu Laboratory.13 pages, 24 figures, and 1 table.


Outline

Background Backplane for High-End Servers Multi-tap Decision-Feedback Equalizer (DFE) Linear Equalizer (LE) + 1-tap DFE

Receiver circuit designAdaptive control

Prior schemes Proposed scheme: Sign-based Zero-Forcing (S-ZF)

Measurement resultsSummary


Backplane for High-End Servers

Channel Up to 1m PCB trace

Backplane + 2 line cards 2 connectors

Target speed 10.3Gb/s x 4CH for 40Gb Ethernet

Basic issues Inter-Symbol Interference (ISI) caused by frequency-dependent

dielectric loss Reflection and crosstalk noise at 2 connectors


Decision-Feedback Equalizer (DFE)

DFE cancels ISI without amplifying noise The ISI is emulated by a feedback filter (FBF) The emulated ISI is subtracted from the input signal However, DFE speed is limited, because analog feedback must be

completed before the next decision


Multi-Tap DFE

Avoided only by fully speculative DFE

Limited speed The first post-cursor tap is

most timing critical A partially speculative DFE

applies speculation to the most critical first tap

However, a partially speculative DFE is still speed limited, because pipelining is limited as long as analog feedback remains


Multi-Tap DFE

Instead of dynamically emulating ISI, all potential ISI levels are statically computed and dynamically subtracted in parallel to generate multiple speculative decisions

Increased power and area When using fully speculative DFE


The proposed approach

LE + 1-Tap DFE Linear Equalizer (LE) to cancel long-tail ISI except the first post-cursor ISI The first post-cursor ISI is cancelled by a 1-tap speculative DFE Advantages

Fastest achievable speed Low power and small area High capability of loss compensation Low noise enhancement at high frequency

Challenge Adaptive control (particularly for LE)


Receiver architecture


Linear Equalizer

Two-stage differential buffer with capacitive and resistive source degeneration Resistive degeneration in first stage is digitally controlled by

parameter LEGain, which affects the zero frequency, the amount of peaking, and DC gain

The pole frequency is kept constant around a quarter of the baud rate


Data detector with 1-tap speculative DFE

It compares the two differential inputs, D/DX and R/RX

Using CLK

Using CLKX

Based on positive referenceBased on negative reference


Speculative Error Detector

If there is no data transition, level error LVE0 (LVE1) from the top (or third) decision circuit, which uses an error reference voltage generated by a DAC, is selected.

If there is a data transition, phase error PHE0 (PHE1) from the second (or fourth) decision circuit, which use differential zero volt as the reference, is selected.


Equalizer Control

Operation FPDOS decodes two successive data values and the error to indicate

whether residual offset is positive or negative FPDLVE also decodes two successive data values and the error to

indicates whether the error reference voltage is higher or lower than the LE output amplitude

To speculative error detector

To data detector

To linear equalizer

To linear equalizer


Issues of prior adaptive schemes for LE

No adaptive control Low compensation, or manual adjustment

Heuristic algorithm Needs an eye measurement circuit, microcontroller, and control

software

Sign-sign-least-mean-square (SS_LMS) Not applicable to some types of LE Increases power and area for parallel signal paths and extra error

samplers for each signal path Difficult to distinguish advantages of LE and DFE

Zero-forcing (ZF) for analog filters Needs an ADC and logic to perform matrix multiplication


ResISId.5 indicates whether residual ISI is positive or negative at d.5 UI

Sign-based zero-forcing

*Randomly selects on ResISId.5

*Preserves the correct result of statistical subtraction


Residual ISI detection in FPD

Residual ISI h1.5 can be calculated as the difference between error E4.5 values for FP0 and FP1 which differ only at D3.


Key points in FPD and FPB FPD checks FP0/FP1 for same number of times to perform statistical

subtraction correctly Implemented by watching for FP0 and FP1 in turn

FPB checks 4 FPDs for same number of times to define adaptation characteristics only by weight constant Implemented by watching 4 FPDs randomly

FPD/B keep watching for the FP until it is received No timeout to guarantee above statistics It also implements the pattern tolerant feature

Will not drift for any data sequence Works for non-scrambled interface

Advantages of sign-based zero-forcing Applicable to any LE circuit Easy to distinguish advantages of LE and DEF

Don by adjusting weight constants Implemented in simple logic

No matrix multiplication, ADC, microcontroller, and control software


Measurement result

Measurement conditions 10.3Gb/s transmission over FR4 backplane Trance between 2 connectors

2 to 30 inches Total insertion loss at 5GHz

15.7 to 35.8 dB, including 2 FR4 line cards, 5.74dB Test setup, 4.58dB

Tx setting is fixed Rx setting is adapted BER is estimated from BER measured with skewed offset Test pattern is PRBS31


Measurement result

Evaluation results for 10.3 Gb/s transmission over an FR4 backplane. Adapted Rx settings and BER for PRBS31


Measurement result Eye diagrams of PRBS7 with 3-tap Tx pre-emphasis

@ SMA3 after 30cm backplane @ SMA3 after 60cm backplane @ SMA3 after 75cm backplane

LE output with adapted LEGainfor 30cm




Performance Summary

Documents

Seminar 1 - Yonsei Universitytera.yonsei.ac.kr/class/2013_1_2/lecture/sp1_pjh.pdf · Seminar 1 JungHyun Park 2013. 4. 1. ... Low noise enhancement at high frequency ... values for