Secrets of the DCM: Part 2 Steven Knapp General Products Division ([email protected]) (v1.2, 11-OCT-2004) © 2004 by Xilinx, Inc. All rights reserved

Secrets of the DCM: Part 2Steven KnappGeneral Products Division([email protected])

(v1.2, 11-OCT-2004)

© 2004 by Xilinx, Inc. All rights reserved.

NOTICE:This is an early draft of this presentation.Please visit the Xilinx Sales Partner Web(SPW) for the latest version.http://www.partner.xilinx.com/common/spartan3/faeconf.htm

http://www.partner.xilinx.com/common/spartan3/faeconf.htm

Secrets of the DCM (Part I) 2

Continuing On …

• This is a continuation of Secrets of the DCM: Part 1 that covered the following topics …– Overview of the DCM and its applications– Basic Delay Locked-Loop (DLL) operation– Clock Wizard– Clock Jitter


Workshop Objectives

By the end of this class, you will …

• Understand how the DCM can phase shift clocks• Understand how to generate other clock frequencies• Learn how to build high-speed data interfaces• Overcome various DCM limitations• Legitimately say “DCMs Don’t Confuse Me”

Lesson Four

Phase Shifting


DCM

DCM Block Diagram

DigitalFrequencySynthesizer

Phase Shifter (PS)

Inpu

t Sta

ge

Out

put S

tage

Dela

y Ta

ps

Status Logic

Delay-Locked Loop (DLL)

PSINCDECPSEN

PSCLK

CLKIN

CLKFB

RST

PSDONE

STATUS[7:0]LOCKED

CLK0CLK90CLK180CLK270CLK2XCLK2X180CLKDV

CLKFXCLKFX180


Phase Shifting

• The DCM provides various phase shifting options• Dedicated phase shift outputs

– These signals always maintain their relationship – Quadrant: CLK0, CLK90, CLK180, CLK270– Half-Period: CLK2X/CLK2X180, CLKFX/CLKFX180

• Fixed or Variable phase shifting– Adjust the phase relationship of all DCM clock outputs– Requires the DCM’s DLL function


Quadrant Phase Shifts

• CLK90 and CLK270 only available in low-frequency mode

0°

1T

CLK0

°90

¼T

CLK90

T

180°

½

CLK180

270°

¾T

CLK270

360°

0Phase Shift (degrees)

Delay (fraction ofclock period)

Clock Period (T)


Half-Period Phase Shift

• CLK2X/CLK2X180 and CLKFX/CLKFX180 are similar

180°0°

½T 1T

CLK0

CLK180

360°

0Phase Shift (degrees)

Delay (fraction ofclock period)

Clock Period (T)

• Highly useful for high-performance Dual-Data Rate (DDR) applications

• Guarantees precise half-period timing


DDR ExampleClock Inversion at I/O Block

Introduces Duty-cycle Distortion

< 150 MHz ≥ 150 MHz

“Local inversion”

CLKx at Flip-Flop(with duty-cycle distortion)

180°Phase Shift

CLKx180 at Flip-Flop(with duty-cycle distortion)

CLKx(50% duty cycle)

D0

D1

CE

C0

C1

Q

OFDDRCPE

CLKx

DCM

CLKIN

CLKx180

BUFG

BUFG

Precise Timing with Half-Period Phase Shifting

“Complementary”

D0

D1

CE

C0

C1

Q

OFDDRCPE

CLKx at Flip-Flop(with duty-cycle distortion)

Duty-cycle distortion

Factor in distortionwhen using a single,inverted clock.

CLKx(50% duty cycle)

BUFGCLKx

DCM

CLKIN


Review: The DLL

• DLL shifts the feedback until the Clock and the Feedback are in phase (0° phase shift)

• DLL controls the phase relationship, can be other than 0°

PhaseDetector

Delay Line

Clock

Feedback

Clock

Feedback

Positive Phase ShiftNegative Phase Shift


Fixed Phase Shifting

• Fixed phase shift value set during configuration, unchangeable• Affects all DCM clock outputs

Clock Outputs

0

Fixed Phase Shift+ Limit

Fixed Phase Shift– Limit

The PHASE_SHIFT attribute determinesthe initial phase shift position. DCMinitially asserts LOCKED with this phaseshift value. DCM returns to this valueupon RESET.

CLKIN

Phase Shift

Type:

Value: 23

Enter the Fixedphase shift value

2.695 ns 32.344 Degrees

Resulting fixed phaseshift in nanoseconds anddegrees of phase shift

NONEFIXED

ChooseFIXEDClock Wizard


Checking If You’re Awake

• A DCM has a FIXED phase shift of 10°• What is the phase relationship between CLK0 and

CLK90?

• What is the phase relationship between CLKIN and CLK0?

• What is the phase relationship between CLKIN and CLK90?

Always 90°

100° = 90°+ 10°

10° = 0°+ 10°


Delay Line and Frequency

• Delay line has 255 taps, each 30 ps to 60 ps• Maximum guaranteed delay line is 10 ns, ~40 ps per tap• Clock inputs above 100 MHz can be shifted a full period (360°)

– Shift resolution defined by individual tap delay

PhaseDetector

Delay Line

Clock

Feedback

Clock LIMIT


Shift Limits < 100 MHz

• Clock inputs < 100 MHz have clock period longer than the guaranteed tap length (> 10 ns)

• Can only shift the clock a fraction of the clock period (<360°)

PhaseDetector

Delay Line

Clock

Feedback

ClockBEYONDLIMIT


Phase-Shift Limits

• TCLKIN > FINE_SHIFT_RANGE (Frequency < 100 MHz)

CLKINLIMITS T

_RANGEFINE_SHIFT256INTEGERTPHASE_SHIF

255TPHASE_SHIF LIMITS

• TCLKIN = Period of CLKIN input clock

• TCLKIN ≤ FINE_SHIFT_RANGE (Frequency > 100 MHz)

• FINE_SHIFT_RANGE = Guaranteed length of delay line = 10 ns (per data sheet)


Variable Phase Shifting

Clock Outputs

The PHASE_SHIFT attribute determinesthe initial phase shift position. DCMinitially asserts LOCKED with this phaseshift value. DCM returns to this valueupon RESET.

CLKIN

0Fixed Phase Shift+ Limit

Increment PhaseShift Value

Decrement PhaseShift Value

0

Dynamic Phase Shift- Limit

Dynamic Phase Shift+ Limit

After the DCM asserts LOCKED, the FPGAapplication can increment or decrement thepresent phase shift value using the DynamicPhase Shift Control logic.

PSEN

PSINCDEC

PSCLK

PSDONE

STATUS[0]

Enable

Increment/Decrement

Phase Shift Clock

Phase Shift DoneVariable PhaseShift Overflow

DCM Variable PhaseShift Control

Fixed Phase Shift+ Limit


Variable Phase Shift Timing

LOCKED remains asserted duringa variable phase shift operation

PSINCDEC

PSEN

PSCLK

PSDONE0 = Decrement phase shift1 = Increment phase shift

Start new phase shiftoperation. Shift byone phase increment.

Operation complete.Okay to start newoperation.

STATUS[0](Variable PhaseShift Overflow)

The timing to complete a phaseshift operation varies. PSDONEindicates operation is complete.

If phase shift incremented ordecremented to limit value,STATUS[0] stays High until newoperation shifts away from limit.


Phase Shift Mathematics

)PS(360PS

60ps to 30~F

1000

360

PSPS(ns)

CLKIN

Convert Negative Phase Shift to Positive Phase Shift

Convert Phase Shift in Degrees to Phase Shift in Nanoseconds

Alternate Phase Shift Solutions

60CLK180120CLK0120

Lesson Five

Clock Synthesis


Frequency SynthesisFPGA

DCM

F

n-bitswide

Fn

F

High-speed serial datadown-converted toslower parallel data

Clock Division

DCM

F FŸm

m-bitswide

F

Slower parallel dataup-converted to high-speed serial data

Clock Multiplication

F

Overclocked,time-shared logic

DCM

F FŸx

Clock Synthesis

Low cost design technique: Utilize full performance of the FPGA


Output clocks are phase alignedwhen using clock feedback viathe CLKFB input.

Frequency Synthesis

CLKIN CLK0

CLKFBDCM

CLK2X

CLK2X180

F=2ŸFCLKIN

Clock Doubler

50% duty cycleOutput available only whenDLL_FREQUENCY_MODE=LOW

De-skewed ClockF=FCLKIN

50% duty cycle whenDUTY_CYCLE_CORRECTION=TRUE

CLKDV

Clock Divider

F=FCLKIN

CLKDV_DIVIDEUsually 50% duty cycle,depending on conditions

CLKFX

CLKFX180

Frequency Synthesizer

F=FCLKINŸCLKFX_MULTIPLY

CLKFX_DIVIDE50% duty cycleDoes not require CLKFB input


Clock Synthesis Options

FunctionDCM

Output(s) FrequencyFunctional

UnitFeedbackRequired?

Clock Doubler

CLK2XCLK2X180 2*FCLKIN DLL Yes

Clock Divider CLKDV FCLKIN/DIV DLL Yes

Frequency Synthesizer

CLKFXCLKFX180 FCLKIN *M/D DFS Optional


Clock Divider

• CLKDV output requires the DLL and consequently the CLKFB feedback

• For Spartan-3, the CLKDV_DIVIDE attribute can be …– 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6, 6.5, 7, 7.5, 8, 9, 10, 11,

12, 13, 14, 15, 16• Lower output jitter when CLKDV_DIVIDE is an integer• 50% duty-cycle output usually

– Except when operating in High Frequency mode and CLKDV_DIVIDE is a non-integer (i.e., 1.5)


Digital Frequency Synthesizer (DFS)

• CLKFX/180 output frequency controlled by fraction of two attributes– CLKFX_MULTIPLY = {2,3,4• • •32}– CLKFX_DIVIDE = {1,2,3,4• • •32}– Reduce to least common multiple

• CLKIN and CLKFX/180 outputs are more limited when also using the DLL– Using the DLL with the DFS

limits the frequency range• When used, DDL and DFS are

phase aligned every– CLKFX_DIVIDE cycles of CLKIN– CLKFX_MULTIPLY cycles of CLKFX

Source:Feedback

Internal External None

Value: 1X 2X

If only using the CLKFX or CLKFX180clock ouputs, optionally click None toextend the DCM frequency limits.

(from General Setup window)


Period Jitter on CLKFX

• Maximum period jitter for CLKFX output is characterized– Depends on multiply and divide values– Depends on input and output frequencies– Room temperature (25°C)– Nominal voltages– 50% CLBs and 40 simultaneous outputs switching at 100 MHz

• Jitter reported by Clock Wizard• Spartan-3 jitter is effectively same as Virtex-II Pro

http://www.xilinx.com/applications/web_ds_v2/jitter_calc.htm

http://www.xilinx.com/applications/web_ds_v2/jitter_calc.htm


Spartan-3 CLKFX Jitter Equations

DECLKFX_DIVI

IPLYCLKFX_MULTFF CLKINCLKFX

CLKFX/CLKFX180 Output Frequency

32

KBF0.0006Jitter(UI) CLKFX(MHz)

Peak-to-peak Period Jitter (Unit Interval)

CLKFX(MHz)F

1000Jitter(UI)Jitter(ns)

Peak-to-peak Period Jitter (ns)

B = 0.05 when FCLKIN > 8 MHz, else = 0.04K =CLKFX_MULTIPLY when CLKFX_MULTIPLY > CLKFX_DIVIDE,

else = CLKFX_DIVIDE


Jitter on CLKFX

CLK0

CLKFXCLKFX180

Check CLKFX orCLKFX180 to enablethe FrequencySynthesizer options

If using only theCLKFX or CLKFX180clock outputs, uncheckCLK0 to extend theDCM frequency limits

Source:Feedback

Internal External None

Value: 1X 2X

If only using the CLKFX or CLKFX180clock ouputs, optionally click None toextend the DCM frequency limits.


Xilinx Clocking Wizard - Clock Frequency Synthesizer

Inputs for Jitter Calculations

Use output frequency

MHz ns87

Use Multiply (M) and Divide (D) values:

4M 1D

Input Clock Frequency: 33.000 MHz

Calculate

< Back Finish Cancel

More Info

Enter the desired outputfrequency, in MHz or ns,then click Calculate. DCMWizard calculates the bestmultiply (M) and divide (D)values possible.

Optionally, enter the specificvalues for the multiply (M)and divide (D) values, thenclick Calculate

Displays the incoming clockfrequency, specified earlier

Click Finishwhen finished

DCM attribute name

CLKFX_MULTIPLY CLKFX_DIVIDE

DFS_FREQUENCY_MODE

Valid Ranges for Speed Grade -4

DFS

Low

High

Fin (MHz)

24.000 - 165.000

48.000 - 280.000

Fout (MHz)

24.000 - 210.000

210.000 - 280.000

M D OutputFrequency(MHz)

Period Jitter(unit interval)

Period Jitter(pk-to-pk ns)

Generated Output

29 11 87 1.12 0.10

After entering the desiredoutput frequency or multiplyand divide values, clickCalculate to compute theresulting jitter for theFrequency Synthesizer output

Displays the frequency limitsfor the Frequency Synthesizerin both low- and high-frequency mode

Displays the calculated outputjitter values based on thesettings

Click here for help onthis screen

CLKFX_MULTIPLY CLKFX_DIVIDE


Cascading DCMs

• DCMs can be cascaded, but there is no dedicated routing available for this– The specified output jitter from the first DCM must not exceed

the specified input jitter of the second DCM– CLKFX output practically eliminated for the first DCM stage

due to jitter• Keep second DCM reset until first DCM locks

– WARNING: CLKDV does not toggle until LOCKED1– Requires three flip-flops to synchronize reset

http://support.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=19005

• Function also available in the DCM Wizard

http://support.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=19005


Clock Wizard Cascade DCMs

Lesson Six

System vs. Source Synchronous Design


System Synchronous

• Assumes a single, system-wide clock• DLL path includes delay to compensate for clock path

– Ensures no hold time requirement at the receiver• System synchronous is the default assumption

ClockSource

DATA_INDATA_OUT


Source Synchronous

• Clock generated by same source as data• Typically, clock and data have same phase• No compensation for clock path delay• Receiver hold time is not an issue

– Clock MUST be phase shifted in the receiver

ClockSource

DATA_INDATA_OUT

DATA_CLK


System vs. Source Synchronous Timing

DATA_IN

SOURCE_SYNCHRONOUS

SYSTEM_SYNCHRONOUS

SOURCE_SYNCHRONOUS+ Fixed or Dynamic Phase Shift

Data capture windowor data “eye”

A little extra delay guarantees no hold time requirement

Application phase shifts clock to middle of data eye


Deskew Adjustment inClock Wizard

Advanced ... More Info

< Back Next > Cancel

1X 2X

Feedback ValueClick for Advancedoptions


Xilinx Clocking Wizard Advanced

SOURCE_SYNCHRONOUS

OK Cancel

DCM Deskew Adjust:

Controls how much skew ispurposely added to the DCMclock path

DCM attribute name

DESKEW_ADJUST

Wait for DCM lock before DONE signal goes High

Divide Input Clock by 2

Insert reset logic for external feedback

More Info

Lesson Seven

Optional Divide by 2


Dividing Input Clock by 2

• Optional divide-by-2 function on CLKIN input– Dedicated high-speed toggle flip-flop inside the DCM

• Divide down a high-frequency clock to the range acceptable to the DCM

• Clean up a non-50% duty-cycle input to guarantee a clean 50% clock input– 50% to 60% duty-cycle improves DLL performance– Low/high duty cycles will stop the DCM working

• See data sheet for specs


Divide-by-2 inClock Wizard

Advanced ... More Info

< Back Next > Cancel

1X 2X

Feedback ValueClick for Advancedoptions


Xilinx Clocking Wizard Advanced

SYSTEM_SYNCHRONOUS

OK Cancel

DCM Deskew Adjust:Optionally divides CLKINfrequency by 2

DCM attribute name

CLKIN_DIVIDE_BY_2

Wait for DCM lock before DONE signal goes High

Divide Input Clock by 2

Insert reset logic for external feedback

More Info

Lesson Eight

622 Mbps Interface: Pulling it all together


Spartan-3 DCM Errata

• CLK2X feedback– Fixed on XC3S50 and XC3S1000– Coming on remainder of Spartan-3 family in 2005

• Negative phase shift (No longer an issue)• Maximum DLL frequency in High Frequency

mode


Problem Statement• We want to build a LVDS transmitter operating at

622 Mbps with a 311 MHz input clock• Issues:

– Probably NONE• DCM not required as long as the input clock has roughly

50% duty cycle• Transmitter macros with embedded FIFO are available for

the Spartan-3 in 4:1, 6:1, 7:1 and 8:1 SERDES factors• Transmitter macros are also available without the FIFO for

designs that use the DCM


622Mbit/second DDR Transmitter Example

Clock output shown – data outputs are similar

BUFG

BUFG

D0

D1

CE

C0

C1

Q

FDDRCPE OBUFDS

311 MHz

FPGA

IBUFGDS_DIFF_OUT

311 MHz

100W

No resistorsrequired fordifferentialtransmitters.


Problem Statement

• We want to build a LVDS receiver operating at 622 Mbps with a 311 MHz input clock

• Issues:– We have and need a 311 MHz clock– We need phase shifting, which requires the DLL – It is a DDR application

• Worry about jitter and duty-cycle distortion

MISSIO

N

IMPOSSIB

LE?


Typical 622 Mbps DDRDCM Configuration

CLK0

CLK180

CLKFB

CLKIN

Phase shift control

311 MHz

Exceeds DLL maximum frequency

Exceeds DLL maximum frequency

311 MHz

Exceeds DLL maximum phase shift frequency of 165 MHz

Exceeds DLL maximum phase shift frequency of 165 MHz

DDR interface uses half-rate clock



Fundamental Problem• 311 MHz forwarded clock coming right at us!• Spartan-3 DCM supports shifting if CLKIN ≤ 165 MHz• What to do?

– Use the dedicated divide by 2 option at the input of the DCM• Clock applied to the DLL in the DCM will be 155.5 MHz• Guarantees 50% duty-cycle DCM Friendly!

– Phase shifting is performed with DCM in low-frequency mode

– Use the 2X and 2X180 DCM outputs to reproduce to the required 311 MHz once phase shift has been applied


Example 622 Mbps DDRDCM Configuration

CLK2X

CLK2X180

CLKFB

CLKIN

Phase shift control

CLKIN_DIVIDE_BY_2=TRUE

311 MHz

Clock double reproduces original input frequency

311 MHz

Reduces 311 MHz incoming clock to <165 MHz, placing DCM in low-frequency mode

Because input clock is 311 MHz and further reduced with optional divide-by-2, DCM support phase shifting



CLK2X output supports up to 330 MHz!

NOTE: Double jitter as well

CLK2X output supports up to 330 MHz!

NOTE: Double jitter as well

• Some devices require additional BUFG due to CLK2X feedback errata


CLK0

DCM

CLK2X

CLKIN

CLKFBBUFG

BUFG

CLK2X180

CLKIN_DIVIDE_BY_2= TRUE

CLK_FEEDBACK= 1XDLL_FREQUENCY_MODE= LOW

155.5 MHz

311 MHz

BUFG

The CLKIN_DIVIDE_BY_2option reduces the effectiveDCM frequency to 155.5 MHz,which is within the DCM’sfrequency limits.

IBUFDS

Phase shifter operatesat up to 165 MHz.

D

CE

C

FDCPE

Q

D

CE

C

FDCPE_1

Q

CLK2X, CLK2X180 outputslimited to 330 MHz, maximum.

CLK0 feedback required for specificpart numbers. Optionally, usegeneral-purpose interconnect butphase alignment not guaranteed.

622 Mbps

100W

LVDS/RSDSreceiverterminationresistor.

FPGA

IBUFGDS

311 MHz

100W

DETAILED VIEW


Problem Re-Statement

• We want to build a LVDS receiver operating at 622 Mbps with a 311 MHz input clock

• Issues solved :– Phase shifting is indirectly available at 311 MHz– Receiver macros are available for Spartan-3 at 1:4,

1:6, 1:7 and 1:8 SERDES factors– Setup and hold ‘eye’ parameters do still require

characterization


XAPP462: The DCM Reference

• A comprehensive 68-page “tree killer”

• Updated for ISE 6.3i and latest Spartan-3 DCM knowledge

www.xilinx.com/bvdocs/appnotes/xapp462.pdf

http://www.xilinx.com/bvdocs/appnotes/xapp462.pdf


Questions?

[email protected]


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Steve KnappSecrets of the DCM: Part 2

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• Lesson 4: Phase Shifting

• Lesson 5: Frequency Synthesis

• Lesson 6: System vs. Source Synchronous

• Lesson 7: Optional CLKIN divide-by-2

• Lesson 8: Spartan-3 622Mbps Design Example

• Session Evaluation Forms

Documents

Secrets of the DCM: Part 2 Steven Knapp General Products Division ([email protected]) (v1.2, 11-OCT-2004) © 2004 by Xilinx, Inc. All rights reserved