Secrets of the DCM: Part 1 Steve Knapp General Products Division ([email protected]) (v1.2, 11-OCT-2004) © 2004 by Xilinx, Inc. All rights reserved

Secrets of the DCM: Part 1Steve KnappGeneral Products Division([email protected])

(v1.2, 11-OCT-2004)

© 2004 by Xilinx, Inc. All rights reserved.

スティーブ・ナップ NOTICE:This is an early draft of this presentation.Please visit the Xilinx Sales Partner Web(SPW) for the latest version.http://www.partner.xilinx.com/common/spartan3/faeconf.htm

http://www.partner.xilinx.com/common/spartan3/faeconf.htm

Secrets of the DCM (Part I) 2

Workshop Objectives

• Understand the function and application of Digital Clock Managers (DCMs)

• Unlock a few mysteries on how DCMs operate – More mysteries revealed in Part II

• Become a Clock Wizard and easily configure a DCM • Have a few new approaches to teach customers on

DCMs• Legitimately say “DCMs Don’t Confuse Me”

By the end of this class, you will …


Real-World Experience

Up the Learning Curve

What’s a DCM?

Time

Exp

erti

se

Part I

Part II


DCMs Everywhere!

• In this presentation, the Spartan-3 DCM demonstrates basic principals and concepts

• The Spartan-3 DCM is similar to Virtex-II and Virtex-II Pro

• The DLL in the DCM is similar to the DLL in Virtex/E and Spartan-II/E

• Virtex-4 DCM also employees similar concepts


DCMs: The ClockProblem Solver

Eliminate clock skew—improved performance!Multiply or divide an incoming clock or create a

completely new clock frequencyPhase shift a clockCondition a clock input to create 50% duty cycleAny or all of the above, simultaneously!

Don’t need it? Then don’t use it!


DCM, Where Are You?

Block RAMColumn

DCM_X1Y1

DCM_X1Y0DCM_X0Y0

DCM_X0Y1Global buffer multiplexers

EmbeddedMultiplierColumn

Global buffer multiplexers

XC3S50 only

• Located at top and bottom of block RAM/multiplier column(s)

• Four DCMs in each Spartan-3, except XC3S50, which has two DCM

• DCMs have direct connections to global buffers along the same edge

• Each DCM has a unique location string– Watch PAR placement!


DCM

DCM Block Diagram

DigitalFrequencySynthesizer

Phase Shifter (PS)

Inpu

t Sta

ge

Out

put S

tage

Dela

y Ta

ps

Status Logic

Delay-Locked Loop (DLL)

PSINCDECPSEN

PSCLK

CLKIN

CLKFB

RST

PSDONE

STATUS[7:0]LOCKED

CLK0CLK90CLK180CLK270CLK2XCLK2X180CLKDV

CLKFXCLKFX180

Up to all nine clock outputs available simultaneously

Any four of nine clock outputs optionally connect to global buffers along same edge

Lesson One

Avoid beingskewed!


The Ideal World

OtherDevice on

Board

FPGA

A

B

C

A

B

C

SKEW


In the Real World, You’re Skewed

OtherDevice on

BoardA

FPGA

A

B

B

C

C

DcDb

Dc

Db

Two different timing relationships!


No Skew, No Problem

Symbol -4TIOCKP 1.72 ns

Q

CLK

CLK

Q

Flip-flop Delay


Skew: The Time Thief

CLK

Q

Input BufferClock Distribution

Flip-flop

Symbol -4

TIOCKP 1.72 ns

TICKOF 4.56 ns

Q

CLK


Quick Review: What We Want

OtherDevice on

Board

FPGA

A

B

C

A

B

C


How Do We Get There?

OtherDevice on

BoardA

B

C

A

B

C

cb

What if we provide advance clocks?


A

B

C

D b

D c

The Answer?Clairvoyant Logic, Of Course!

OtherDevice on

BoardA

B

CDb

Dc

-Db + Db = NO SKEW!


Houston, We Have a Problem

• First Rule of Time Travel: You can’t go backwards!• Clairvoyant logic does not exist (well, at least not yet)• Now what!?!


Forward Thinking

OtherDevice on

BoardA

B

C

A

B

C

bD

Dc

Delay=T- Dc

Delay=T - Db

Clock Period (T)


The Tough Questions

• How do you specify the clock period?• How do you determine the delays for Db and Dc?

• How do you voltage- and temperature-compensate the design?

You Don’t!

?


Classroom Experiments• Everyone please take out your Delay-Lock Loop (DLL)

simulators

LAB 1: Feedback, frequency and phase locking

LAB 2: Stable, monotonic clock


The Magical Delay-Locked Loop (DLL)

Delay Line

Clock

Feedback

Clock

Feedback

Too Early

Each of the 256 taps is between 30

to 60 ps

PhaseDetector

ADJUST

Delay matched Clock and Feedback path lengths


The Magical Delay-Locked Loop (DLL)

PhaseDetector

Delay Line

Clock

Feedback

Clock

Feedback

Perfect!

Delay tap settings updated periodically for temperature/voltage compensationUpdate rate controlled by an internal attribute called FACTORY_JF

LOCKED


Resulting Timing

Symbol Description -4TIOCKP Output flip-flop clock-to-output 1.72 nsTICKOF Pin-to-pin clock-to-output delay, no DCM 4.56 ns

TICKOFDCM Pin-to-pin clock-to-output delay, with DCM deskew

1.52 ns

• ~ 3 ns eliminated from clock distribution delay when using internal feedback!

• Output delay nearly completely eliminated when using external feedback


Locking• The DLL requires a stable monotonic clock input

– Stable clock frequency– Minimal jitter

• The DCM LOCKED output indicates when the DCM has acquired and locked to the incoming clock– Application should ignore the DCM clock outputs until LOCKED

asserted• No clock edges can be missing during the locking process• If clock is not yet stable, hold the DCM in reset

– External enabled oscillators– External frequency scaling– Cascaded DCMs


Locking ProcessFPGA Configuration

Startup Phase

LOCKED outputis LOW

Phasealigned?

Output clocksgood?

LOCKED outputis HIGH

Lost lock.LOCKED output

is LOW

Is CLKIN stable? Withinspecified limits?

RST InputAsserted

Y

N

Y

N

FPGA applicationasserts RST input

If CLKIN not yet stable,assert RST input untilCLKIN stabilizes.

If lock is lost, assert RSTinput to force DCM toreacquire lock.


LOCKED and STATUS Bits

• LOCKED (Output clocks good)– The DCM clock outputs are not valid until LOCKED=1– If LOCKED 0, reset the DCM (hit delay tap limits)– It is possible for LOCKED=1 but the output clocks are invalid– STATUS bits provide additional detail

• STATUS[1] – CLKIN Stopped– STATUS[1]=1 if CLKIN stops toggling, reset the DCM

• STATUS[2] – CLKFX, CLKFX180 Stopped– STATUS[2]=1 if CLKFX or CLKFX180 outputs stop, and these

outputs are used in the design, reset the DCM


Feedback from a Reliable Source

• DLL requires feedback from one of two DCM outputs– CLK0 (1X feedback)– CLK2X (2X feedback)

• CLK2X not presently available on all devices– Presently supported only on XC3S50 and XC3S1000– Coming to the remainder of the family in 2005– Not supported in Virtex-II Pro


DCMs Integrate into FPGA Clock Path

IBUFG BUFG

PAD

IBUFG BUFG

PAD

CLKIN

CLKFB

CLKx

DCM


Internal Feedback

I OBUFG

Clock tointernalFPGA logic

(or BUFGMUX,or BUFGCE)

(Internal Feedback)

(alternate clock inputspossible, but not fully

skew adjusted)

I OIBUFG

CLKIN CLK0

CLKFB LOCKEDDCM

(or CLK2X)


External Feedback

CLKIN CLK0

CLKFB LOCKEDDCM

(or CLK2X)I OOBUF

I OOBUF

FPGA OtherDevice(s)on Board

CLK

ENABLE

(External Feedback Trace)

Circuit-board tracedelay, additional

clock buffers, etc.

RESETD

WCLK

A[3:0]

Q

INIT=000F

SRL16

I OIBUFG

I OIBUFG

Delay matched Clock and Feedback path lengths


Clock Wizard Makes it Easy!

Lesson Two

Wizard School


DCM Rules and Lots of Them

The DFS accepts input clock

frequencies down to 1 MHz if you

are not using the Delay-Locked

Loop (DLL)

The DLL outputs operate up to

280 MHz unless you use phase

shifting, then the maximum

frequency is 165 MHz

The CLK9

0 and

CLK270 o

utputs a

re

only ava

ilable

when the

DLL is

in

low-freq

uency mo

de

The minimum DLL output

frequency must be 24 MHz

or greater

The DLL feedback must come from either CLK0 or CLK2X. The CLK2X feedback does not work for all devices

The variable phase shifter uses the PSEN, PSINCDEC, PSCLK, PSDONE, and STATUS bits

The output jitter on the CLKFX and

CLKFX180 output depends on the

DFS Multiply and Divide settings

Any four of the nine possible

DCM outputs can connect to

global clock buffers

The CL

KDV ou

tput

can on

ly div

ide th

e

incomi

ng clo

ck by

certai

n valu

es

The frequencies supported by the DFS may be limited by the DLL if used within the same DCM

The DLL requires that the CLKFB input be connected. The DFS does not require feedback

The amount of phase shift may be limited due to the

incoming clock frequency


DCM Rule #1

• All DCMs in a design must be instantiated

• Language Templates available in ISE

• Clock Wizard makes it easy

CLKIN CLK0CLK90CLK180CLK270CLK2XCLK2X180CLKDV

CLKFXCLKFX180

STATUS[7:0]LOCKEDPSDONE

CLKFB

RSTPSEN

PSINCDECPSCLK

DCM

DSSEN


Schematic of DCM Example

CLK0

CLK90

CLK180

CLK270

CLK2X

CLK2X180

CLKDV

CLKFX

CLKFX180

STATUS

LOCKED

PSDONE

CLKIN

CLKFB

RST

PSEN

PSINCDEC

PSCLK

DCMIBUFG BUFG

BUFG

33 MHz 33 MHz

3.3 MHz

CLK_FEEDBACK = 1XCLKDV_DIVIDE = 10CLKFX_MULTIPLY = 29CLKFX_DIVIDE = 11CLKOUT_PHASE_SHIFT = VARIABLEDFS_FREQUENCY_MODE = LOWDLL_FREQUENCY_MODE = LOWPHASE_SHIFT = 23

87 MHz


ISE 6.3i Clock Wizard

Clock Wizard

Graphically configure aDigital Clock Manager(DCM)

Vendor-specificVHDL or Verilog

VHDL or Veriloginstatiation

template

Xilinx ArchitectureWizard (XAW)

settings file

User constraintsfile (UCF)

Greatly simplifies using a DCM!


Two Methods to Invoke Clock Wizard

• From Window Start menu– Start Xilinx ISE 6 Accessories Architecture

Wizard

• From within Project Navigator– Project New Source


Project Navigator Method

New Source

User Document

SchematicVHDL LibraryVHDL PackageVHDL Test BenchTest Bench WaveformBMM FileMEM FileImplementation Constraints File

IP (CorGen & Architecture Wizard)

State Diagram

My_Spartan-3

File Name:

MyDirectory

Location:

...

Add to Project

< Back Next > Cancel Help

Enter the filename tosave the settings for thisDCM module

Click here to select thedirectory for thefilename

Click Next tocontinue

Choose IP (CoreGen &Architecture Wizard)

VHDL Module


Selecting the Right Wizard

Architecture Selection Wizard

Architecture Wizards for Spartan-3Clocking Wizard

Single DCMClock Forwarding / Board DeskewBoard Deskew with an Internal DeskewClock Switching with Two DCMsCascading in Series with Two DCMs

Select the wizard:

OK Cancel

(a) Architecture Wizard Accessory

Select Core Type

Basic ElementsClocking

Cascading in Series with Two DCMsBoard Deskew with an Internal Deskew

Clock Forwarding / Board DeskewClock Switching with Two DCMs

Communications & NetworkingDigital Signal Processing

< Back Next > Cancel Help

Single DCM

Architecture Wizard: Single DCM

(b) IP (CoreGen & Architecture Wizard)


General SetupXilinx Clocking Wizard - General Setup

Input Clock Frequency

MHz ns33

Advanced ...

CLK0CLK90

CLK180CLK270CLKDVCLK2X

CLK2X180CLKFX

CLKFX180

LOCKEDSTATUS

PSDONE

CLKINCLKFB

RSTPSENPSINCDECPSCLK

More Info

< Back Next > Cancel

Check CLKFX orCLKFX180 to enable theFrequency Synthesizeroptions

Check CLKDV to enablethe Clock Divider options

Enter input clockfrequency, withfull accuracy, inMHz or ns

Click here for helpon this screen

Click here foradvanced options

When checked, the CLK0,CLK90, CLK180, andCLK270 outputs have 50%duty cycle


DCM attribute name

10

Divide By Value

CLKDV_DIVIDE

Value:

Phase Shift PHASE_SHIFT

23

VARIABLEType:

2.695 ns 32.344 Degrees

CLKIN SourceInternalExternal

SingleDifferential

DLL_FREQUENCY_MODE

DUTY_CYCLE_CORRECTION

1X 2X

Feedback Value

CLK_FEEDBACK

Feedback SourceInternalExternal None

SingleDifferential

Use Duty Cycle Correction

CLKOUT_PHASE_SHIFT

Selecting Externalautomatically connectsCLKIN to an IBUFG globalbuffer input primitive.Select Internal to connectCLKIN to another source.

Select Fixed to phase shiftall outputs by the valuedefined below. SelectVariable mode todynamically adjust phaseshifting using the PSEN,PSINCDEC, and PSCLKinputs.

Sets the Fixed phase shiftvalue or the initial value forVariable phase shift mode,measured as x/256ths of aclock period, where x=0 to255.

Indicate whether thefeedback is from anInternal or External sourceor None

If clock feedback isrequired, is it from theCLK0 output (1X) or theCLK2X output (2X)?

If clock or feedback isExternal, choose whetherthe input is Single-ended orDifferential

Set the frequency divider forthe Clock Divider output,CLKDV


Assigning Global BuffersXilinx Clocking Wizard - Clock Buffers

Clock Buffer Settings

Use Global Buffers for all selected clock outputs

Customize buffers

More Info

< Back Next > Cancel

By default, ClockWizard placesglobal buffers(BUFG) on all theselected DCMclock outputs

Optionally,customize how theDCM clock outputsconnect to theother FPGA logicusing the gridbelow

Click here for help onthis screen


Add Buffer

Input I0 Input I1 View/Edit Buffer

Global BufferCLK0

Enabled BufferCLK90

Clock MuxCLK180

Local RoutingCLK270

LowskewlineCLKDV

For each clockoutput, select thetype of bufferconnecting thesignal to theFPGA

CLK90

BUFGI0 O

BUFGCEI0 O

CE

O

S

BUFGMUXI0

I1

I0

I0

Global Buffer

Enabled Buffer

Clock Mux

Local Routing

Lowskewline


Frequency Synthesizer

CLK0

CLKFXCLKFX180

Check CLKFX orCLKFX180 to enablethe FrequencySynthesizer options

If using only theCLKFX or CLKFX180clock outputs, uncheckCLK0 to extend theDCM frequency limits

Source:Feedback

Internal External None

Value: 1X 2X

If only using the CLKFX or CLKFX180clock ouputs, optionally click None toextend the DCM frequency limits.

(back on General Setup)

Xilinx Clocking Wizard - Clock Frequency Synthesizer

Inputs for Jitter Calculations

Use output frequency

MHz ns87

Use Multiply (M) and Divide (D) values:

4M 1D

Input Clock Frequency: 33.000 MHz

Calculate

< Back Finish Cancel

More Info

Enter the desired outputfrequency, in MHz or ns,then click Calculate. DCMWizard calculates the bestmultiply (M) and divide (D)values possible.

Optionally, enter the specificvalues for the multiply (M)and divide (D) values, thenclick Calculate

Displays the incoming clockfrequency, specified earlier

Click Finishwhen finished

DCM attribute name

CLKFX_MULTIPLY CLKFX_DIVIDE

DFS_FREQUENCY_MODE

Valid Ranges for Speed Grade -4

DFS

Low

High

Fin (MHz)

24.000 - 165.000

48.000 - 280.000

Fout (MHz)

24.000 - 210.000

210.000 - 280.000

M D OutputFrequency(MHz)

Period Jitter(unit interval)

Period Jitter(pk-to-pk ns)

Generated Output

29 11 87 0.10 1.12

After entering the desiredoutput frequency or multiplyand divide values, clickCalculate to compute theresulting jitter for theFrequency Synthesizer output

Displays the frequency limitsfor the Frequency Synthesizerin both low- and high-frequency mode

Displays the calculated outputjitter values based on thesettings

Click here for help onthis screen

CLKFX_MULTIPLY CLKFX_DIVIDE


Voila!


Instantiation Template

Module View

COMPONENT my_dcmPORT ( CLKIN_IN : IN std_logic; RST_IN : IN std_logic; LOCKED_OUT : OUT std_logic; CLK0_OUT : OUT std_logic );END COMPONENT;

Inst_my_dcm: my_dcm PORT MAP( CLKIN_IN => , RST_IN => , LOCKED_OUT => , CLK0_OUT => );

xc3s400-4fg456My_Design (my_design.vhd)my_dcm (my_dcm.xaw)

Process View

Sources in Project:

Add Existing SourceCreate New SourceCreate Schematic SymbolView HDL SourceView HDL Instantiation Template

Processes for Source: “my_dcm”

Click new ClockWizard source file

Double click to viewinstantiation template

VHDLcomponentdeclaration

VHDLcomponentinstantiation

Available for both VHDL and Verilog

VHDL Example

Lesson Three

Jitter


What is Jitter?

• Uncertainty on exact timing of a clock edge• Affected by power noise, decoupling, SSOs, internal

switching, etc.• Period (peak-to-peak) jitter specification is most quoted

– Specified as either absolute (300 ps) or deviation (± 150 ps)

Ideal Clock

Measured clock period

Nu

mb

er o

f sa

mp

les

Peak-to-peak Period Jitter


Clock Jitter Specifications• Period (peak-to-peak) jitter• Cycle-to-cycle jitter

• Unit Interval (UI)

T1=T0+100 ps T2=T1-150 psT0

Bit Period

Peak-to-peakPeriod Jitter

Unit Interval (UI) Peak-to-peak period jitter,represented as fraction ofUnit Interval

ExampleUI=0.10 means that period jitter is 10% of the total bit period


HalfPeriodJitter

Jitter Effects on Cycle Timing

Bit Period

Single Data Rate (SDR)

Available Period

EarliestArrival

Clock Period


Jitter Effects on Cycle TimingDouble Data Rate (DDR)

Clock Period

No duty-cycle distortioneffects considered

EarliestArrival

Bit Period

Consider both clock edges in DDR applicationsAvailable

PeriodJitter

AvailablePeriod


Jitter Effects on Flip-Flop Timing

Early Clock Edge Late Clock Edge

• Increases input set-up time• Reduces minimum clock-to-

output time

• Increases hold time• Increases maximum clock-to-

output time

HalfPeriodJitter

HalfPeriodJitter


Minimizing Clock Jitter• Switching noise causes jitter

– Proper power, PCB design, and decoupling• XAPP623: Power System Distribution Guidelines

http://www.xilinx.com/xapp/xapp623.pdf• PCB Checklist

http://support.xilinx.com/products/design_resources/highspeed_design/si_pcbcheck.htm

– % CLB switching contributes noise– Obey SSO recommendations (in Spartan-3 data sheet)

• VCCAUX is voltage source for DCMs• GND pins for logic and DCMs are common• Jitter on input clock

– Garbage in, garbage out• Take care of your clocks and your clocks will take care of you

http://www.xilinx.com/xapp/xapp623.pdf

http://support.xilinx.com/products/design_resources/highspeed_design/si_pcbcheck.htm


GOVERNMENT HEALTH WARNING:FAILING TO APPLY XAPP623 COULD BE

HAZARDOUS TO YOUR DCM DESIGN ANDYOUR MENTAL HEALTH


XAPP462: The DCM Reference

• A comprehensive 68-page “tree killer”

• Updated for ISE 6.3i and latest Spartan-3 DCM knowledge

www.xilinx.com/bvdocs/appnotes/xapp462.pdf

http://www.xilinx.com/bvdocs/appnotes/xapp462.pdf


Second Verse, Same as the First*

• If you enjoyed this session, please also attend …

* Only a little bit louder and a whole lot worse

Secrets of the DCM

Part II


Questions?

[email protected]


Please Fill Out and Return the Feedback Forms!

Steve KnappSecrets of the DCM: Part 1

ü

ü

ü

• Forms are in the back of your FAE conference book• Please return at back of the room

Thank You!


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• Overview

• Lesson 1: Avoid Being Skewed

• Lesson 2: Clock Wizard School

• Lesson 3: Clock Jitter

• Session Evaluation Forms

Documents

Secrets of the DCM: Part 1 Steve Knapp General Products Division ([email protected]) (v1.2, 11-OCT-2004) © 2004 by Xilinx, Inc. All rights reserved