SBOS477 DECEMBER 2011 Low Noise and Distortion, General

Burr-Brown Audio

OPA1652OPA1654

www.ti.com SBOS477 –DECEMBER 2011

™ Low Noise and Distortion, General-Purpose, FET-InputAUDIO OPERATIONAL AMPLIFIERS

Check for Samples: OPA1652, OPA1654

1FEATURES DESCRIPTIONThe OPA1652 (dual) and OPA1654 (quad) FET-input

234• Low Noise: 4.5 nV/√Hz at 1 kHzoperational amplifiers achieve a low 4.5 nV/√Hz noise• Low Distortion: 0.00005% at 1 kHz density with an ultralow distortion of 0.00005% at 1

• Low Quiescent Current: kHz. The OPA1652 and OPA1654 op amps offer2 mA Per Channel rail-to-rail output swing to within 800 mV with 2-kΩ

load, which increases headroom and maximizes• Low Input Bias Current: 10 pAdynamic range. These devices also have a high• Slew Rate: 10 V/μs output drive capability of ±30 mA.

• Wide Gain Bandwidth: 18 MHz (G = +1)These devices operate over a very wide supply range

• Unity Gain Stable of ±2.25 V to ±18 V, or +4.5 V to +36 V, on only 2 mA• Rail-to-Rail Output of supply current per channel. The OPA1652 and

OPA1654 op amps are unity-gain stable and provide• Wide Supply Range:excellent dynamic behavior over a wide range of load±2.25 V to ±18 V, or +4.5 V to +36 Vconditions.

• Dual and Quad Versions AvailableThese devices also feature completely independent• Small Package Sizes:circuitry for lowest crosstalk and freedom fromDUAL: SO-8 and MSOP-8 interactions between channels, even when overdriven

QUAD: SO-14 and TSSOP-14 or overloaded.

The OPA1652 and OPA1654 temperature ranges areAPPLICATIONSspecified from –40°C to +85°C. SoundPlus™

• Analog and Digital Mixers• Audio Effects Processors• Musical Instruments• A/V Receivers• DVD and Blu-Ray™ Players• Car Audio Systems

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2SoundPlus is a trademark of Texas Instruments Incorporated.3Blu-Ray is a trademark of Blu-Ray Disc Association.4All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Copyright © 2011, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.

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1

2

3

4

8

7

6

5

V+

OUT B

-IN B

+IN B

OUT A

-IN A

+IN A

V-

A

B

Out A

-In A

+In A

V+

+ In B

-In B

Out B

1

2

3

4

5

6

7

14

13

12

11

10

9

8

DA

B C

Out D

-In D

+In D

V-

+ In C

-In C

Out C

OPA1652OPA1654

SBOS477 –DECEMBER 2011 www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be moresusceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

PACKAGE INFORMATION (1)

PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR PACKAGE MARKING

SO-8 D OP1652OPA1652

MSOP-8 DGK OUPI

SO-14 D OP1654OPA1654

TSSOP-14 PW OP1654

(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TIweb site at www.ti.com.

ABSOLUTE MAXIMUM RATINGS (1)

Over operating free-air temperature range (unless otherwise noted).

OPA1652, OPA1654 UNIT

Supply Voltage VS = (V+) – (V–) 40 V

Input Voltage (V–) – 0.5 to (V+) + 0.5 V

Input Current (All pins except power-supply pins) ±10 mA

Output Short-Circuit (2) Continuous

Operating Temperature –55 to +125 °CStorage Temperature –65 to +150 °CJunction Temperature 200 °C

Human Body Model (HBM) 2 kV

ESD Ratings Charged Device Model (CDM) 1 kV

Machine Model (MM) 200 V

(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods maydegrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyondthose specified is not supported.

(2) Short-circuit to VS/2 (ground in symmetrical dual supply setups), one amplifier per package.

PIN CONFIGURATIONS

OPA1652: D AND DGK PACKAGESOPA1654: D AND PW PACAKGESSO-8 AND MSOP-8

SO-14 AND TSSOP-14(TOP VIEW)(TOP VIEW)

2 Copyright © 2011, Texas Instruments Incorporated

Product Folder Link(s): OPA1652 OPA1654



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OPA1652OPA1654


ELECTRICAL CHARACTERISTICS: VS = ±15 VAt TA = +25°C, RL = 2 kΩ, and VCM = VOUT = midsupply, unless otherwise noted.

OPA1652, OPA1654

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

AUDIO PERFORMANCE

0.00005 %THD+N Total harmonic distortion + noise

G = +1, f = 1 kHz, VO = 3 VRMS –126 dB

0.00005 %SMPTE/DIN Two-Tone, 4:1(60 Hz and 7 kHz) –126 dB

0.00005 %G = +1, DIM 30 (3-kHz square waveIMD Intermodulation distortion VO = 3 VRMS and 15-kHz sine wave) –126 dB

0.00005 %CCIF Twin-Tone(19 kHz and 20 kHz) –126 dB

FREQUENCY RESPONSE

GBW Gain-bandwidth product G = +1 18 MHz

SR Slew rate G = –1 10 V/μs

Full power bandwidth (1) VO = 1 VP 1.6 MHz

Overload recovery time G = –10 1 μs

Channel separation (dual and quad) f = 1 kHz –120 dB

NOISE

en Input voltage noise f = 20 Hz to 20 kHz 5.4 μVPP

Input voltage noise density f = 1 kHz 4.5 nV/√Hz

In Input current noise density f = 1 kHz 0.5 pA/√Hz

OFFSET VOLTAGE

VS = ±2.25 V to ±18 V ±0.5 ±1.5 mVVOS Input offset voltage

VS = ±2.25 V to ±18 V, TA = –40°C to +85°C (2) 2 8 μV/°C

PSRR Power-supply rejection ratio VS = ±2..25 V to ±18 V 3 8 μV/V

INPUT BIAS CURRENT

IB Input bias current VCM = 0 V ±10 ±100 pA

IOS Input offset current VCM = 0 V ±10 ±100 pA

INPUT VOLTAGE RANGE

VCM Common-mode voltage range (V–) + 0.5 (V+) – 2 V

CMRR Common-mode rejection ratio 100 110 dB

INPUT IMPEDANCE

Differential 100 || 6 MΩ || pF

Common-mode 6000 || 2 GΩ || pF

OPEN-LOOP GAIN

AOL Open-loop voltage gain (V–) + 0.8 V ≤ VO ≤ (V+) – 0.8 V, RL = 2 kΩ 106 114 dB

OUTPUT

VOUT Voltage output RL = 2 kΩ (V–) + 0.8 (V+) – 0.8 V

IOUT Output current See Typical Characteristics mA

ZO Open-loop output impedance f = 1 MHz See Typical Characteristics Ω

ISC Short-circuit current (3) ±50 mA

CLOAD Capacitive load drive 100 pF

POWER SUPPLY

VS Specified voltage ±2.25 ±18 V

IOUT = 0 A 2.0 2.5 mAQuiescent currentIQ (per channel) IOUT = 0 A, TA = –40°C to +85°C (2) 2.8 mA

(1) Full-power bandwidth = SR/(2π × VP), where SR = slew rate.(2) Specified by design and characterization.(3) One channel at a time.

Copyright © 2011, Texas Instruments Incorporated 3




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OPA1652OPA1654


ELECTRICAL CHARACTERISTICS: VS = ±15 V (continued)At TA = +25°C, RL = 2 kΩ, and VCM = VOUT = midsupply, unless otherwise noted.

OPA1652, OPA1654

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

TEMPERATURE

Specified range –40 +85 °C

Operating range –55 +125 °C

THERMAL INFORMATION: OPA1652OPA1652

THERMAL METRIC (1) D (SO) DGK (MSOP) UNITS

8 PINS 8 PINS

θJA Junction-to-ambient thermal resistance 143.6 218.9

θJCtop Junction-to-case (top) thermal resistance 76.9 78.6

θJB Junction-to-board thermal resistance 61.8 103.7°C/W

ψJT Junction-to-top characterization parameter 27.8 14.6

ψJB Junction-to-board characterization parameter 61.3 101.8

θJCbot Junction-to-case (bottom) thermal resistance N/A N/A

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

THERMAL INFORMATION: OPA1654OPA1654

THERMAL METRIC (1) D (SO) PW (TSSOP) UNITS

14 PINS 14 PINS

θJA Junction-to-ambient thermal resistance 90.1 126.9

θJCtop Junction-to-case (top) thermal resistance 54.8 46.6

θJB Junction-to-board thermal resistance 44.4 58.6°C/W

ψJT Junction-to-top characterization parameter 19.9 5.5

ψJB Junction-to-board characterization parameter 44.2 57.8

θJCbot Junction-to-case (bottom) thermal resistance N/A N/A

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.





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Time (1 s/div)

Voltage N

ois

e (

500 n

V/d

iv)

G002

1

10

100

1 10 100 1k 10k 100kFrequency (Hz)

Vol

tage

Noi

se (n

V/

Hz

)

G001

0

2

5

8

10

12

15

18

20

10k 100k 1M 10MFrequency (Hz)

Out

put V

olta

ge (

V)

VS = ± 15 V

VS = ± 2.25 V

G004

1

10

100

1k

10k

100 1k 10k 100k 1M

Resistor Noise

OPA166x

OPA165x

Source Resistance ( )W

Voltage N

ois

e (nV

/H

z)

Eo

2= e

n

2+ (inRS)

2+ 4KTRS

G003

RS

EO

10 100 1k 10k 100k 1M 10M 100M−20

0

20

40

60

80

100

120

140

0

45

90

135

180

Frequency (Hz)

Gai

n (d

B)

Pha

se (

°)

GainPhase

CL = 10 pF

G005

−20

0

20

40

100k 1M 10M 100MFrequency (Hz)

Gai

n (d

B)

Gain = −1 V/VGain = +1 V/VGain = +10 V/V

CL = 10 pF

G006

OPA1652OPA1654


TYPICAL CHARACTERISTICSAt TA = +25°C, VS = ±15 V, and RL = 2 kΩ, unless otherwise noted.

INPUT VOLTAGE NOISE DENSITYvs FREQUENCY 0.1Hz TO 10Hz NOISE

Figure 1. Figure 2.

VOLTAGE NOISE vs SOURCE RESISTANCE MAXIMUM OUTPUT VOLTAGE vs FREQUENCY

Figure 3. Figure 4.

GAIN AND PHASE vs FREQUENCY CLOSED-LOOP GAIN vs FREQUENCY

Figure 5. Figure 6.





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0.00001

0.0001

0.001

0.01

20 100 1k 10k 20kFrequency (Hz)

TH

D+

N (

%)

G = 10 V/V, RL = 600 ΩG = 10 V/V, RL = 2 kΩG = +1 V/V, RL = 600 ΩG = +1 V/V, RL = 2 kΩG = −1 V/V, RL = 600 ΩG = −1 V/V, RL = 2 kΩ

VOUT = 3 VRMS

BW = 80 kHz

G007

0.00001

0.0001

0.001

0.01

20 100 1k 10k 20k

Frequency (Hz)

TH

D+

N (

%)

RS = 0 W

RS = 30 W

RS = 60 W

RS = 1 kW

VOUT = 3 VRMS

BW = 80 kHz

G008

OPA1652

+15V

-15V RL

RSOURCE

0.00001

0.0001

0.001

0.01

20 100 1k 10k 100kFrequency (Hz)

TH

D+

N (

%)


VOUT = 3 VRMS

BW = 500 kHz

G009

0.00001

0.0001

0.001

0.01

20 100 1k 10k 100k

Frequency (Hz)

TH

D+

N (

%)

RS = 0 W

RS = 30 W

RS = 60 W

RS = 1 kW

VOUT = 3 VRMS

BW = 500 kHz

G010

OPA1652

+15V

-15V RL

RSOURCE

0.00001

0.0001

0.001

0.01

1m 10m 100m 1 10 20Output Amplitude (Vrms)

TH

D+

N (

%)


f = 1 kHzBW = 80 kHzRS = 0 Ω

G011

0.00001

0.0001

0.001

0.01

100m 1 10 20Output Amplitude (Vrms)

TH

D+

N (

%)

DIM 30: 3 kHz − Square Wave, 15 kHz Sine WaveCCIF Twin Tone: 19 kHz and 20 kHzSMPTE / DIN: Two −Tone 4:1, 60 Hz and 7 KHz

G = +1 V/V

G012

OPA1652OPA1654


TYPICAL CHARACTERISTICS (continued)At TA = +25°C, VS = ±15 V, and RL = 2 kΩ, unless otherwise noted.

THD+N RATIO vs FREQUENCY THD+N RATIO vs FREQUENCY

Figure 7. Figure 8.

THD+N RATIO vs FREQUENCY THD+N RATIO vs FREQUENCY

Figure 9. Figure 10.

INTERMODULATION DISTORTION vsTHD+N RATIO vs OUTPUT AMPLITUDE OUTPUT AMPLITUDE






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−160

−140

−120

−100

−80

100 1k 10k 100kFrequency (Hz)

Cro

ssta

lk (

dB)

VOUT = 3 VRMS

Gain = +1 V/V

G013

0

20

40

60

80

100

120

140

100 1k 10k 100k 1M 10M 100MFrequency (Hz)

CM

RR

, PS

RR

(dB

)

+PSRR−PSRRCMRR

G014

Time (0.2 s/div)m

Voltage (

25 m

V/d

iv)

VIN

VOUT

G = +1 V/VCL = 100 pF

G015 Time (0.2 s/div)m

Voltage (

25 m

V/d

iv)

VIN

VOUT

G = −1 V/VCL = 100 pF

G016

Time (1 s/div)m

Voltage (

2.5

V/d

iv)

VIN

VOUT

G = + 1V/VRF = 2 kW

CL = 100 pF

G017 Time (1 s/div)m

Voltage (

2.5

V/d

iv)

VIN

VOUT

G018

G = −1 V/VCL = 100 pF

OPA1652OPA1654



CHANNEL SEPARATION vs FREQUENCY CMRR AND PSRR vs FREQUENCY (Referred to Input)


SMALL-SIGNAL STEP RESPONSE SMALL-SIGNAL STEP RESPONSE(100mV) (100mV)


LARGE-SIGNAL STEP RESPONSE LARGE-SIGNAL STEP RESPONSE






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0

5

10

15

20

25

30

35

40

45

50

0 50 100 150 200 250 300 350 400

Capacitance (pF)

Ove

rsh

oo

t (%

)

RS = 0 W

RS = 25 W

RS = 50 W

VOUT = 100 mVPP

G = +1 V/V

G019

+15 V

-15 V

RS

CL

OPA1652

RL

0

5

10

15

20

25

30

35

40

45

50

0 50 100 150 200 250 300 350 400

Capacitance (pF)

Ove

rsh

oo

t (%

)

RS = 0 W

RS = 25 W

RS = 50 W

VOUT = 100 mVPP

G = −1 V/V

G020

OPA1652

R =I 2 kW

RS

CL

RF = 2 kW

+15 V

-15 V

−1

0

1

2

3

4

−40 −15 10 35 60 85 110 135Temperature (°C)

AO

L (µ

V)

RL = 2 kΩ

G022

0

5

10

15

20

25

0 1 2 3 4 5

Capacitance (pF)

Overs

hoot (%

)

VOUT = 100 mVPP

G = −1 V/VRS = 0 W

G021

OPA1652

R =I 2 kW

RS

CL

CF

RF = 2 kW

+15 V

-15 V

−2000

−1600

−1200

−800

−400

0

400

800

1200

−40 −15 10 35 60 85 110 135Temperature (°C)

Ib a

nd Io

s C

urre

nt (

pA)

IbnIbp

Ios

G023

−8

−6

−4

−2

0

2

4

6

8

−18 −15 −12 −9 −6 −3 0 3 6 9 12 15 18Common − Mode Voltage (V)

Ib a

nd Io

s C

urre

nt (

pA)

Ibp

IbnIos

G024

OPA1652OPA1654



SMALL-SIGNAL OVERSHOOT SMALL-SIGNAL OVERSHOOTvs CAPACITIVE LOAD vs CAPACITIVE LOAD


SMALL-SIGNAL OVERSHOOTvs FEEDBACK CAPACITOR (100mV Output Step) OPEN-LOOP GAIN vs TEMPERATURE


IB AND IOS vs TEMPERATURE IB AND IOS vs COMMON-MODE VOLTAGE






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0

0.5

1

1.5

2

2.5

3

−40 −15 10 35 60 85 110 135Temperature (°C)

Sup

ply

Cur

rent

(m

A)

G025

0

0.5

1

1.5

2

2.5

3

0 4 8 12 16 20 24 28 32 36Supply Voltage (V)

Sup

ply

Cur

rent

(m

A)

G026

−40

−30

−20

−10

0

10

20

30

40

0 5 10 15 20 25 30 35 40 45 50 55 60Output Current (mA)

Out

put V

olag

e S

win

g (V

)

−40 C−25 C0 C25 C85 C125 C

G029

−100

−80

−60

−40

−20

0

20

40

60

80

100

−40 −15 10 35 60 85 110 135Temperature (°C)

Isc

(mA

)

+Isc−Isc

G028

0

10

20

30

40

50

60

70

80

90

0 50 100 150 200 250 300 350 400Capacitance (pF)

Pha

se M

argi

n (°

)

G = +1 V/V

G031

0

10

20

30

40

50

0 50 100 150 200 250 300 350 400Capacitance (pF)

Ove

rsho

ot (

%)

VS = ± 2.25 VVS = ± 18 V

G = +1 V/VVIN = 100 mVPP

G032

OPA1652OPA1654



SUPPLY CURRENT vs TEMPERATURE SUPPLY CURRENT vs SUPPLY VOLTAGE


OUTPUT VOLTAGE vs OUTPUT CURRENT SHORT-CIRCUIT CURRENT vs TEMPERATURE


PHASE MARGIN vs CAPACITIVE LOAD PERCENT OVERSHOOT vs CAPACITIVE LOAD






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Time (0.4 s/div)m

Ou

tpu

t V

olta

ge

(5

V/d

iv)

VIN

VOUT

G = −10 V/V

G033

2 kW

20 kW

VIN

VOUTOPA1652

G = 10-

+18 V

-18 V

Time (0.4 s/div)m

Outp

ut V

oltage (

5 V

/div

)

VIN

VOUT

G = −10 V/V

G027

2 kW

20 kW

VIN

VOUTOPA1652

G = 10-

+18 V

-18 V

G = +1 V/V

−20

−15

−10

−5

0

5

10

15

20

Time (125 s/div)m

Vo

lta

ge

(V

)

VIN

VOUT

G034

+18 V

-18 V

37VPP

Sine Wave

( 18.5 V)±

OPA1652

10

100

1k

10 100 1k 10k 100k 1M 10M 100MFrequency (Hz)

Impe

danc

e (Ω

)

G030

OPA1652OPA1654



NEGATIVE OVERLOAD RECOVERY POSITIVE OVERLOAD RECOVERY


OPEN-LOOP OUTPUT IMPEDANCE vsFREQUENCY NO PHASE REVERSAL






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VBIAS1

Class AB

Control

Circuitry

VBIAS2

V +IN

V+

V-

V -IN

VO

TailCurrent

OPA1652OPA1654


APPLICATION INFORMATION

applications do not require equal positive andThe OPA1652 and OPA1654 are unity-gain stable, negative output voltage swing. With the OPA165xprecision dual and quad op amps with very low noise. series, power-supply voltages do not need to beApplications with noisy or high-impedance power equal. For example, the positive supply could be setsupplies require decoupling capacitors close to the to +25 V with the negative supply at –5 V.device pins. In most cases, 0.1-μF capacitors areadequate. Figure 35 shows a simplified schematic of In all cases, the common-mode voltage must bethe OPA165x (one channel shown). maintained within the specified range. In addition, key

parameters are assured over the specifiedtemperature range of TA = –40°C to +85°C.OPERATING VOLTAGEParameters that vary significantly with operating

The OPA165x series op amps operate from ±2.25 V voltage or temperature are shown in the Typicalto ±18 V supplies while maintaining excellent Characteristics.performance. The OPA165x series can operate withas little as +4.5V between the supplies and with up to+36 V between the supplies. However, some

Figure 35. OPA165x Simplified Schematic





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1

10

100

1k

10k

100 1k 10k 100k 1M

Resistor Noise

OPA166X

OPA165X

Source Resistance (Ω)

Vol

tage

Noi

se (n

V/

Hz

)

Eo2 = en

2 + (inRS)2 + 4KTRS

G003

OPA165x Output

RF

Input

-

+RI

OPA1652OPA1654


INPUT PROTECTION The equation in Figure 37 shows the calculation ofthe total circuit noise, with these parameters:

The input terminals of the OPA1652 and OPA1654• en = Voltage noiseare protected from excessive differential voltage with• in = Current noiseback-to-back diodes, as Figure 36 illustrates. In most

circuit applications, the input protection circuitry has • RS = Source impedanceno consequence. However, in low-gain or G = +1 • k = Boltzmann’s constant = 1.38 × 10–23 J/Kcircuits, fast ramping input signals can forward bias • T = Temperature in Kelvins (K)these diodes because the output of the amplifiercannot respond rapidly enough to the input ramp. Ifthe input signal is fast enough to create this forwardbias condition, the input signal current must be limitedto 10 mA or less. If the input signal current is notinherently limited, an input series resistor (RI) and/ora feedback resistor (RF) can be used to limit thesignal input current. This resistor degrades thelow-noise performance of the OPA165x and isexamined in the following Noise Performance section.Figure 36 shows an example configuration when bothcurrent-limiting input and feeback resistors are used.

Figure 37. Noise Performance of the OPA165x inUnity-Gain Buffer Configuration

BASIC NOISE CALCULATIONS

Design of low-noise op amp circuits requires carefulconsideration of a variety of possible noisecontributors: noise from the signal source, noisegenerated in the op amp, and noise from theFigure 36. Pulsed Operationfeedback network resistors. The total noise of thecircuit is the root-sum-square combination of all noisecomponents.NOISE PERFORMANCE

The resistive portion of the source impedanceFigure 37 shows the total circuit noise for varyingproduces thermal noise proportional to the squaresource impedances with the op amp in a unity-gainroot of the resistance. Figure 37 plots this equation.configuration (no feedback resistor network, andThe source impedance is usually fixed; consequently,therefore no additional noise contributions).select the op amp and the feedback resistors to

The OPA165x (GBW = 18 MHz, G = +1) is shown minimize the respective contributions to the totalwith total circuit noise calculated. The op amp itself noise.contributes both a voltage noise component and a

Figure 38 illustrates both inverting and noninvertingcurrent noise component. The voltage noise isop amp circuit configurations with gain. In circuitcommonly modeled as a time-varying component ofconfigurations with gain, the feedback networkthe offset voltage. The current noise is modeled asresistors also contribute noise. The current noise ofthe time-varying component of the input bias currentthe op amp reacts with the feedback resistors toand reacts with the source resistance to create acreate additional noise components. The feedbackvoltage component of noise. Therefore, the lowestresistor values can generally be chosen to makenoise op amp for a given application depends on thethese noise sources negligible. The equations forsource impedance. For low source impedance,total noise are shown for both configurations.current noise is negligible, and voltage noise

generally dominates. The voltage noise of theOPA165x series op amps makes them a betterchoice for source impedances greater than or equalto 1 kΩ.





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R1

R2

EO

R1

R2

EOR

S

VS

RS

VS

A) Noise in Noninverting Gain Configuration

B) Noise in Inverting Gain Configuration

Noise at the output:

Where e =S

4kTRS

4kTR1

4kTR2

= thermal noise of RS

= thermal noise of R1


e =1

e =2

Noise at the output:

E =O

21 +

R2

R + R1 S

R2

R + R1 S

2 22

Where e =S

4kTRS

4kTR1

4kTR2

= thermal noise of RS



e =1

e =2

R2

R + R1 S

2

1 +R

2

R1

1 +R

2

R1

2

R2

R1

2

e + e +1 2

2 2E =

O

2e +

n

2e

s

2

e + e +1 2

2 2e

s

2e +

n

2

OPA1652OPA1654


Note: For the OPA165x series of op amps at 1kHz, en = 4.5nV/√Hz.

Figure 38. Noise Calculation in Gain Configurations





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R2

OPA165x

R1

Signal Gain = 1+

Distortion Gain = 1+

R3 V = 3 VO RMS

GeneratorOutput

AnalyzerInput

Audio Precision

System Two(1)

with PC Controller

SIGNAL

GAIN

DISTORTION

GAIN R1

R2

R3

¥

4.99 kW

1 kW

4.99 kW

10 W

49.9 W

+1

-1

101

549 W 4.99 kW 49.9 W+10 110

101R2

R1

R2

R II R1 3

Load

OPA1652OPA1654


TOTAL HARMONIC DISTORTION The validity of this technique can be verified byMEASUREMENTS duplicating measurements at high gain and/or high

frequency where the distortion is within theThe OPA165x series op amps have excellent measurement capability of the test equipment.distortion characteristics. THD + noise is below Measurements for this data sheet were made with an0.0002% (G = +1, VO = 3 VRMS, BW = 80 kHz) Audio Precision System Two distortion/noisethroughout the audio frequency range, 20 Hz to 20 analyzer, which greatly simplifies such repetitivekHz, with a 2-kΩ load (see Figure 7 for characteristic measurements. The measurement technique can,performance). however, be performed with manual distortion

measurement instruments.The distortion produced by the OPA165x series opamps is below the measurement limit of manycommercially available distortion analyzers. However, CAPACITIVE LOADSa special test circuit (such as Figure 39 shows) can

The dynamic characteristics of the OPA1652 andbe used to extend the measurement capabilities.OPA1654 have been optimized for commonly

Op amp distortion can be considered an internal error encountered gains, loads, and operating conditions.source that can be referred to the input. Figure 39 The combination of low closed-loop gain and highshows a circuit that causes the op amp distortion to capacitive loads decreases the phase margin of thebe gained up (refer to the table in Figure 39 for the amplifier and can lead to gain peaking or oscillations.distortion gain factor for various signal gains). The As a result, heavier capacitive loads must be isolatedaddition of R3 to the otherwise standard noninverting from the output. The simplest way to achieve thisamplifier configuration alters the feedback factor or isolation is to add a small resistor (RS equal to 50 Ω,noise gain of the circuit. The closed-loop gain is for example) in series with the output.unchanged, but the feedback available for error

This small series resistor also prevents excess powercorrection is reduced by the distortion gain factor,dissipation if the output of the device becomesthus extending the resolution by the same amount.shorted. Figure 19 illustrates a graph of Small-SignalNote that the input signal and load applied to the opOvershoot vs Capacitive Load for several values ofamp are the same as with conventional feedbackRS. Also, refer to Applications Bulletin AB-028without R3. The value of R3 should be kept small to(literature number SBOA015, available for downloadminimize its effect on the distortion measurements.from the TI web site) for details of analysistechniques and application circuits.

(1) For measurement bandwidth, see Figure 7 through Figure 12.

Figure 39. Distortion Test Circuit





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http://www.ti.com/lit/pdf/SBOA015

http://www.ti.com/lit/pdf/SBOA015



5 kW

Device10 mA max

V+

VIN

VOUT

IOVERLOAD

OPA1652OPA1654


POWER DISSIPATION

The OPA1652 and OPA1654 series op amps arecapable of driving 2-kΩ loads with a power-supplyvoltage up to ±18V and full operating temperaturerange. Internal power dissipation increases whenoperating at high supply voltages. Copper leadframeconstruction used in the OPA165x series op ampsimproves heat dissipation compared to conventionalmaterials. Circuit board layout can also help minimize Figure 40. Input Current Protectionjunction temperature rise. Wide copper traces helpdissipate the heat by acting as an additional heat An ESD event produces a short duration,sink. Temperature rise can be further minimized by high-voltage pulse that is transformed into a shortsoldering the devices to the circuit board rather than duration, high-current pulse as it discharges throughusing a socket. a semiconductor device. The ESD protection circuits

are designed to provide a current path around theELECTRICAL OVERSTRESS operational amplifier core to prevent it from beingdamaged. The energy absorbed by the protectionDesigners often ask questions about the capability ofcircuitry is then dissipated as heat.an operational amplifier to withstand electrical

overstress. These questions tend to focus on the When the operational amplifier connects into a circuit,device inputs, but may involve the supply voltage pins the ESD protection components are intended toor even the output pin. Each of these different pin remain inactive and not become involved in thefunctions have electrical stress limits determined by application circuit operation. However, circumstancesthe voltage breakdown characteristics of the may arise where an applied voltage exceeds theparticular semiconductor fabrication process and operating voltage range of a given pin. Should thisspecific circuits connected to the pin. Additionally, condition occur, there is a risk that some of theinternal electrostatic discharge (ESD) protection is internal ESD protection circuits may be biased on,built into these circuits to protect them from and conduct current. Any such current flow occursaccidental ESD events both before and during through ESD cells and rarely involves the absorptionproduct assembly. device.These ESD protection diodes also provide in-circuit, If there is an uncertainty about the ability of theinput overdrive protection, as long as the current is supply to absorb this current, external zener diodeslimited to 10 mA as stated in the Absolute Maximum may be added to the supply pins. The zener voltageRatings. Figure 40 shows how a series input resistor must be selected such that the diode does not turnmay be added to the driven input to limit the input on during normal operation.current. The added resistor contributes thermal noise

However, its zener voltage should be low enough soat the amplifier input and its value should be kept to athat the zener diode conducts if the supply pin beginsminimum in noise-sensitive applications.to rise above the safe operating supply voltage level.





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I L+OUT

Audio DACwith Differential

CurrentOutputs

OPA165x

8200 pF

100 W

I L-OUT

OPA165x

0.1 Fm

2200 pF

820 W

0.1 Fm

2700 pF

-VA

( 15 V)-

+VA

(+15 V)

680 W 620 W

330 W

-VA

( 15 V)-

+VA

(+15 V)

0.1 Fm

0.1 Fm

330 W 2700 pFOPA165x

0.1 Fm

2200 pF

820 W

0.1 Fm

-VA

( 15 V)-

+VA

(+15 V) 680 W 620 W

L ChOutput

OPA1652OPA1654


APPLICATION CIRCUIT

An additional application idea is shown in Figure 41.

Figure 41. Audio DAC I/V Converter and Output Filter





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PACKAGE OPTION ADDENDUM

www.ti.com 11-Apr-2013

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead/Ball Finish MSL Peak Temp(3)

Op Temp (°C) Top-Side Markings(4)

Samples

OPA1652AID ACTIVE SOIC D 8 75 Green (RoHS& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR -40 to 85 OP1652

OPA1652AIDGK ACTIVE VSSOP DGK 8 80 Green (RoHS& no Sb/Br)

CU NIPDAUAG Level-1-260C-UNLIM -40 to 85 OUPI

OPA1652AIDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS& no Sb/Br)

CU NIPDAUAG Level-1-260C-UNLIM -40 to 85 OUPI

OPA1652AIDR ACTIVE SOIC D 8 2500 Green (RoHS& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR -40 to 85 OP1652

OPA1654AID ACTIVE SOIC D 14 50 Green (RoHS& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA1654

OPA1654AIDR ACTIVE SOIC D 14 2500 Green (RoHS& no Sb/Br)


OPA1654AIPW ACTIVE TSSOP PW 14 90 Green (RoHS& no Sb/Br)


OPA1654AIPWR ACTIVE TSSOP PW 14 2000 Green (RoHS& no Sb/Br)


(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availabilityinformation and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement thatlead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used betweenthe die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weightin homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

http://www.ti.com/product/OPA1652?CMP=conv-poasamples#samplebuy








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PACKAGE OPTION ADDENDUM


Addendum-Page 2

(4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is acontinuation of the previous line and the two combined represent the entire Top-Side Marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device PackageType

PackageDrawing

Pins SPQ ReelDiameter

(mm)

ReelWidth

W1 (mm)

A0(mm)

B0(mm)

K0(mm)

P1(mm)

W(mm)

Pin1Quadrant

OPA1652AIDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

OPA1652AIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

OPA1654AIPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION


Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

OPA1652AIDGKR VSSOP DGK 8 2500 364.0 364.0 27.0

OPA1652AIDR SOIC D 8 2500 367.0 367.0 35.0

OPA1654AIPWR TSSOP PW 14 2000 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION


Pack Materials-Page 2

IMPORTANT NOTICE

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Documents

SBOS477 DECEMBER 2011 Low Noise and Distortion, General