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Resistive RAM (Resistive RAM (ReRAMReRAM) Technology ) Technology for High Density Memory Applicationsfor High Density Memory Applicationsfor High Density Memory Applicationsfor High Density Memory Applications
Sunjung KimSunjung [email protected]@samsung.com
S i d t R&D C tS i d t R&D C tSemiconductor R&D Center Semiconductor R&D Center SAMSUNG ElectronicsSAMSUNG Electronics
4th Workshop on Innovative Memory Technologies
Contents
Introduction• NAND Scaling Technologies & Barriers
Samsung Vertical ReRAM (VRRAM)• VRRAM vs. 3D cross-point
• ALD/CVD ReRAM Properties
• VRRAM Integration & Challenges
Selector-less Cell for VRRAM
• Review on Self-Rectifying Cell (SRC) TechnologiesReview on Self Rectifying Cell (SRC) Technologies
Conclusions
2 / 33
Scaling Technology of NAND Flash
Lith Sh i k A F i D bl PT Q d l PT Litho. Shrink : ArF-imm. Double-PT Quadruple-PT # of cells increase : 64 128 ? Vertical 3-D Stack Multi-Bit : 2 3 4 bit ? (data processing + ECC )
QPT/DPT
0.1
]
CG
Planar FGMulti‐bit
/DPT
64cell NAND1
10Rul
e [n
m]
FG
Air
Physical DR100Des
ign
STI
AirGap
3D NVM era2D NAND era
10001994 2004 2014 2024
Y2xnm NAND YearSource : 2010 IEDM, page 98 & page 103
2xnm NAND
3 / 33
Scaling Barriers of NAND Flash
Scaling Barriers seem difficult to be overcome from 10 nodes.WL-WL leakage : High PGM_V, Tun_Oxide (Etun.OX. ~ EWL) # of electron decrease : Cstorage (High-K) Bigger cell coupling : Thin storage, ECC
3D NVM[Parasitic capacitance
coupling of FG]
J.‐D. Lee, IEEE EDL,pp. 264‐266, 2002
3D NVM
4 / 33
Scaling Breakthrough with 3D Structures
Planar > VNAND for sub 20nm > VRRAM for sub 10nm scaling
TCAT (VNAND)
Planar > VNAND for sub-20nm > VRRAM for sub-10nm scaling
VRRAM (Vertical ReRAM)
ReRAM Cell
J H Jang Samsung 2009 VLSI Tech p 192 I G Baek Samsung 2011 IEDM p 737J.H. Jang, Samsung, 2009 VLSI Tech., p. 192. I.G. Baek, Samsung, 2011 IEDM, p. 737.
5 / 33
Contents
Introduction• NAND Scaling Challenges
Samsung Vertical ReRAM (VRRAM)• VRRAM vs. 3D cross-point
• ALD/CVD ReRAM Properties
• VRRAM Integration & Challenges
Selector-less Cell for VRRAM
• Review on Self-Rectifying Cell (SRC) TechnologiesReview on Self Rectifying Cell (SRC) Technologies
Conclusions
6 / 33
3D ReRAM Technology
7
Traditional 3D x-point array vs. innovative VRRAM structure
/ 33
C t # f C iti l k
Fabrication Cost of 3D X-point ReRAM
Cost ~ # of Critical masks The # of stacks is limited by the
affordable # of masks Cost effective # of stacks
< 8 stacks (4 stacks with DPT)
Cost ~ Lithography tools EUV must be used to reach
> 512Gb even with 2bit MLC Only 2 more generations may be
covered with 3D X-point ReRAM
Chip area x Cell efficiency 100mm2
3D X-point is only a temporary solution
8
Chip area x Cell efficiency = 100mm2, 2bit MLC, 4F2 unit cell assumed
I.G. Baek, Samsung, 2011 IEDM, p. 737.
/ 33
Scalability of VRRAM
Compared to 3D X-point, the # of critical masks relatively independent of the # of stacks.
Compared to VNAND, ~ smaller cell area and ~ shorter stack height
V-RRAMV-NANDPoly Switching material
~ shorter stack height.
WLWL e
ee
eee
• Short ch. effect
Vertical coupling
Poly channel
CTF stackElectrode
Switching material(direct tunneling limited > 5 nm)
•WL leakage
WLWL
• Vertical coupling
• Charge spreading
g
9
J.D. Choi, Samsung, 2011 VLSI, p. 178.
/ 33
Process Requirements of VRRAM
Cell material deposition with high step coverage
High A/R dry etching High A/R dry etching
Selective wet etching, treatment
Good diffusion barrier etch stopper materials Good diffusion barrier, etch stopper materials
Low heat budget
3D inspection methodology 3D inspection methodology
…
10/ 33
Contents
Introduction• NAND Scaling Challenges
Samsung Vertical ReRAM (VRRAM)• VRRAM vs. 3D cross-point
• ALD/CVD ReRAM Properties
• VRRAM Integration & Challenges
Selector-less Cell for VRRAM
• Review on Self-Rectifying Cell (SRC) TechnologiesReview on Self Rectifying Cell (SRC) Technologies
Conclusions
11/ 33
TMO : PVD Ta / ALD Ta2O5 ( ~ Ta2O5 x )
Reference Planar ReRAM
TMO : PVD Ta / ALD Ta2O5 ( Ta2O5-x ) Electrodes : PVD TiN (TE), CVD TiN (BEC) I_sw < 100uA, V_sw < 2.5V (pulse)
10
10-5 R ead @ 0.2 V10-3
SET V G :2 V
t_sw ~ 10ns Endurance > 1E6
10-7
10-6
10-5
ent (
A)
@
10-6
10-5
10-4
ent (
A)
SET V G : 2 VRESET V G :3 V
10-9
10-8
10
Cur
re
SET: 10ns/2.5V
RESET: 10ns/-2.5V10-9
10-8
10-7
Cur
re
SetReset
100 101 102 103 104 105 106 10710
Cycles (N)-2 -1 0 1 210
Drain Voltage (V)
1 order of S/W window with >1E6 endurance
12
I.G. Baek, Samsung, 2011 IEDM., p. 737.
/ 33
PVD-free Planar ReRAM
TMO : ALD Ta2O5 TMO : ALD Ta2O5
Electrodes : CVD TiN (TE, BEC) No memory switching : leaky
Cl f CVD TiN TE h TiN/T O i i i
TOF-SIMS depth profiles of
Cl from CVD TiN TE enhances TiN/Ta2O5 intermixing TaN, TaO generation at the interface
10-5
10-4
10-3
(A)
p pPVD TiN/ALD Ta2O5, CVD TiN/ALD Ta2O5
10-8
10-7
10-6
C
urre
nt
CV D TiN / A LD Ta2O 5
-3 -2 -1 0 1 2 310-9
Voltage (V)
No S/W window poor CVD TiN interface quality
13
No S/W window, poor CVD TiN interface qualityI.G. Baek, Samsung, 2011 IEDM., p. 737.
/ 33
ALD based diffusion barrier with optimum thickness
S/W Properties with a Diffusion Barrier
10-4
10-3
ALD based diffusion barrier with optimum thickness
10-7
10-6
10-5
rren
t (A
)
10-9
10-8
10
Cur
CV D TiN
Barrier + CV D TiN TaO x
Barrier layer
CV D TiN
-2 -1 0 1 210-10
Voltage (V)
CV D TiN TaO x
Reference S/W properties are reproduced with only CVD and ALD processes
14
I.G. Baek, Samsung, 2011 IEDM., p. 737.
/ 33
10-5
Reliabilities with a Diffusion Barrier
103
105
ail (
hr) 85oC10 years
180oC10-6
10
(A)
R ead @ 0.2 V
101
10
Ti
me
to fa
PV D (Ref.)
Barrier + CV D TiN
250oC
200oC
10-7
Cur
rent
SET: 10ns/2.5VRESET 10 / 2 5V
Barrier + CV D TiN
2.0 2.2 2.4 2.6 2.8 3.010-1
1000/T (1000/K)
T
CV D TiN
100 101 102 103 104 105 106 10710-8
Cycles (N)
RESET: 10ns/-2.5V CV D TiN
Endurance : > 1E6 Retention : ~ 10yrs @85C
No critical reliability degradation was observed with CVD TiN + ALD barrier
15
I.G. Baek, Samsung, 2011 IEDM., p. 737.
/ 33
Contents
Introduction• NAND Scaling Challenges
Samsung Vertical ReRAM (VRRAM)• VRRAM vs. 3D cross-point
• ALD/CVD ReRAM Properties
• VRRAM Integration & Challenges
Selector-less Cell for VRRAM
• Review on Self-Rectifying Cell (SRC) TechnologiesReview on Self Rectifying Cell (SRC) Technologies
Conclusions
16/ 33
V ti l NAND i l d
Process Integration of VRRAM (1/2)
Vertical NAND processes are mainly used except for the cell stack, vertical electrode and selection Tr.
17
I.G. Baek, Samsung, 2011 IEDM., p. 737.
/ 33
Process Integration of VRRAM (2/2)
VNAND (TCAT/BiCS) VRRAMStorage layer ONO TMO/Barrier
Vertical Channel Poly-Si TiN (VE)Horizontal Line W / poly Si (W/L) W (HE)
Selection Tr High V, Low I Low V, High IProcess Temp High (>700C) Low (<400C)
18
Process Temp. High (>700C) Low (<400C)I.G. Baek, Samsung, 2011 IEDM., p. 737.
/ 33
TMO : ALD Barrier / ALD Ta O
S/W Properties of VRRAM
TMO : ALD Barrier / ALD Ta2O5
Electrodes : CVD TiN (VE), CVD W/TiN (HE) I_sw < 80uA, V_sw < 4V
10-3
t_sw < 1us (due to high parasitic RC) Endurance > 1e2
10-6
10-5
nt (A
)
Read @ 0.2 V
6
10-5
10-4
10-3
nt (A
)
Ireset: 80 μA C.C : 50μA
8
10-7
10
Cur
ren
SET: 1μsec/4V
RESET: 1μsec/-5V10-8
10-7
10-6
Cur
ren
V R R A M
100 101 10210-8
Cycles (N)-4 -3 -2 -1 0 1 2 3 410-9
Voltage (V)
First reported results using PVD-free process in a vertical structure
19
p g p
I.G. Baek, Samsung, 2011 IEDM., p. 737.
/ 33
Challenges for VRRAM
Demonstrated VRRAM using cost effective 3D process.
But the major challenges for VRRAM include;
Demonstrated VRRAM using cost effective 3D process.
Self-Rectifying Cell (SRC) SRC reduces leakage currents and cell-to-cell disturbance bl l i enables larger array size
- Highly non-linear, asymmetric I-V characteristics are necessary
Hi h ll ffi i High cell efficiency Larger memory block with smaller overhead chip area
- Low operation current needed p- Layout optimization of driving circuits and vertical
interconnection are necessary
20
Developing SRC is most critical for VRRAM/ 33
Contents
Introduction• NAND Scaling Challenges
Samsung Vertical ReRAM (VRRAM)• VRRAM vs. 3D cross-point
• ALD/CVD ReRAM Properties
• VRRAM Integration & Challenges
Selector-less Cell for VRRAM
• Review on Self-Rectifying Cell (SRC) TechnologiesReview on Self Rectifying Cell (SRC) Technologies
Conclusions
21/ 33
Selector
½ V d h½ V read scheme and sneak current
Need selector (function) to avoid sneak current
22/ 33
Why Selector-less (Self-Rectifying) Cell
VRRAMDensity
H.S. Yoon, Samsung, VLSI Tech., 2009
Cross-pointProcess complexity Operation voltage Operation voltage
23
X.A. Tran, IEDM 2011
/ 33
SRC ExamplesISSCC 2010, LETI Memory W/S 2011 – Unity
• Current ratio 1000:1i i l ( )
24
• Epitaxial CMOx (ex. PrCaMnO)
/ 33
IEDM 2010 – Gwangju Inst. Sci. Tech. (GIST)
SRC Examples
• Back-to-back connection of HfO/ZrO stackBack to back connection of HfO/ZrO stack• Thick MIMIM stack
25/ 33
IEDM 2011 – Nanyang Tech. Univ. (NTU)
SRC Examples
• Simple n+Si/HfOx/Ni stackSimple n+Si/HfOx/Ni stack• Uni-polar switching
26/ 33
VLSI 2012 – Macronix
SRC Examples
• 0T1R CBRAM array0T1R CBRAM array• SiO/HfO stack + Cu-GST layer
27/ 33
In Short ...
Targeting to what Unity presented in this W/S last year.
But using fab-friendly materials (transition metal oxides)
LETI Memory W/S 2011 – Unity
28
LETI Memory W/S 2011 – Unity
/ 33
Contents
Introduction• NAND Scaling Challenges
Samsung Vertical ReRAM (VRRAM)• VRRAM vs. 3D cross-point
• ALD/CVD ReRAM Properties
• VRRAM Integration & Challenges
Selector-less Cell for VRRAM
• Review on Self-Rectifying Cell (SRC) TechnologiesReview on Self Rectifying Cell (SRC) Technologies
Conclusions
29/ 33
Conclusions
1. Vertical ReRAM (VRRAM) has been successfully demonstrated as a cost effective post-NAND solution.
2. Compared to the 3D X-point ReRAM, VRRAM has advantages when stacking >8 stacks with relaxed patterning technology. g g gWe expect VRRAM technology can be extensible beyond 1Tb era with ArF-i tools.
3. Self-rectifying cell technology would be main challenges for VRRAM production.
30/ 33
One Day ...
31/ 33
32/ 33
Acknowledgement
In Gyu Baek & Jungdal ChoiIn-Gyu Baek & Jungdal Choi
Advanced Process Development Team
S i d t R&D C tSemiconductor R&D Center
Samsung Electronics
33/ 33