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  • RABBIT 6000 MICROPROCESSOR · 2018. 2. 12. · 010 = crc-16 ibm (usb) 011 = crc-16 ccitt 100 =...
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RABBIT ® 6000 MICROPROCESSOR RABBIT ® 6000 MICROPROCESSOR Read/Write Write Only Read Only Read (Special Behavior on Write Operation) REGISTER LEGEND NOTE: ZERO MUST BE WRITTEN TO ALL UNUSED BITS Processor Control GLOBAL CPU CONFIGURATION REGISTER GCPU (0x002E) GLOBAL REVISION REGISTER GREV (0x002F) 0 = FETCH PER SMODE 1 = IGNORE SMODE RD ONLY SMODE CPU VERSION (GCPU) REVISION (GREV) 7 0 PROCESSOR MODE SELECT BOOTSTRAP OPERATION BOOTSTRAP DISABLED. NORMAL PROCESSOR OPERATION(CODE FETCHED FROM MEMORY) SLAVE PORT. SPD0R USED FOR BOOTSTRAP OPERATION SYNCHRONOUS SERIAL. CLOCKED SERIAL PORT A ON PARALLEL PORT C USED FOR BOOTSTRAP OPER. MAX EXTERNAL CLOCK RATE = PCLK/6 SMODE1 SMODE0 0 0 0 1 1 0 1 1 ASYNCHRONOUS SERIAL. ASYNCH SERIAL PORT A ON PARALLEL PORT C USED FOR BOOTSTRAP OPER. REQUIRED BAUD RATE = 2400 REVISION IDENTIFIERS CPU Revision RABBIT 6000 BGA292 0x04 0x00 GLOBAL POWER SAVE CONTROL REGISTER GPSCR (0x000D) 000 = SELF-TIMED CS DISABLE 001 = 230 ns 010 = 170 ns 011 = 110 ns 100 = 290 ns 101 = 230 ns 110 = 170 ns 111 = 110 ns 0 = NORMAL CS FOR READS 1 = SHORT CS TIMING FOR READS # 0 = NORMAL CS FOR WRITES 1 = SHORT CS TIMING FOR WRITES # 7 0 RESERVED SELF-TIMED CS READ ONLY SELF-TIMED CS READ AND WRITE CPU & PCLK 000 = 32 kHz 001 01X 100 = 16.3848 kHz 101 = 8.192 kHz 110 = 4.096 kHz 111 = 2.048 kHz #(NOT AVAILABLE AT FULL SPEED) GLOBAL OUTPUT CONTROL REGISTER GOCR (0x000E) /BUFEN OUTPUT 00 = LOW FOR EXTERNAL I/O CYCLE 01 = LOW FOR DATA MEMORY ACCESS 10 = LOW 11 = HIGH STATUS OUTPUT 00 = LOW DURING FIRST OPCODE FETCH 01 = LOW DURING INTERRUPT ACKNOWLEDGE 10 = LOW 11 = HIGH /WDTOUT OUTPUT 00 = LOW DURING WD TIMEOUT 01 = TEST MODE (INTERNAL USE) 10 = LOW PULSE (1–2 CYCLES @ 32 kHz) CLK OUTPUT 00 = CLK = PCLK 01 = CLK = PCLK/2 10 = CLK = LOW 11 = CLK = HIGH 7 0 0 GLOBAL CLOCK MODULATOR REGISTERS GCM0R (0x000A) 00 = 1 ns DITHER 01 = 0.5 ns DITHER 10 = 2 ns DITHER RESERVED MUST = 0 7 0 0 SYSTEM PLL LOOP DIVIDER GCM1R (0x000B) 0 = SPREADER OFF 1 = SPREADER ON RESERVED MUST = 0 7 0 0 0 0 SYSTEM PLL PREDIVIDER GLOBAL CLOCK DOUBLE REGISTER GCDR (0x000F) 00000 = CLOCK DOUBLE DISABLED 00001 6 ns 00010 7 ns 00011 8 ns 00100 9 ns 00101 10 ns 00110 11 ns 00111 12 ns 01000 13 ns 01001 14 ns 01010 15 ns 01011 16 ns 01100 17 ns 01101 18 ns 01110 19 ns 01111 20 ns 10001 3 ns 10010 4 ns 10011 5 ns RESERVED MUST = 0 7 0 0 0 CLOCK DOUBLE ENABLED, TYPICAL CLOCK LOW TIME 0 = DISABLE SYSTEM PLL 1 = ENABLE SYSTEM PLL 00 PERIODIC INTERRUPT = DISABLE 01 PERIODIC INTERRUPT = PRIORITY 1 10 PERIODIC INTERRUPT = PRIORITY 2 11 PERIODIC INTERRUPT = PRIORITY 3 000 CPU = OSC/8; PCLK = OSC/8 001 CPU = OSC/8; PCLK = OSC 010 CPU = OSC; PCLK = OSC 011 CPU = OSC/2; PCLK = OSC/2 100 CPU = 32 kHz; PCLK = 32 kHz; MAIN OSC ON 101 CPU = 32 kHz; PCLK = 32 kHz; MAIN OSC OFF 110 CPU = OSC/4; PCLK = OSC/4 111 CPU = OSC/6; PCLK = OSC/6 000 = NO TIMEOUT 010 = WATCHDOG TIMEOUT 110 = HARDWARE RESET 111 = POWER-ON RESET PERIODIC INTERRUPT = 32 kHz/16 (488 ms) PCLK = PERIPHERAL CLOCK CPU = CPU CLOCK OSC = DOUBLED OR NON-DOUBLED CLOCK PERIODIC INTERRUPT OSC 7 0 GLOBAL CONTROL/STATUS REGISTER GCSR (0x0000) MASTER SYSTEM CONFIGURATION REGISTER MSCR (0x0434) 7 0 0 = CPU CLOCK FROM MAIN OSC 1 = CPU CLOCK FROM SYSTEM PLL 0 0 = ETH PHY CLOCK FROM MAIN OSC 1 = ETH PHY CLOCK FROM EXTERNAL PHY OSC 1 = RESET ETH PHY 00 = FIM B DISABLED 01 = FIM B CLOCK FROM CPU CLOCK 11 = FIM B CLOCK FROM MAIN PLL 00 = FIM A DISABLED 01 = FIM A CLOCK FROM CPU CLOCK 11 = FIM A CLOCK FROM MAIN PLL MASTER SYSTEM STATUS REGISTER MSSR (0x0435) 7 0 0 0 0 0 0 = WIFI DIRECT CLOCK 1 = WIFI EXTERNAL XTAL 0 = USB DIRECT CLOCK 1 = USB EXTERNAL XTAL 0 = RD: WIFI PLL NOT READY 1 = RD: WIFI PLL READY 0 = RD: SYSTEM PLL NOT READY 1 = RD: SYSTEM PLL READY 7 0 DATA BUS PIN CONTROL REGISTER DDPCR (0x04A1) 00 = 4mA OUTPUT DRIVE 01 = 8mA OUTPUT DRIVE 10 = 10mA OUTPUT DRIVE 11 = 14mA OUTPUT DRIVE 0 = FAST OUTPUT SLEW 1 = SLOW OUTPUT SLEW 0 0 0 00 = NO PULLUP/DOWN 01 = 75KOHM PULLUP 10 = 75KOHM PULLDOWN 11 = 75KOHM KEEPER 7 0 PIN CONTROL REGISTERS ADPCR (0x04A0) CPCR (0x04A2) IOPCR (0x04A3) 00 = 4mA OUTPUT DRIVE 01 = 8mA OUTPUT DRIVE 10 = 10mA OUTPUT DRIVE 11 = 14mA OUTPUT DRIVE 0 = FAST OUTPUT SLEW 1 = SLOW OUTPUT SLEW 0 0 0 0 0 Parallel Ports Error Check and Correct ECC CONTROL REGISTER ECCR (0x05C4) 0 = DISABLE/INITIALIZE ECC/CRC 1 = ENABLE ECC/CRC 7 0 0 000 = ECC, 256-65K BYTE BLOCKS 001 = CRC-32 (IEEE 802) 010 = CRC-16 IBM (USB) 011 = CRC-16 CCITT 100 = CRC-15 (CAN) 0 0 = READ DATA NOT INVERTED 1 = READ DATA INVERTED 0 = INITIAL VALUE ALL ZEROS 1 = INITIAL VALUE ALL ONES ECC DATA x REGISTER ECD0R (0x05C0) ECD1R (0x05C1) ECD2R (0x05C2) ECD3R (0x05C3) 0 7 RD: LP/CRC BITS 31:0 WR: DATA BYTE FOR ECC/CRC ECC CP READ REGISTER ECPR (0x05C5) 0 7 RD: {00, CP VALUE} WR: {00, CP SET VALUE} ECC CP READ SHIFTED REGISTER ECPSR (0x05C6) 0 7 RD: {CP VALUE, 00} WR: {00, CP SET VALUE} ECC WRITE x REGISTER ECW0R (0x05C7) ECW1R (0x05C8) ECW2R (0x05C9) ECW3R (0x05A) 0 7 RD: LP/CRC BITS 0:31 (REVERSE BIT ORDER) WR: DATA BYTE FOR ECC/CRC ECC COUNT x REGISTER ECC0R (0x05C7) ECC1R (0x05C8) 0 7 RD: ECC COUNTER BITS 15:0 WR: SET ECC COUNTER BITS 15:0 www.digi.com 91001614 A1/410 (USES TIMER A9) Pulse Width Modulation PWM 0 REGISTERS PWM0R (0x0089) PWL0R (0x0088) 7 0 7 0 10-BIT PWM COUNT 00 = NORMAL PWM OPERATION 01 = SUPPRESS PWM OUTPUT 7/8 ITERATIONS 10 = SUPPRESS PWM OUTPUT 3/4 ITERATIONS 11 = SUPPRESS PWM OUTPUT 1/2 ITERATIONS 00 = INTERRUPTS DISABLED 01 = PRIORITY 1 INTERRUPT 10 = PRIORITY 2 INTERRUPT 11 = PRIORITY 3 INTERRUPT 0 = SINGLE-PULSE PWM 1 = SPREAD PWM 0 PWM 2 AND 3 REGISTERS PWM2R (0x008D) PWL2R (0x008C) PWM3R (0x008F) PWL3R (0x008E) 7 0 7 0 10-BIT PWM COUNT 00 = NORMAL PWM 1 OPERATION 01 = SUPPRESS PWM 1 OUTPUT 7/8 ITERATIONS 10 = SUPPRESS PWM 1 OUTPUT 3/4 ITERATIONS 11 = SUPPRESS PWM 1 OUTPUT 1/2 ITERATIONS 0 = SINGLE-PULSE PWM 1 = SPREAD PWM 0 0 0 PWM BLOCK ACCESS REGISTER PWBAR (0x00E8) 0 7 ACCESS PWM REGISTER POINTED TO BY PWBPR PWM BLOCK POINTER REGISTER PWBPR (0x00E9) 0 7 LSBs OF PWM REGISTER 0 0 0 1 1 PWM 1 REGISTERS PWM1R (0x008B) PWL1R (0x008A) 7 0 7 0 10-BIT PWM COUNT 00 = NORMAL PWM OPERATION 01 = SUPPRESS PWM OUTPUT 7/8 ITERATIONS 10 = SUPPRESS PWM OUTPUT 3/4 ITERATIONS 11 = SUPPRESS PWM OUTPUT 1/2 ITERATIONS 00 = NORMAL PWM INTERRUPT 01 = SUPPRESS PWM INT 7/8 ITERATIONS 10 = SUPPRESS PWM INT 3/4 ITERATIONS 11 = SUPPRESS PWM INT 1/2 ITERATIONS 0 = SINGLE-PULSE PWM 1 = SPREAD PWM 0 Quadrature Decoder (USES TIMER A10) QUAD DECODE CONTROL/STATUS REGISTER QDCSR (0x0090) 1 = QD2 = INCREMENTED FROM MAX 0x00 7 0 1 = QD2 = DECREMENTED FROM 0x00 MAX RESET QD2, NO INTERRUPT 1 = QD1 = INCREMENTED FROM MAX 0x00 1= QD1 = DECREMENTED FROM 0x00 MAX RESET QD1, NO INTERRUPT 0 0 QUAD DECODE CONTROL REGISTER QDCR (0x0091) 0 = 8-BIT COUNTER 1 = 10-BIT COUNTER 00 = QD2 INPUT DISABLED 01 = QD2 INPUT FROM PD3 & PD2 10 = QD2 INPUT FROM PE3 & PE2 11 = QD2 INPUT FROM PE7 & PE6 7 0 0 00 = QD INTERRUPT DISABLED 01 = PRIORITY 1 INTERRUPT 10 = PRIORITY 2 INTERRUPT 11 = PRIORITY 3 INTERRUPT 00 = QD1 INPUT DISABLED 01 = QD1 INPUT FROM PD1 & PD0 10 = QD1 INPUT FROM PE1 & PE0 11 = QD1 INPUT FROM PE5 & PE4 QUAD DECODE COUNT REGISTER QDC1R (0x9004) QDC2R (0x0096) 0 7 BITS 0-7 OF QD COUNT QUAD DECODE HIGH COUNT REGISTER QDC1HR (0x0095) QDC2HR (0x0097) 0 7 BITS 8-9 OF QD COUNT 0 0 0 0 0 0 I 2 C (Serial Port G) NOT ALL REGISTERS DISPLAYED; SEE PROCESSOR MANUAL FOR MORE DETAILS. SERIAL PORT G CLOCK DIVISION x REGISTER SPGCD0R (0x0588) SPGCD1R (0x0589) SPGCD2R (0x058A) 0 7 18-BIT DIVIDER FOR I2C CLOCK SERIAL PORT G MAIN CONTROL REGISTER SPGMCR (0x059F) 7 0 0 00 = I2C INTERRUPT DISABLED XX = INTERRUPT PRIORITY 0 0 0 = SCL ON PE1 1 = SCL ON PE5 0 = SDA ON PE0 1 = SDA ON PE4 7 0 0 = NO INTERRUPT ON ADDRESS MATCH 1 = INTERRUPT ON ADDRESS MATCH 0 = NO INTERRUPT ON START CONDITION 1 = INTERRUPT ON START CONDITION 0 = NO INTERRUPT ON ARBITRATION LOST 1 = INTERRUPT ON ARBITRATION LOST 0 = NO INTERRUPT ON STOP CONDITION 1 = INTERRUPT ON STOP CONDITION 0 = NO INTERRUPT ON NON-ACK 1 = INTERRUPT ON NON-ACK 0 = NO INTERRUPT ON RX COMPLETE 1 = INTERRUPT ON RX COMPLETE SERIAL PORT G CONTROL 1 REGISTER SPG1R (0x0581) 0 = NO INTERRUPT ON TX COMPLETE 1 = INTERRUPT ON TX COMPLETE 0 SERIAL PORT G CONTROL 0 REGISTER SGC0R (0x0580) 7 0 0 = PULL SCL LOW 1 = READY TO RCV/XMIT 1 = INITIATE STOP CONDITION (MASTER) 0 = SEND ACK 1 = SEND NACK 1 = INITIATE START CONDITION (MASTER) 0 = NO RESPONSE TO GENERAL CALL 1 = ENABLE RESPONSE 0 = SLAVE MODE 1 = MASTER MODE 1 = RESET I2C (AUTOMATICALLY CLEARED) 0 = DISABLE I2C 1 = ENABLE I2C 7 0 0 = NO BYTE RECEIVED 1 = BYTE RECEIVED 0 = NO STOP CONDITION 1 = STOP CONDITION DETECTED 0 = NO NON-ACK RESPONSE 1 = NON-ACK RESPONSE DETECTED 0 = NO BYTE TRANSMITTED 1 = BYTE TRANSMITTED 0 = I2C BUS NOT BUSY 1 = I2C BUS BUSY 0 = I2C CONTROLLER NOT BUSY 1 = I2C CONTROLLER BUSY SERIAL PORT G STATUS 0 REGISTER SPS0R (0x0584) 0 = NO NON-ACK SENT OR RECEIVED 1 = NON-ACK SEND OR RECEIVED 0 = I2C NOT IN MASTER-RX OR SLAVE-TX 1 = I2C IN MASTER-RX OR SLAVE-TX SERIAL PORT G STATUS 1 REGISTER SPS1R (0x0585) 0 = NO SLAVE ADDRESS MATCH 1 = SLAVE ADDRESS MATCH 7 0 0 0 = NO GENERAL CALL ADDRESS MATCH 1 = GENERAL CALL ADDRESS MATCH 0 0 0 = NO START CONDITION DETECTED 1 = START CONDITION DETECTED 0 = ARBITRATION NOT LOST 1 = ARBITRATION LOST 0 SERIAL PORT G DATA REGISTER SPGDR (0x058C) 0 7 RD: BYTE RECEIVED ON I2C BUS WR: BYTE TO BE SENT ON I2C BUS SERIAL PORT G SLAVE ADDRESS 0 REGISTER SPGSA0R (0x0580) 0 7 SLAVE ADDRESS BITS 7:0 SERIAL PORT G SLAVE ADDRESS 1 REGISTER SPGSA1R (0x0581) 0 7 SLAVE ADDRESS BITS 9:8 0 0 0 0 0 0 SERIAL PORT G SLAVE ADDRESS 3 REGISTER SPGSA3R (0x0583) 0 7 0 = USE 7-BIT ADDRESSING 1 = USE 10-BIT ADDRESSING 0 0 0 0 0 0 0 0 Real-Time Clock REAL-TIME CLOCK CONTROL REGISTER RTCCR (0x0001) 01 = THIS BIT COMBINATION MUST BE USED WITH EVERY BYTE INCREMENT WRITE 0 = NO EFFECT ON RTC COUNTER 1 = INCREMENT CORRESPONDING BYTE OF RTC (RTCxB) 7 0 RTC5B RTC4B RTC3B RTC2B RTC1B RTC0B RTCCR (SHORTCUTS) 0x00 = NO EFFECT ON RTC COUNTER DISABLE BYTE INCREMENT CANCEL RTC COMMAND 0x40 = ARM RTC FOR RESET OR BYTE INCREMENT. THIS COMMAND MUST BE WRITTEN PRIOR TO RTC RESET OR FIRST BYTE RESET 0x80 = RESET ALL SIX BYTES OF RTC TO 0x00. RESET MUST BE PRECEDED BY WRITING 0x40 TO ARM RESET FUNCTION 0xC0 = RESET ALL SIX BYTES IN RTC COUNTER TO 0x00 AND REMAIN IN BYTE INCREMENT MODE 7 0 REAL-TIME CLOCK x REGISTER 7 0 RD = CURRENT VALUE OF 48-BIT RTC HOLDING REGISTER IS RETURNED W = A WRITE TO RTC0R TRANSFERS CURRENT COUNT OF RTC TO HOLDING REGISTER RTC0R (0x0002) R/W RTC1R (0x0003) RD RTC2R (0x0004) RD RTC3R (0x0005) RD RTC4R (0x0006) RD RTC5R (0x0007) RD Slave Port SPD0R (0x0020) RD SA[1:0] /SLAVE ATTENTION /SRD /SWR /SCS SD[7:0] SLAVE PORT DATA REGISTERS INPUT REGISTERS OUTPUT REGISTERS SPD1R (0x0021) RD SPD2R (0x0022) RD SPD0R (0x0020) WR SPD1R (0x0021) WR SPD2R (0x0022) WR MASTER CONTROL LOGIC RABBIT CPU SLAVE PORT STATUS REGISTER SPSR (0x0023) 7 0 WRITE CORRESPONDING PORT STATUS 0 = EMPTY 1 = FULL READ CORRESPONDING PORT STATUS 0 = EMPTY 1 = FULL 0 = PROCESSOR WROTE TO SPSR 1 = MASTER WROTE TO SPD0R 0 = MASTER WROTE TO STATUS REG 1 = PROCESSOR WROTE TO SPD0R SLAVE PORT CONTROL REGISTER SPCR (0x0024) 0 = PROGRAM FETCH AS A FUNCTION OF SMODE PINS 1 = IGNORE SMODE PINS (RD) = REPORT STATE OF SMODE PINS (WR) = IGNORED FOR WRITE 000 = DISABLE SLAVE PORT. PORT A IS BYTE WIDE INPUT 001 = DISABLE SLAVE PORT. PORT A IS BYTE WIDE OUTPUT 010 = ENABLE SLAVE PORT. /SCS ON PE7 011 = ENABLE EXT I/O BUS. ADDR BUS ON PB[7:2] 110 = ENABLE SLAVE PORT. /SCS ON PB6 111 = ENABLE EXT I/O BUS. ADDR BUS ON PB[7:0] 00 = SLAVE PORT INTERRUPT DISABLED 01 = PRIORITY 1 INTERRUPT 10 = PRIORITY 2 INTERRUPT 11 = PRIORITY 3 INTERRUPT 7 0 Flexible Interface Modules NOT ALL REGISTERS DISPLAYED; SEE PROCESSOR MANUAL FOR MORE DETAILS. MASTER SYSTEM RESET REGISTER MSCR (0x0436) 7 0 0 = CLEAR FIM B RESET 1 = RESET FIM B 0 0 0 = CLEAR FIM A RESET 1 = RESET FIM A 0 0 0 0 7 0 0 = NORMAL PORT F 1 = FIM CONTROLS PORT F 0 = NORMAL PORT H 1 = FIM CONTROLS PORT H 0 = NORMAL PORT G 1 = FIM CONTROLS PORT G 0 = NORMAL PORT E 1 = FIM CONTROLS PORT E 0 = NORMAL PORT D 1 = FIM CONTROLS PORT D 0 = NORMAL PORT C 1 = FIM CONTROLS PORT C PORT OVERRIDE CONTROL REGISTER POCR (0x0438) 0 = NORMAL PORT B 1 = FIM CONTROLS PORT B 0 = NORMAL PORT A 1 = FIM CONTROLS PORT A External I/O I/O CONTROL BANK REGISTER IB7CR IB6CR IB5CR IB4CR IB3CR IB2CR IB1CR IB0CR (0x0087) I7 (0x0086) I6 (0x0085) I5 (0x0084) I4 (0x0083) I3 (0x0082) I2 (0x0081) I1 (0x0080) I0 PORT SIGNAL 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 I/O ADDRESS A15 A14 A13 7 0 0 = WRITES NOT ALLOWED 1 = WRITES ALLOWED I/O STROBE FUNCTIONS (IX) 00 = I/O /CS 01 = I/O /RD STROBE 10 = I/O /WR STROBE 11 = I/O DATA (/RD OR /WR) STROBE WAITS STATES 00 = 15 WS 01 = 7 WS 10 = 3 WS 11 = 1 WS I/O BANK x CONTROL REGISTER (IBxCR) 0 = ACTIVE LOW STROBE 1 = ACTIVE HIGH STROBE 0 = NORMAL I/O TRANSACTION TIMING 1 = SHORTEN READ/WRITE STROBES 0 = USE I/O BUS IF ENABLED 1 = ALWAYS USE MEMORY DATA BUS I/O HANDSHAKE CONTROL REGISTER IHCR (0x0028) 7 0 0 0 0 0 0 = I/O HANDSHAKE ACTIVE LOW 1 = I/O HANDSHAKE ACTIVE HIGH 000 = HANDSHAKE WITH PE0 001 = HANDSHAKE WITH PE1 010 = HANDSHAKE WITH PE2 011 = HANDSHAKE WITH PE3 100 = HANDSHAKE WITH PE4 101 = HANDSHAKE WITH PE5 110 = HANDSHAKE WITH PE6 111 = HANDSHAKE WITH PE7 I/O HANDSHAKE SELECT REGISTER IHSR (0x0029) 0 = DISABLE HANDSHAKE FOR I/O BANK 1 = ENABLE HANDSHAKE FOR I/O BANK 0 7 I/O HANDSHAKE TIMEOUT REGISTER IHTR (0x002A) 0 = NO TIMEOUT OCCURRED 1 = TIMEOUT OCCURRED 0 7 HANDSHAKE TIMEOUT COUNTER IN UNITS OF 32 CLOCKS 0 EXTENDED REGISTER (0x045F) (0x045D) (0x045B) (0x0459) (0x0457) (0x0455) (0x0453) (0x0451) I/O BANK x EXTENDED REGISTER 7 0 0 0 0 0 0 = I/O BANK IS 8-BIT 1 = I/O BANK IS 16-BIT 000 = USE CPU CLOCK 100 = USE CPU CLOCK/2 101 = USE CPU CLOCK/4 110 = USE CPU CLOCK/8 111 = USE CPU CLOCK/16 Timer B TIMER B CONTROL/STATUS REGISTER TBCSR (0x00B0) 7 0 0 0 0 0 0 (WRITE) 0 = CORRESPONDING INTERRUPT IS DISABLED 1 = CORRESPONDING INTERRUPT IN ENABLED 0 = TIMMER B CLOCK (PCLK/2) IS DISABLED 1 = TIMER B CLOCK (PCLK/2) IS ENABLED (READ) 0 = CORRESPONDING HAS NOT ENCOUNTERED A MATCH 1 = CORRESPONDING INT. HAS ENCOUNTERED A MATCH (STATUS BITS AND INTERUPTS ARE CLEARED BY READ OF THIS REGISTER) TIMER B MATCH 1 REGISTER BIT9 BIT7 (LSB) (MSB) BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 BIT8 0 0 0 0 0 0 TBM1R (0x00B2) TBL1R (0x00B3) TIMER B MATCH 2 REGISTER BIT9 BIT7 (LSB) (MSB) BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 BIT8 0 0 0 0 0 0 TBM2R (0x00B4) TBL2R (0x00B5) TIMER B COUNT REGISTER BIT9 BIT7 (LSB) (MSB) BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 BIT8 0 0 0 0 0 0 TBCMR (0x00BE) TBCLR (0x00BF) TIMER B CONTROL REGISTER TBCR (0x00B1) 0 7 0 0 0 = NORMAL B2 OPERATION 1 = B2 USES STEP REGS 0 = NORMAL B1 OPERATION 1 = B1 USES STEP REGS 00 = CLOCKED BY PCLK/2 01 = CLOCKED BY TIMER A1 10 = CLOCKED BY PCLK/16 11 = CLOCKED BY A11 00 = INTERRUPTS DISABLED 01 = PRIORITY 1 INTERRUPT 10 = PRIORITY 2 INTERRUPT 11 = PRIORITY 3 INTERRUPT TIMER B STEP LSB x REGISTER TBSL1R (0x00BA) TBSL2R (0x00BC) 0 7 LSB OF STEP SIZE FOR COMPARATOR TIMER B STEP MSB x REGISTER TBSM1R (0x00BB) TBSM2R (0x00BD) 0 7 MSB OF STEP SIZE FOR COMPARATOR 0 0 0 0 0 0 Timer C TIMER C CONTROL/STATUS REGISTER TCCSR (0x0500) 7 0 0 0 0 0 0 0 0 = LIMIT NOT REACHED 1 = LIMIT REACHED 0 = TIMER C CLOCK (PCLK/2) IS DISABLED 1 = TIMER C CLOCK (PCLK/2) IS ENABLED TIMER C DIVIDER LOW REGISTER TCDLR (0x0502) 0 7 TIMER C DIVIDER HIGH REGISTER TCDHR (0x0503) 8 15 TIMER C SET x LOW REGISTER TCS0LR (0x0508) TCS1LR (0x050C) TCS2LR (0x0518) TCS3LR (0x051C) 0 7 TIMER C SET x HIGH REGISTER TCS0HR (0x0509) TCS1HR (0x050D) TCS2HR (0x0519) TCS3HR (0x051D) 8 15 TIMER C BLOCK ACCESS REGISTER TCBAR (0x00F8) 0 7 ACCESS REGISTER POINTED TO BY TCBPR TIMER C BLOCK POINTER REGISTER TCDBPR (0x00F9) 0 7 LSB OF REGISTER ADDRESS 0 0 0 TIMER C RESET x LOW REGISTER TCR0LR (0x050A) TCR1LR (0x050E) TCR2LR (0x051A) TCR3LR (0x051E) 0 7 TIMER C RESET x HIGH REGISTER TCR0HR (0x050B) TCR1HR (0x050F) TCR2HR(0x051B) TCR3HR (0x051F) 8 15 TIMER C CONTROL REGISTER TCCR (0x0501) 00 = CLOCKED BY PCLK/2 01 = CLOCKED BY TIMER A1 10 = CLOCKED BY PCLK/16 11 = CLOCKED BY A11 00 = INTERRUPTS DISABLED 01 = PRIORITY 1 INTERRUPT 10 = PRIORITY 2 INTERRUPT 11 = PRIORITY 3 INTERRUPT 7 0 0 0 0 0 Timer A 7 0 TMRA7 TMRA6 TMRA5 TMRA4 TMRA3 TMRA2 TMRA1 (WRITE) 0 = CORRESPONDING TIMER A INTERRUPT IS DISABLED 1 = CORRESPONDING TIMER A INTERRUPT IS ENABLED 0 = TIMER A CLOCK IS DISABLED 1 = TIMER A CLOCK IS ENABLED (READ) 0 = CORRESPONDING TIMER A HAS NOT REACHED TERM. COUNT 1 = CORRESPONDING TIMER A HAS REACHED TERM. COUNT TIMER A CONTROL/STATUS REGISTER / TACSR (0x00A0) RESULTS IN ALL TIMER A TIMERS TO BE CLOCKED BY PCLK OR PCLK/2 TIMER A PRESCALE REGISTER / TAPR (0x00A1) 7 0 TIMER A CLOCK DIVIDER 7 0 TMRA7 TMRA6 TMRA5 TMRA4 0 = CORRESPONDING TIMER CLOCKED BY MAIN TIMER A CLK 1 = CORRESPONDING TIMER CLOCKED BY TIMER A1 00 = INTERRUPTS DISABLED 01 = PRIORITY 1 INTERRUPT 10 = PRIORITY 2 INTERRUPT 11 = PRIORITY 3 INTERRUPT TIMER A CONTROL REGISTER / TACR (0x00A4) TMRA3 TMRA2 TIMER A EXTENDED CONTROL REGISTER TAECR (0x00A2) 0 7 0 0 0 = TIMER A11 CLOCKED BY TAPR 1 = TIMER A11 CLOCKED BY A12 0 = TIMER A10 CLOCKED BY TAPR 1 = TIMER A10 CLOCKED BY A12 0 0 0 = TIMER A9 CLOCKED BY TAPR 1 = TIMER A9 CLOCKED BY A12 0 = TIMER A8 CLOCKED BY TAPR 1 = TIMER A8 CLOCKED BY A12 TIMER CONSTANT REGISTERS TIMER TAT1R (0x00A3) TAT2R (0x00A5) TAT3R (0x00A7) TAT4R (0x00A9) TAT5R (0x00AB) TAT6R (0x00AD) TAT7R (0x00AF) TAT8R (0x00A6) TAT9R (0x00A8) TAT10R (0x00AA) TAT11R (0x00AC) TAT12R (0x00AE) CASCADE FROM PERIPHERAL VARIOUS SERIAL PORT E SERIAL PORT F SERIAL PORT A SERIAL PORT B SERIAL PORT C SERIAL PORT D INPUT CAPTURE PWM QUADRATURE DECODER TIMERS B AND C TIMERS A8-A11 NONE A1 A1 A1 A1 A1 A1 A12 A12 A12 A12 NONE Breakpoints BREAKPOINT CONTROL REGISTER B0CR (0x030B) B4CR (0x034B) B1CR (0x031B) B5CR (0x036B) B2CR (0x032B) B6CR (0x037B) B3CR (0x0033B) 0 7 0 0 00 = NO BKPT ON EXECUTE MATCH 01 = BKPT ON USER EXECUTE MATCH 10 = BKPT ON SYSTEM EXECUTE MATCH 11 = BKPT ON SYS OR USER EXECUTE MATCH 00 = NO BKPT ON READ MATCH 01 = BKPT ON USER READ MATCH 10 = BKPT ON SYSTEM READ MATCH 11 = BKPT ON SYS OR USER READ MATCH 00 = NO BKPT ON WRITE MATCH 01 = BKPT ON USER WRITE MATCH 10 = BKPT ON SYSTEM WRITE MATCH 11 = BKPT ON SYS OR USER WRITE MATCH RESERVED MUST = 0 RD = CORRESPONDING BREAKPOINT IS PENDING. CLEARED WHEN THIS REGISTER READ WR = MAKE CORRESPONDING BREAKPOINT PENDING 7 0 BREAKPOINT/DEBUG CONTROL REGISTER BDCR (0x001C) 0 = NORMAL RST28 1 = RST28 = NOP BREAKPOINT ADDRESS REGISTERS B0A2R (0x030E) B0A1R (0x030D) B0A0R (0x030C) B1A2R (0x031E) B1A1R (0x031D) B1A0R (0x031C) B2A2R (0x032E) B2A1R (0x032D) B2A0R (0x032C) B3A2R (0x033E) B3A1R (0x033D) B3A0R (0x033C) B4A2R (0x034E) B4A1R (0x034D) B4A0R (0x034C) B5A2R (0x036E) B5A1R (0x036D) B5A0R (0x036C) B6A2R (0x037E) B6A1R (0x037D) B6A0R (0x037C) 7 0 15 8 23 16 PHYSICAL ADDRESS MASK BxA2R BxA1R BxA0R BREAKPOINT MASK REGISTERS B0M2R (0x030A) B0M1R (0x0309) B0M0R (0x0308) B1M2R (0x031A) B1M1R (0x0319) B1M0R (0x0318) B2M2R (0x032A) B2M1R (0x0329) B2M0R (0x0328) B3M2R (0x033A) B3M1R (0x0339) B3M0R (0x0338) B4M2R (0x034A) B4M1R (0x0349) B4M0R (0x0348) B5M2R (0x036A) B5M1R (0x0369) B5M0R (0x0368) B6M2R (0x037A) B6M1R (0x0379) B6M0R (0x0378) 7 0 15 8 23 16 PHYSICAL ADDRESS MASK BxM2R BxM1R BxM0R PORT x DATA REGISTERS PADR (0x0030) PDDR (0x0060) PBDR (0x0040) PEDR (0x0070) PCDR (0x0050) PHDR (0x0034) 0 7 READ/WRITE DATA TO PORT PORT x DATA DIRECTION REGISTERS PBDDR (0x0007) PEDDR (0x0077) PCDDR (0x0051) PHDDR (0x0037) PDDDR (0x0067) 0 7 0 = CORRESPONDING BIT IS INPUT 1 = CORRESPONDING BIT IS OUTPUT PORT x DRIVE CONTROL REGISTERS PCDCR (0x0054) PEDCR (0x0076) PDDCR (0x0066) PHDCR (0x0036) 0 7 0 = OUTPUT IS DRIVEN HIGH AND LOW 1 = OUTPUT IS OPEN-DRAIN PORT x FUNCTION REGISTERS PCFR (0x0055) PEFR (0x0075) PDFR (0x0065) PHFR (0x0035) 0 7 0 = BIT FUNCTIONS AS I/O 1 = BIT IS ALTERNATE OUTPUT PORT x DRIVE CONTROL REGISTERS PCDCR (0x0054) PEDCR (0x0076) PDDCR (0x0066) 0 7 0 = OUTPUT IS DRIVEN HIGH AND LOW 1 = OUTPUT IS OPEN DRAIN PORT x CONTROL REGISTER PDCR (0x0064) PECR(0x0074) 0 7 UPPER NIBBLE CLOCK IS PERCLK UPPER NIBBLE CLOCK IS TIMER A1 UPPER NIBBLE CLOCK IS TIMER B1 UPPER NIBBLE CLOCK IS TIMER B2 LOWER NIBBLE CLOCK IS PERCLK LOWER NIBBLE CLOCK IS TIMER A1 LOWER NIBBLE CLOCK IS TIMER B1 LOWER NIBBLE CLOCK IS TIMER B2 0 0 0 0 PORT x ALTERNATE LOW REGISTERS PCALR (0x0052) PEALR (0x0072) PDALR (0x0062) PHALR (0x0032) 0 7 SELECT BIT 3 ALTERNATE OUTPUT SELECT BIT 2 ALTERNATE OUTPUT SELECT BIT 1 ALTERNATE OUTPUT SELECT BIT 0 ALTERNATE OUTPUT PORT x ALTERNATE HIGH REGISTERS PCAHR (0x0053) PEAHR (0x0073) PDAHR (0x0063) 0 7 SELECT BIT 7 ALTERNATE OUTPUT SELECT BIT 6 ALTERNATE OUTPUT SELECT BIT 5 ALTERNATE OUTPUT SELECT BIT 4 ALTERNATE OUTPUT PORT x BIT y REGISTERS PDB0R (0x0068) PEB0R (0x0078) PDB1R (0x0069) PEB1R (0x0079) PDB2R (0x006A) PEB2R (0x007A) PDB3R (0x006B) PEB3R (0x007B) PDB4R (0x006C) PEB4R (0x007C) PDB5R (0x006D) PEB5R (0x007D) PDB6R (0x006E) PEB6R (0x007E) PDB7R (0x006F) PEB7R (0x007F) 0 7 A WRITE TO THE CORRESPONDING BIT CHANGES THAT BIT PARALLEL PORT C PIN PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 ALTO ALT1 ALT2 ALT3 TXA TXA TXB TXB TXC TXC TXD TXD I7 I6 I5 I4 I3 I2 I1 I0 PWM3 PWM2 PWM1 PWM0 TMRC3 TMRC2 TMRC1 TMRC0 SCLKC TXE RCLKE TCLKE SCLKD TXF RCLKF TCLKF ALTERNATE OUTPUT FUNCTIONS: PORTS C, D, E, F-G, H PARALLEL PORT D PIN PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 ALT0 ALT1 ALT2 ALT3 IA7 TXA IA6 TXB IA7 SCLKC IA6 SCLKD I7 I6 I5 I4 I3 I2 I1 I0 PWM3 PWM2 PWM1 PWM0 TMRC3 TMRC2 TMRC1 TMRC0 SCLKC TXE RCLKE TCLKE SCLKD TXF RCLKF TCLKF PARALLEL PORT E PIN ALT0 ALT1 ALT2 ALT3 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 SCLKG SDATG USBPWR SCLKG SDATG I7 I6 I5 I4 I3 I2 I1 I0 PWM3 PWM2 PWM1 PWM0 TMRC3 TMRC2 TMRC1 TMRC0 SCLKC TXE RCLKE TCLKE SCLKD TXF RCLKF TCLKF RXA RXB RXC RXD RXE RCLKE TCLKE RXF RCLKF TCLKF YES YES YES YES ALTERNATE INPUT FUNCTIONS: PORTS C, D, E, F-G, H SERIAL A–D SERIAL E–F INPUT CAPT PARALLEL PORT C PIN PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PARALLEL PORT D DREQ1 DREQ0 INT1 INT0 QRD2A QRD2B QRD1A RQD1B SERIAL A–D SERIAL E–F INPUT CAPT DMA & INT QUAD DEC RXA RXB RXC SCLKC RXD SCLKD YES YES YES YES PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PIN PARALLEL PORT E QRD2A QRD2B QRD1A QRD1B SERIAL A–D SERIAL E–F INPUT CAPT DMA & INT QUAD DEC RXA RXB RXC SCLKC RXD SCLKD PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 DREQ1 DREQ0 INT1 INT0 DREQ1 DREQ0 INT1 INT0 YES YES YES YES PIN RXE RCLKE TCLKE RXF RCLKF TCLKF RXE RCLKE TCLKE RXF RCLKF TCLKF YES YES YES YES YES YES YES YES I/O HANDSH PARALLEL PORT H PIN ALT0 ALT1 ALT2 ALT3 PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 I7 I6 I5 I4 I3 I2 I1 I0 PWM3 PWM2 PWM1 PWM0 TMRC3 TMRC2 TMRC1 TMRC0 SCLKC TXE RCLKE TCLKE SCLKD TXF ACLKF TCLKF DATA BUS 16-BIT DATA BUS PARALLEL PORT H PIN PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 DATA BUS 16-BIT DATA BUS PARALLEL PORT A* AUX I/O SLAVE I/O PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PARALLEL I/O SLAVE DATA EXT I/O DATA *SELECTION VIA SPCR *SELECTION VIA SPCR, SACR, SBCR PARALLEL PORT B* PIN PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 AUX I/O SLAVE SERIAL IA5 IA4 IA3 IA2 IA1 IA0 IA7 IA6 SCLKA SCLKB /ATTN /SCS SA1 SA0 /SRD /SWR PIN PARALLEL PORTS F-G PIN PF7/PG7 PF6/PG6 PF5/PG5 PF4/PG4 PF3/PG3 PF2/PG2 PF1/PG1 PF0/PG0 ALT0 ALT1 ALT2 ALT3 FIMA/B[7] FIMA/B[6] FIMA/B[5] FIMA/B[4] FIMA/B[3] FIMA/B[2] FIMA/B[1] FIMA/B[0] I7 I6 I5 I4 I3 I2 I1 I0 PWM3 PWM2 PWM1 PWM0 TMRC3 TMRC2 TMRC1 TMRC0 SCLKC TXE RCLKE TCLKE SCLKD TXF RCLKF TCLKF USBOVR USB PARALLEL PORTS F-G PIN PF7/PG7 PF6/PG6 PF5/PG5 PF4/PG4 PF3/PG3 PF2/PG2 PF1/PG1 PF0/PG0 INT FIM FIMA/B[7] FIMA/B[6] FIMA/B[5] FIMA/B[4] FIMA/B[3] FIMA/B[2] FIMA/B[1] FIMA/B[0] INT2-7 INT2-7 INT2-7 INT2-7 INT2-7 INT2-7 INT2-7 INT2-7 PORT x BIT y CONTROL REGISTER 0 = FAST OUTPUT SLEW 1 = SLOW OUTPUT SLEW 00 = 4mA OUTPUT DRIVE 01 = 8mA OUTPUT DRIVE 10 = 10mA OUTPUT DRIVE 11 = 14mA OUTPUT DRIVE 00 = NO PULLUP/DOWN 01 = 75KOHM PULLUP 10 = 75KOHM PULLDOWN 11 = 75KOHM KEEPER 7 0 PAyCR (0x04By) PByCR (0x04Cy) PCyCR (0x04Dy) PDyCR (0x04Ey) PEyCR (0x04Fy) PFyCR (0x04By+8) PGyCR (0x04Cy+8) PHyCR (0x04Dy+8) 0 0 0 Memory Management Unit MMU INSTRUCTION/DATA REGISTER MMIDR (0x0010) R/W 0 7 0 = A16, MSB INVERSION INDEPENDENT OF INSTRUCTION/DATA 1 = A16, MSB INVERSION FOR DATA ACCESS ONLY. (THIS ENABLES SEPARATE I AND D SPACE) 0 = USE 8-BIT INTERNAL I/O ADDRESSES 1 = USE 15-BIT INTERNAL I/O ADDRESSES RESERVED WRITE MUST = 0 0 = NORMAL /CS1 OPERATION 1 = FORCE /CS1 ALWAYS ACTIVE 0 = NORMAL 1 = INVERT MSB ON DATASEG ACCESS 0 = NORMAL 1 = INVERT A16 ON DATASEG ACCESS 0 = NORMAL 1 = INVERT BANK SEL ADDR MSB ON ROOT ACCESS 0 = NORMAL 1 = INVERT A16 ON ROOT ACCESS 0 RAM SEGMENT REGISTER RAMSR (0x0448) 0 7 00 = DISABLE RAM SEGMENT LIMIT CHECKING 01 = SELECT DATA MMU TRANSLATION IF PC[15:10] = RAMSR[7:2] 10 = SELECT DATA MMU TRANSLATION IF PC[15:11] = RAMSR[7:3] 11 = SELECT DATA MMU TRANSLATION IF PC[15:12] = RAMSR[7:4] COMPARE VALUE FOR RAM SEGMENT LIMIT CHECKING MEMORY TIMING CONTROL REGISTER MTCR (0x0019) 0 = NORMAL TIMING 1 = EXTENDED TIMING 0 = NO INTERNAL WRITE WAIT STATES 1 = ADD INTERNAL WRITE WAIT STATE 7 0 0 0 0 /OE1 /OE0 /WE1 /WE0 FFFF FFFFFF 64 KB 16 MB 0X000 00000 E000 Y000 X000 0000 0 3 4 7 XMEM STACK SEGMENT DATA SEGMENT ROOT LOGICAL ADDRESS MAP PHYSICAL ADDRESS MAP Y X SEGSIZE (0X13) R/W SEGMENT REGISTERS 0 23 24-BIT PHYSICAL ADDRESS 7 8 11 43 0 SEGMENT H/L 0 15 16-BIT LOGICAL ADDRESS DATA SEGMENT H/L REGISTERS (0x1E) (0x1F) 7 8 11 43 0 DATASEG H/L DATA SEGMENT REGISTER (0x12) 7 8 11 43 0 DATASEG 0000 STACK SEGMENT H/L REGISTERS (0x18) (0x1A) 7 8 11 43 0 STACKSEG H/L STACK SEGMENT REGISTER (0x11) 7 8 11 43 0 STACKSEG 0000 EXTENDED PROGRAM COUNTER REGISTER 7 8 11 43 0 LXPC 7 8 11 43 0 XPC 0000 WRITING TO DATASEG/STACKSEG PUTS 8-BIT VALUE INTO DATASEGL/STACKSEGL AND 0000 INTO DATASEGH/STACKSEGH. WRITING TO XPC PUTS VALUE INTO LOWER 8 BITS AND 0000 INTO UPPER 4 BITS OF LXPC X ≤Y ≤0xE ADVANCED CHIP SELECT CONTROL REGISTERS ACS0CR (0x0410) ACS1CR (0x0411) ACS2CR (0x0412) 0 7 000 = 0 EXTRA WS (RD, WR, 1st PAGE READ) 001 = 1 EXTRA WS (RD, WR, 1st PAGE READ) 010 = 2 EXTRA WS (RD, WR, 1st PAGE READ) 011 = 3 EXTRA WS (RD, WR, 1st PAGE READ) 100 = 4 EXTRA WS (RD, WR, 1st PAGE READ) 101 = 5 EXTRA WS (RD, WR, 1st PAGE READ) 110 = 6 EXTRA WS (RD, WR, 1st PAGE READ) 111 = 7 EXTRA WS (RD, WR, 1st PAGE READ) 00 = 0 EXTRA WS (LATER PAGE READS) 01 = 1 EXTRA WS (LATER PAGE READS) 10 = 2 EXTRA WS (LATER PAGE READS) 11 = 3 EXTRA WS (LATER PAGE READS) 0 = PAGE SIZE 16 BYTES 1 = PAGE SIZE 8 BYTES 0 = DISABLE BYTE WRITES ON 16-BIT BUS 1 = ENABLE BYTE WRITES ON 16-BIT BUS MEMORY ALTERNATE CONTROL REGISTER MACR (0x001D) 7 0 0 0 = NORMAL 8-BIT OPERATION FOR /CS3 1 = NORMAL 16-BIT OPERATION FOR /CS3 00 = NORMAL 8-BIT OPERATION FOR /CS2 01 = PAGE-MODE 8-BIT OPERATION FOR /CS2 10 = NORMAL 16-BIT OPERATION FOR /CS2 11 = PAGE-MODE 16-BIT OPERATION FOR /CS2 00 = NORMAL 8-BIT OPERATION FOR /CS1 01 = PAGE-MODE 8-BIT OPERATION FOR /CS1 10 = NORMAL 16-BIT OPERATION FOR /CS1 11 = PAGE-MODE 16-BIT OPERATION FOR /CS1 00 = NORMAL 8-BIT OPERATION FOR /CS0 01 = PAGE-MODE 8-BIT OPERATION FOR /CS0 10 = NORMAL 16-BIT OPERATION FOR /CS0 11 = PAGE-MODE 16-BIT OPERATION FOR /CS0 MMU EXPANDED CODE REGISTER MECR (0x0018) 0 7 0000 = NORMAL 0100 = USE MB0LCR FOR XPC ACCESS 0101 = USE MB1LCR FOR XPC ACCESS 0110 = USB MB2LCR FOR XPC ACCESS 0111 = USB MB3LCR FOR XPC ACCESS 1100 = USB MB0HCR FOR XPC ACCESS 1101 = USB MB1HCR FOR XPC ACCESS 1110 = USB MB2HCR FOR XPC ACCESS 1111 = USB MB3HCR FOR XPC ACCESS 000 = BANK SELECT ADDRESS IS A [19:18] 001 = BANK SELECT ADDRESS IS A [20:19] 010 = BANK SELECT ADDRESS IS A [21:20] 011 = BANK SELECT ADDRESS IS A [22:21] 100 = BANK SELECT ADDRESS IS A [23:22] 111 = BANK SELECT ADDRESS IS A [18:17] OTHERS RESERVED 0 0 = NO ADDITIONAL WAIT STATES 1 = ADD 8 WAIT STATES 00 = 4 WS (5 FOR WRITES) 01 = 2 WS (3 FOR WRITES) 10 = 1 WS (2 FOR WRITES) 11 = 0 WS (1 FOR WRITES) MBxCR MEMORY BANK CONTROL REGISTERS 0 7 00 = /OE0 AND /WE0 ARE ACTIVE 01 = /OE1 AND /WE1 ARE ACTIVE 10 = /OE0 IS ACTIVE (READ ONLY) 11 = /OE1 IS ACTIVE (READ ONLY) 00 = /CS0 IS ACTIVE 01 = /CS1 IS ACTIVE 10 = /CS2 IS ACTIVE 11 = /CS3 (INTERNAL MEM) IS ACTIVE 0 = PASS BANK SEL ADDR MSB 0 = INVERT BANK SEL ADDR MSB 0 = PASS BANK SEL ADDR LSB 0 = INVERT BANK SEL ADDR LSB BANK SELECT BITS 00x 000 001 01x 010 011 10x 100 101 11x 110 111 CONTROL REGISTER USED MB0CR MB0LCR MB0HCR MB1CR MB1LCR MB1HCR MB2CR MB2LCR MB2HCR MB3CR MB2LCR MB2HCR ADDRESS (0x0014) (0x0400) (0x0401) (0x0015) (0x0402) (0x0403) (0x0016) (0x0404) (0x0405) (0x0017) (0x0406) (0x0407) Serial Ports 0 = NORMAL CODING 1 = ENABLE RZI CODING (3/16 IrDA) 0 = NORMAL BREAK OPERATION 1 = FAST BREAK TERMINATION 0 = ASYNC CLK = 16 × DATA RATE 1 = ASYNC CLK = 8 × DATA RATE 0 = CHAR ASSY DURING BREAK 1 = NO CHAR ASSY DURING BREAK SERIAL PORT x EXTENDED REGISTER SAER (0x00C5) SBER (0x00D5) SCER (0x00E5) SDER (0x00F5) SEER (0x00CD) SFER (0x00DD) ASYNCH MODE (A,B,C,D,E,F) RESERVED 000 = DISABLE PARITY 100 = ENABLE EVEN PARITY 101 = ENABLE ODD PARITY 110 = ENABLE SPACE PARITY 111 = ENABLE MARK PARITY 7 0 0 0 = NORMAL CLOCKED SERIAL OPERATION 1 = TIMER-SYNCHED CLOCKED SERIAL OPERATION TERMINATE XMIT TERMINATE RECEIVE 0 = TIMED BY TIMER B1 1 = TIMED BY TIMER B2 00 = NORMAL CLK, INACTIVE HIGH, INT OR EXT CLK 01 = NORMAL CLK, INACTIVE LOW, INT CLK 10 = INVERTED CLK, INACTIVE LOW, INT OR EXT CLK 11 = INVERTED CLK, INACTIVE HIGH, INT CLK 0 = CLOCK INPUT FROM PARALLEL PORT D (SCER, SDER) 1 = CLOCK INPUT FROM PARALLEL PORT E (SCER, SDER) 0 = NORMAL DATA BIT ORDER 1 = REVERSE DATA BIT ORDER CLOCKED MODE (A,B,C,D) 7 0 0 = NORMAL DATA CODING 1 = ENABLE RZI ENCODING (¼-BIT IrDA) (W/NRZ & INT CLK) 0 = IDLE LINE COND. = FLAG 1 = IDLE LINE COND. = ONE 0 = XMIT FLAG ON UNDERRUN 1 = XMIT ABORT ON UNDERRUN 0 = SEPARATE EXTERNAL RCV/XMIT CLOCKS 1 = COMBINED EXTERNAL RCV/XMIT CLOCKS (XMIT PIN) 000 = NRZ DATA CODING 010 = NRZI DATA CODING 100 = BIPHASE LEVEL CODING (MANCHESTER) 110 = BIPHASE SPACE CODING (FM0) 111 = BIPHASE MARK CODING (FM1) HDLC MODE (E,F) 7 0 0 SERIAL PORT x STATUS REGISTER 7 0 7 0 0 = XMIT IDLE 1 = XMIT SENDING BYTE 0 = XMIT BUF EMPTY 1 = XMIT BUF FULL ASYNCH MODE (A,B,C,D,E,F) 0 0 0 = RCV DATA REG EMPTY 1 = BYTE IN RCV BUF, INTERRUPT CLEARED WHEN RCV BUF READ 0 = BYTE IN RCV BUF IS DATA 1 = BYTE IN RCV BUF IS ADDRESS 0 = RCV BUF NOT OVERRUN 1 = RCV BUF OVERRUN, CLEARED WHEN RCV BUF READ 0 = BYTE IN RCV BUF PARITY OK 1 = BYTE IN RCV BUF PARITY ERROR 0 = XMIT IDLE 1 = XMIT SENDING BYTE 0 = XMIT BUF EMPTY 1 = XMIT BUF FULL CLOCKED MODE (A,B,C,D) 0 0 0 = RCV DATA REG EMPTY 1 = BYTE IN RCV BUF, INTERRUPT CLEARED WHEN RCV BUF READ 0 = RCV BUF NOT OVERRUN 1 = RCV BUF OVERRUN, CLEARED WHEN RCV BUF READ 0 0 HDLC MODE (E,F) 7 0 00 = XMIT INT, BUF EMPTY 01 = XMIT FINISHED SENDING CRC 10 = XMIT FINISHED SENDING ABORT 11 = XMIT FINISHED SENDING CLOSING FLAG 0 = XMIT BUF EMPTY 1 = XMIT BUF FULL 0 = RCV DATA REG EMPTY 1 = BYTE IN RCV BUF, INTERRUPT CLEARED WHEN RCV BUF READ 00 = BYTE IN RCV BUF IS DATA 01 = BYTE IN RCV BUF FOLLOWED BY ABORT 10 = BYTE IN RCV BUF LAST IN FRAME, CRC VALID 11 = BYTE IN RCV BUF LAST IN FRAME, CRC ERROR 0 = RCV BUF NOT OVERRUN 1 = RCV BUF OVERRUN, CLEARED WHEN RCV BUF READ BITS [6,4] 0 = BYTE IN RCV BUT IS 8 BITS 1 = BYTE IN RCV BUF < 8 BITS SASR (0x00C3) SBSR (0x00D3) SCSR (0x00E3) SDSR (0x00F3) SESR (0x00CB) SFSR (0x00DB) **ASYNCH ONLY (REFER TO MANUAL FOR CLOCKED SERIAL & HDLC) *** TX INTERRUPTS ARE CLEARED WITH A WRITE TO THE SxSR SERIAL PORT x DATA REGISTER (SxDR) SADR (0x00C0) SBDR (0x00D0) SCDR (0x00E0) SDDR (0x00F0) SEDR (0x00C8) SFDR (0x00D8) RD = RETURNS CONTENTS OF RECEIVE BUFFER WR = LOADS XMIT BUFFER WITH DATA BYTE FOR TRANSMISSION 0 7 7 SERIAL PORT x ADDRESS REGISTER** SAAR (0x00C1) SBAR (0x00D1) SCAR (0x00E1) SDAR (0x00F1) SEAR (0x00C9) SFAR (0x00D9) RD = RETURNS CONTENTS OF RECEIVE BUFFER W R = LOADS XMIT BUFFER WITH ADDRESS BYTE FOR TRANSMISSION (9TH BIT=0) 0 SERIAL PORT x LONG STOP REGISTER (SxLR) SALR (0x00C2) SBLR (0x00D2) SCLR (0x00E2) SDLR (0x00F2) SELR (0x00CA) SFLR (0x00DA) RD = RETURNS CONTENTS OF RECEIVE BUFFER WR = LOADS XMIT BUFFER WITH ADDRESS BYTE FOR TRANSMISSION 0 7 SERIAL PORT x CONTROL REGISTER (SxCR) 00 = NO OPERATION. IGNORED IN ASYNCH MODE 01 = CLOCKED MODE: START BYTE RCV OPERATION 10 = CLOCKED MODE: START BYTE XMIT OPERATION 11 = CLOCKED MODE: START SIMULT. BYTE RCV & XMIT 00 = PARALLEL PORT C USED FOR INPUT 01 = PARALLEL PORT D USED FOR INPUT 10 = PARALLEL PORT E USED FOR INPUT 11 = DISBALE RCV INPUT 00 = ASYNCH MODE: 8 BITS PER CHAR. 01 = ASYNCH MODE: 7 BITS PER CHAR. 10 = CLOCKED MODE: EXTERNAL CLOCK (INPUT) 11 = CLOCKED MODE: INTERNAL CLOCK (OUTPUT) INTERRUPT 00 = DISABLED 01 = PRIORITY 1 10 = PRIORITY 2 11 = PRIORITY 3 7 0 SACR (0x00C4) SBCR (0x00D4) SCCR (0x00E4) SDCR (0x00F4) SECR (0x00CC) SFCR (0x00DC) 00 = NO OPERATION (IGNORED IN ASYNCH MODE) 01 = HDLC MODE: FORCE FLAG SEARCH MODE 10 = NO OPERATION 11 = HDLC MODE: TRANSMIT ABORT PATTERN 00 = PARALLEL PORT C USED FOR INPUT 01 = PARALLEL PORT D USED FOR INPUT 10 = PARALLEL PORT E USED FOR INPUT 11 = DISABLE RECEIVE INPUT 00 = ASYNCH MODE: 8 BITS PER CHAR. 01 = ASYNCH MODE: 7 BITS PER CHAR. 10 = HDLC MODE: EXTERNAL CLOCK (INPUT) 11 = HDLC MODE: INTERNAL CLOCK (OUTPUT) INTERRUPT 00 = DISABLED 01 = PRIORITY 1 10 = PRIORITY 2 11 = PRIORITY 3 7 0 SERIAL PORT x DIVIDER LOW REGISTER SADLR (0x00C6) SBDLR (0x00D6) SCDLR (0x00E6) SDDLR (0x00F6) SEDLR (0x00CE) SFDLR (0x00DE) 0 7 SERIAL PORT x DIVIDER HIGH REGISTER SADHR (0x00C7) SBDHR (0x00D7) SCDHR (0x00E7) SDDHR (0x00F7) SEDHR (0x00CF) SFDHR (0x00DF) 8 15 ENABLE DEDICATED SERIAL PORT DIVIDER 15-BIT DIVIDER VALUE 15-BIT DIVIDER VALUE Tamper-Protect RAM TAMPER -PROTECT BYTE X VRAM00 (0x0600) VRAM08 (0x0608) VRAM16 (0x0610) VRAM24 (0x0618) VRAM01 (0x0601) VRAM09 (0x0609) VRAM17 (0x0611) VRAM25 (0x0619) VRAM02 (0x0602) VRAM10 (0x060A) VRAM18 (0x0612) VRAM26 (0x061A) VRAM03 (0x0603) VRAM11 (0x060B) VRAM19 (0x0613) VRAM27 (0x061B) VRAM04 (0x0604) VRAM12 (0x060C) VRAM20 (0x0614) VRAM28 (0x061C) VRAM05 (0x0605) VRAM13 (0x060D) VRAM21 (0x0615) VRAM29 (0x061D) VRAM06 (0x0606) VRAM14 (0x060E) VRAM22 (0x0616) VRAM30 (0x061E) VRAM07 (0x0607) VRAM15 (0x060F) VRAM23 (0x0617) VRAM31 (0x061F) 7 0 ACCESS TAMPER-PROTECTED BYTE WATCHDOG TIMER CONTROL REGISTER WDTCR (0x0008) 0x5A = RESET WDT WITH 2-SECOND TIMEOUT 0x57 = RESET WDT WITH 1-SECOND TIMEOUT 0x59 = RESET WDT WITH 0.5-SECOND TIMEOUT 0x53 = RESET WDT WITH 0.25-SECOND TIMEOUT 0x5F = RESTART SECONDARY WATCHDOG TIMER OTHER = NO EFFECT READ = LSB OF CPU CLOCK CYCLE COUNTER 0x54 = DISABLE WDT (MUST BE PRECEDED BY A WRITE OF 0x51,0x52, OR 0x53) TO THIS REGISTER OTHER = NORMAL, WATCHDOG TIMER IS CLOCKED BY 32 kHz CLOCK READ = MSB OF CPU CLOCK CYCLE COUNTER WATCHDOG TIMER TEST REGISTER WDTTR (0x0009) 7 0 7 0 SECONDARY WATCHDOG TIMER TIME CONSTANT DISABLED BY 0x5A - 0x52 - 0x44 TO THIS REGISTER SECONDARY WATCHDOG TIMER SWDTR (0x000C) 7 0 Watchdog Timer External Interrupts EXTERNAL INTERRUPT HOLD TIME MUST BE AT LEAST 3 PERIPHERAL CLOCK CYCLES 7 0 00 = INT0 DISABLED 01 = INT0 PRIORITY 1 10 = INT0 PRIORITY 2 11 = INT0 PRIORITY 3 00 = DISABLE PD0 INTERRUPT 01 = ENABLE PD0 FALLING EDGE 10 = ENABLE PD0 RISING EDGE 11 = ENABLE PD0 BOTH EDGES 00 = DISABLE PE4 INTERRUPT 01 = ENABLE PE4 FALLING EDGE 10 = ENABLE PE4 RISING EDGE 11 = ENABLE PE4 BOTH EDGES 00 = DISABLE PE0 INTERRUPT 01 = ENABLE PE0 FALLING EDGE 10 = ENABLE PE0 RISING EDGE 11 = ENABLE PE0 BOTH EDGES INTERRUPT 0 CONTROL REGISTER I0CR (0x0098) INTERRUPT 1 CONTROL REGISTER I1CR (0x0099) 7 0 00 = INT1 DISABLED 01 = INT1 PRIORITY 1 10 = INT1 PRIORITY 2 11 = INT1 PRIORITY 3 00 = DISABLE PD1 INTERRUPT 01 = ENABLE PD1 FALLING EDGE 10 = ENABLE PD1 RISING EDGE 11 = ENABLE PD1 BOTH EDGES 00 = DISABLE PE5 INTERRUPT 01 = ENABLE PE5 FALLING EDGE 10 = ENABLE PE5 RISING EDGE 11 = ENABLE PE5 BOTH EDGES 00 = DISABLE PE1 INTERRUPT 01 = ENABLE PE1 FALLING EDGE 10 = ENABLE PE1 RISING EDGE 11 = ENABLE PE1 BOTH EDGES INTERRUPT 2-7 CONTROL REGISTER I2CR (0x009A) I3CR (0x009B) I4CR (0x009C) I5CR (0x009D) I6CR (0x009E) I7CR (0x009F) 0 7 0 = INT FROM PORT F 1 = INT FROM PORT G INTERRUPT PIN ON PORT 00 = INTERRUPT DISABLED 01 = INTERRUPT FALLING EDGE 10 = INTERRUPT RISING EDGE 11 = INTERRUPT BOTH EDGES 00 = INTERRUPT DISABLED xx = INTERRUPT PRIORITY Stack Limit Protection STACK LIMIT CONTROL REGISTER STKCR (0x0444) 0 7 0 = DISABLE STACK LIMIT CHECKING 1 = ENABLE STACK LIMIT CHECKING 0 0 0 0 0 0 0 STACK LOW LIMIT REGISTER STKLLR (0x445) 0 7 SET LOWER LIMIT FOR STACK LIMIT CHECKING IF STACK ACCESS ATTEMPTED BELOW {STKLLR, 0x10} INTERRUPT OCCURS STACK HIGH LIMIT REGISTER STKHLR (0x0446) 0 7 SET UPPER LIMIT FOR STACK LIMIT CHECKING IF STACK ACCESS ATTEMPTED ABOVE {STKHLR, 0x00EF} INTERRUPT OCCURS Input Capture INPUT CAPTURE CONTROL REGISTER ICCR (0x0057) 7 0 0 0 0 0 00 = INPUT CAPTURE INTERRUPTS DISABLED 01 = PRIORITY 1 INTERRUPT 10 = PRIORITY 2 INTERRUPT 11 = PRIORITY 3 INTERRUPT 0 = IC2 CAPTURE OPERATION 1 = IC2 COUNTER OPERATION 0 = IC1 CAPTURE OPERATION 1 = IC1 COUNTER OPERATION RESERVED MUST = 0 7 0 INPUT CAPTURE TRIGGER x REGISTERS ICT1R (0x0058) — ICT2R (0x005C) 00 = COUNTER DISABLED 01 = COUNT RUNS FROM START TO STOP 10 = COUNT RUNS CONTINUOUSLY 11 = COUNT RUNS UNTIL STOP 00 = DISABLE COUNTER LATCH 01 = LATCH COUNTER ON STOP 10 = LATCH COUNTER ON START 11 = LATCH COUNTER ON START OR STOP 00 = IGNORE START INPUT 01 = START AT START INPUT RISING EDGE 10 = START AT START INPUT FALLING EDGE 11 = START AT START INPUT EITHER EDGE 00 = IGNORE STOP INPUT 01 = STOP AT STOP INPUT RISING EDGE 10 = STOP AT STOP INPUT FALLING EDGE 11 = STOP AT STOP INPUT EITHER EDGE INPUT CAPTURE SOURCE x REGISTERS ICS1R (0x0059) — ICS2R (0x005D) 7 0 00 = PORT C 01 = PORT D 10 = PORT E 11 = RESERVED AS START CONDITIONS INPUT 00 = BIT 1 01 = BIT 3 10 = BIT 5 11 = BIT 7 00 = PORT C 01 = PORT D 10 = PORT E 11 = RESERVED 00 = BIT 1 01 = BIT 3 10 = BIT 5 11 = BIT 7 AS STOP CONDITIONS INPUT USE USE INPUT CAPTURE COUNTER REGISTER MSB — ICM1R (0x005B) ICM2R (0x005F) READ MSB (RE-OPENS LATCH) 7 0 LSB — ICL1R (0x005A) ICL2R (0x005E) READ LSB (LATCHES MSB) 7 0 0 = IC1 START CONDITION NOT OCCURRED 1 = IC1 START CONDITION OCCURRED 0 = IC2 START CONDITION NOT OCCURRED 1 = IC2 START CONDITION OCURRED 0 = IC2 START INT. DISABLED 1 = IC2 START INT. ENABLED 7 0 0 = IC2 STOP CONDITION NOT OCCURRED 1 = IC2 STOP CONDITION OCCURRED 0 = IC1 STOP CONDITION NOT OCCURRED 1 = IC1 STOP CONDITION OCCURRED 0 = IC2 NOT ROLLED OVER 1 = IC2 ROLLED OVER 0 = IC1 NOT ROLLED OVER 1 = IC1 ROLLED OVER 0 = IC1 START INT. DISABLED 1 = IC1 START INT. ENABLED 0 = IC1 STOP INT. DISABLED 1 = IC1 STOP INT. ENABLED 0 = IC2 STOP INT. DISABLED 1 = IC2 STOP INT. ENABLED RESET IC2 COUNTER & ROLLOVER LATCH RESET IC1 COUNTER & ROLLOVER LATCH 0 0 INPUT CAPTURE CONTROL/STATUS REGISTER ICCSR (0x0056) CLEARED WHEN READ RESERVED MUST = 0 READ WRITE (USES TIMER A8) Analog NOT ALL REGISTERS DISPLAYED; SEE PROCESSOR MANUAL FOR MORE DETAILS. ADC COMMAND/STATUS REGISTER ADCCSR (0x0543) 7 0 0 1 = START CONVERSION 01 = INTERNAL REFERENCE 10 = EXTERNAL REFERENCE CHANNEL FOR CONVERSION (0-7) 0 ADC LSB REGISTER ADCLR (0x0540) 7 0 4 LSB OF CURRENT CHANNEL 0 = NO CONVERSION RUNNING 1 = CONVERSION IN PROGRESS 0 0 0 = CONVERSION NOT COMPLETE 1 = CONVERSION COMPLETE, DATA READY ADC MSB REGISTER ADCMR (0x0541) 7 0 8 MSB OF CURRENT CHANNEL ADC CONTROL REGISTER ADCCR (0x0544) 0 = USE PERIPHERAL CLOCK 1 = USE PD4 AS CLOCK INPUT 000 = DIVIDE CLOCK BY 2 001 = DIVIDE CLOCK BY 4 010 = DIVIDE CLOCK BY 8 011 = DIVIDE CLOCK BY 16 100 = DIVIDE CLOCK BY 32 101 = DIVIDE CLOCK BY 64 110 = DIVIDE CLOCK BY 128 111 = DIVIDE CLOCK BY 256 0 = ADC POWERED DOWN 1 = ADC ACTIVE 7 0 0 00 = NO ADC INTERRUPT XX = INTERRUPT PRIORITY Write Protect 7 0 15 8 WRITE PROTECT CONTROL REGISTER WPCR (0x0440) 7 0 0 0 0 0 0 0 0 0 0 0 0 = ENABLE WRITE PROTECTION IN USER MODE ONLY 1 = ENABLE WRITE PROTECTION IN ALL MODES 7 0 WRITE PROTECT LOW/HIGH REGISTERS WP0R (0x0460) – WP31R (0x047F) 0 = DISABLE WRITE PROTECT FOR 64 KB BLOCK 1 = ENABLE WRITE PROTECT FOR 64 KB BLOCK WRITE PROTECT SEGMENT HIGH/LOW REGISTERS WPSAHR (0x0482) WPSALR (0x0481) WPSBHR (0x0486) WPSBLR (0x0485) 0 = DISABLE WRITE PROTECT FOR 4 KB BLOCK 1 = ENABLE WRITE PROTECT FOR 4 KB BLOCK WRITE PROTECT SEGMENT REGISTERS WPSAR (0x0480) WPSBR (0x0484) WHEN THESE MATCH PHYSICAL ADDRESS [23:16], SUBDIVIDE WRITE PROTECT FOR THAT 64 KB BLOCK INTO 4 KB BLOCKS 7 0 WPSxHR WPSxLR Direct Memory Access DMA TIMED REQUEST DIVIDER LOW REGISTER DTRDLR (0x0116) LSB OF LIMIT VALUE FOR TIMER 0 7 DMA TIMED REQUEST DIVIDER HIGH REGISTER DTRDHR (0x0117) MSB OF LIMIT VALUE FOR TIMER 8 15 DMA MASTER AUTO-LOAD REGISTER DMALLR (0x0110) DMALMR (0x0111) 0 = NO EFFECT 1 = AUTO-LOAD CHANNEL 0 7 00 = REQUESTS DISABLED 01 = REQUEST ENABLED FROM PD2 10 = REQUEST ENABLED FROM PE2 11 = REQUEST ENABLED FROM PE6 REQUEST 0 TO THIS DMA CHANNEL 00 = FALLING EDGE TRIGGERED (1 BYTE) 01 = RISING EDGE TRIGGERED (1 BYTE) 10 = ACTIVE LOW 11 = ACTIVE HIGH DMA MASTER REQUEST 0 CONTROL REGISTER DMR0CR (0x0106) 7 0 00 = REQUESTS DISABLED 01 = REQUEST ENABLED FROM PD3 10 = REQUEST ENABLED FROM PE3 11 = REQUEST ENABLED FROM PE7 00 = FALLING EDGE TRIGGERED (1 BYTE) 01 = RISING EDGE TRIGGERED (1 BYTE) 10 = ACTIVE LOW 11 = ACTIVE HIGH REQUEST 1 TO THIS DMA CHANNEL DMA MASTER REQUEST 1 CONTROL REGISTER DMR1CR (0X0107) 7 0 DMA y TERMINATION BYTE REGISTER D0TBR-D7TBR (0x01y8) D8TBR-D15TBR (0x09y8) MATCH VALUE 0 7 DMA y TERMINATION MASK REGISTER D0TMR-D7TMR (0x01y9) D8TMR-D15TMR (0x09y9) TERMINATION BYTE MASK 0 7 DMA MASTER CONTROL/STATUS REGISTER DMCSLR (0x0100) DMCSMR (0x0101) WR 0 = NO EFFECT WR 1 = START/RESTART CHANNEL RD 0 = CHANNEL DISABLED RD 1 = CHANNEL ENABLED 0 7 DMA y BUFFER COMPLETE REGISTER D0BCR-D7BCR (0x01y3) D8BCR-D15BC (0x09y3) WR = LOAD COUNTER RD = READ COUNTER 0 7 DMA y BUFFER UNUSED [7:0] REGISTER D0BU0R-D7BU0R (0x01yA) D8BU0R-D15BU0R (0x09yA) DMA x BUFFER UNUSED [15:8] REGISTER D0BU1R-D7BU1R (0x01yB) D8BU1R-D15BU1R (0x09yB) STORES BITS OF BUFFER UNUSED LENGTH VALUE 0 7 000 = MAX 1 BYTE BURST 001 = MAX 2 BYTE BURST 010 = MAX 3 BYTE BURST 011 = MAX 4 BYTE BURST 100 = MAX 8 BYTE BURST 101 = MAX 16 BYTE BURST 110 = MAX 32 BYTE BURST 111 = MAX 64 BYTE BURST 000 = MIN 12 CLOCKS BETWEEN BURSTS 001 = MIN 16 CLOCKS BETWEEN BURSTS 010 = MIN 24 CLOCKS BETWEEN BURSTS 011 = MIN 32 CLOCKS BETWEEN BURSTS 100 = MIN 64 CLOCKS BETWEEN BURSTS 101 = MIN 128 CLOCKS BETWEEN BURSTS 110 = MIN 256 CLOCKS BETWEEN BURSTS 111 = MIN 512 CLOCKS BETWEEN BURSTS 0x = FIXED DMA CHANNEL PRIORITY 10 = ROTATE PRIORITY AFTER EVERY BYTE 11 = ROTATE PRIORITY AFTER EVERY REQUEST DMA MASTER TIMING CONTROL REGISTER DMTCR (0x0105) 7 0 0 = CONTINUE TO NEXT BUFFER DESCRIPTOR 1 = FINAL BUFFER DESCRIPTOR 0 = USE SEQUENTIAL ADDRESS 1 = USE LINK ADDRESS FIELD 0 = NORMAL 1 = SPECIAL LAST BYTE 00 = DESTINATION ADDRESS IS FIXED INTERNAL I/O ADDR 01 = DESTINATION ADDRESS IS FIXED EXTERNAL I/O ADDR 10 = DESTINATION ADDRESS IS MEMORY ADDR, AUTO DECREMENT 11 = DESTINATION ADDRESS IS MEMORY ADDR, AUTO INCREMENT 00 = SOURCE ADDRESS IS FIXED INTERNAL I/O ADDRESS 01 = SOURCE ADDRESS IS FIXED EXTERNAL I/O ADDRESS 10 = SOURCE ADDRESS IS MEMORY ADDR, AUTO-DECREMENT 11 = SOURCE ADDRESS IS MEMORY ADDR, AUTO-INCREMENT 0 = NO INTERRUPT ON COMPLETION 1 = INTERRUPT ON COMPLETION DMA x CONTROL REGISTER D0CR (0x0181) DMA DESCRIPTOR REGISTER ADD MULTIPLE OF 0x10 FOR CHANNELS 1 THRU 7; ADD 0x800 FOR CHANNELS 8 THRU 15 D0CR (0x0181) D0L0R (0x0182) D0SA0R (0x0184) D0DA0R (0x0188) D0LA0R (0x0180) 7 0 DMA SOURCE ADDRESS DMA DEST ADDRESS DMA LINK ADDRESS DMA LENGTH 23 16 15 8 7 0 (0x0184) (0x0185) (0x0186) 23 16 15 8 (0x0189) (0x018A) 23 16 15 8 (0x018D) (0x018E) 15 8 (0x183) 7 0 (0x182) 7 0 (0x181) SEE BIT SETTINGS BELOW 7 0 (0x188) 7 0 (0x18C) DMA MASTER CONTROL REGISTER DMCR (0x0104) 00 = DISABLE INTERRUPT 01 = PRIORITY 1 INTERRUPT 10 = PRIORITY 2 INTERRUPT 11 = PRIORITY 3 INTERRUPT 00 = PRIORITY 0 TRANSFER 01 = PRIORITY 1 TRANSFER 10 = PRIORITY 2 TRANSFER 11 = PRIORITY 3 TRANSFER 0 7 0 0 0 0 0 = TIMED REQUEST DISABLED 1 = TIMED REQUEST ENABLED 00 = 1 BYTE PER REQUEST 01 = (RESERVED) 10 = TRANSFER UNTIL BUFFER DESCRIPTOR IS COMPLETE 11 = (RESERVED) REQUEST TO THIS DMA CHANNEL 7 0 0 DMA TIMED REQUEST CONTROL REGISTER DTRCR (0x0115) 0 = NO EFFECT 1 = HALT CHANNEL 0 7 DMA MASTER HALT REGISTER DMHLR (0x0102) DMHMR (0x0121) DMA SPECIAL CONTROL REGISTER D0SCR (0x0180) D1SCR (0x0190) D2SCR (0x01A0) D3SCR (0x01B0) D4SCR (0x01C0) D5SCR (0x01D0) D6SCR (0x01E0) D7SCR (0x01F0) 7 0 0 0 = NORMAL DEST ADDRESS 1 = FIXED DEST ADDRESS 0 = AUTO-CONNECT DEST DMA REQUEST 1 = DISCONNECT DEST DMA REQUEST 0 = NORMAL SOURCE ADDRESS 1 = FIXED SOURCE ADDRESS 0 = AUTO-CONNECT SOURCE DMA REQUEST 1 = DISCONNECT SOURCE DMA REQUEST 10 = ENABLE DMA FOR USB RX 11 = ENABLE DMA FOR USB TX 0X = NORMAL DMA OPERATION 0 = AUTOMATIC SELECTION OF CYCLE-STEAL MODE 1 = DISABLE CYCLE-STEAL MODE 0x = FIXED DMA CHANNEL PRIORITY 10 = ROTATE PRIORITY AFTER EVERY BYTE 11 = ROTATE PRIORITY AFTER EVERY REQUEST 000 = MAX 1 BYTE BURST 001 = MAX 2 BYTE BURST 010 = MAX 3 BYTE BURST 011 = MAX 4 BYTE BURST 100 = MAX 8 BYTE BURST 101 = MAX 16 BYTE BURST 110 = MAX 32 BYTE BURST 111 = MAX 64 BYTE BURST DMA CYCLE-STEAL TIMING CONTROL REGISTER DCSTCR (0x0125) 7 0 0 0 0 NOT ALL REGISTERS DISPLAYED; SEE PROCESSOR MANUAL FOR MORE DETAILS. Network Ports NOT ALL REGISTERS DISPLAYED; SEE PROCESSOR MANUAL FOR MORE DETAILS. NETWORK PORT C CPU WAIT REGISTER NCCWR (0x0431) ONES COMPLIMENT OF WIFI CPU WAIT STATES (0-31) 0 7 0 0 NETWORK PORT C DMA WAIT REGISTER NCDWR (0x0432) ONES COMPLIMENT OF WIFI DMA WAIT STATES (0-31) 0 7 0 0 NETWORK PORT D WAIT REGISTER NDDWR (0x0433) ONES COMPLIMENT OF USB WAIT STATES (0-31) 0 7 0 0 USB WRAPPER REGISTER USBWR (0x1060) 7 0 0 0 0 0 = DISABLE USB OVERCURRENT SIGNAL 1 = ENABLE USB OVERCURRENT SIGNAL ON PE3 0 = DISABLE D- PULLDOWN 1 = DISABLE D- PULLDOWN 0 0 = DISABLE D+ PULLDOWN 1 = ENABLE D+ PULLDOWN 0 ENABLE NETWORK PORT REGISTER ENPR (0x0430) 7 0 0 00 = WIFI INTERRUPT DISABLED XX = WIFI INTERRUPT PRIORITY 00 = USB INTERRUPT DISABLED XX = USB INTERRUPT PRIORITY 0 = DISABLE USB HOST 1 = ENABLE USB HOST 0 = DISABLE ETHERNET 1 = ENABLE ETHERNET 0 = DISABLE WIFI 1 = ENABLE WIFI A (1P): 91001614-88

RABBIT 6000 MICROPROCESSOR · 2018. 2. 12. · 010 = crc-16 ibm (usb) 011 = crc-16 ccitt 100 = crc-15 (can) 0 0 = read data not inverted 1 = read data inverted 0 = initial value all

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Page 1: RABBIT 6000 MICROPROCESSOR · 2018. 2. 12. · 010 = crc-16 ibm (usb) 011 = crc-16 ccitt 100 = crc-15 (can) 0 0 = read data not inverted 1 = read data inverted 0 = initial value all

RABBIT®

6000 MICROPROCESSORRABBIT®

6000 MICROPROCESSOR Read/Write Write Only Read Only

Read (Special Behavior on Write Operation)

REGISTER LEGEND

NOTE: ZERO MUST BE WRITTEN TO ALL UNUSED BITS

Processor Control

GLOBAL CPU CONFIGURATION REGISTER GCPU (0x002E)GLOBAL REVISION REGISTER GREV (0x002F)

0 = FETCH PER SMODE1 = IGNORE SMODE

RD ONLY

SMODE

CPU VERSION (GCPU)REVISION (GREV)

7

0

PROCESSOR MODE SELECTBOOTSTRAP OPERATION

BOOTSTRAP DISABLED. NORMAL PROCESSOR OPERATION(CODE FETCHED FROM MEMORY)

SLAVE PORT. SPD0R USED FOR BOOTSTRAP OPERATION

SYNCHRONOUS SERIAL. CLOCKED SERIAL PORT A ON PARALLEL PORT C USED FOR BOOTSTRAP OPER. MAX EXTERNAL CLOCK RATE = PCLK/6

SMODE1 SMODE0

0 0

0 1

1 0

1 1 ASYNCHRONOUS SERIAL. ASYNCH SERIAL PORT A ON PARALLEL PORT C USED FOR BOOTSTRAP OPER. REQUIRED BAUD RATE = 2400

REVISION IDENTIFIERS CPU Revision

RABBIT 6000 BGA292 0x04 0x00

GLOBAL POWER SAVE CONTROL REGISTERGPSCR (0x000D)

000 = SELF-TIMED CS DISABLE001 = 230 ns010 = 170 ns011 = 110 ns100 = 290 ns101 = 230 ns110 = 170 ns111 = 110 ns

0 = NORMAL CS FOR READS1 = SHORT CS TIMING FOR READS#

0 = NORMAL CS FOR WRITES1 = SHORT CS TIMING FOR WRITES#

7

0 RESERVED

SELF-TIMED CSREAD ONLY

SELF-TIMED CSREAD AND WRITE

CPU & PCLK

000 = 32 kHz00101X100 = 16.3848 kHz101 = 8.192 kHz110 = 4.096 kHz111 = 2.048 kHz

#(NOT AVAILABLE AT FULL SPEED)

GLOBAL OUTPUT CONTROL REGISTER GOCR (0x000E)

/BUFEN OUTPUT00 = LOW FOR EXTERNAL I/O CYCLE01 = LOW FOR DATA MEMORY ACCESS10 = LOW11 = HIGH

STATUS OUTPUT00 = LOW DURING FIRST OPCODE FETCH01 = LOW DURING INTERRUPT ACKNOWLEDGE10 = LOW11 = HIGH

/WDTOUT OUTPUT00 = LOW DURING WD TIMEOUT01 = TEST MODE (INTERNAL USE)10 = LOW PULSE (1–2 CYCLES @ 32 kHz)

CLK OUTPUT00 = CLK = PCLK01 = CLK = PCLK/210 = CLK = LOW11 = CLK = HIGH

7

0

0

GLOBAL CLOCK MODULATOR REGISTERS GCM0R (0x000A)

00 = 1 ns DITHER01 = 0.5 ns DITHER10 = 2 ns DITHER

RESERVEDMUST = 0

7 0

0

SYSTEMPLL LOOPDIVIDER

GCM1R (0x000B)

0 = SPREADER OFF1 = SPREADER ON

RESERVEDMUST = 0

7 0

00 0

SYSTEM PLLPREDIVIDER

GLOBAL CLOCK DOUBLE REGISTERGCDR (0x000F)

00000 = CLOCK DOUBLE DISABLED00001 6 ns 00010 7 ns00011 8 ns00100 9 ns00101 10 ns00110 11 ns00111 12 ns01000 13 ns01001 14 ns01010 15 ns01011 16 ns01100 17 ns01101 18 ns01110 19 ns01111 20 ns10001 3 ns10010 4 ns10011 5 ns

RESERVED MUST = 0

7

0

0

0

CLOCK DOUBLE ENABLED, TYPICAL CLOCK LOW TIME

0 = DISABLE SYSTEM PLL1 = ENABLE SYSTEM PLL

00 PERIODIC INTERRUPT = DISABLE01 PERIODIC INTERRUPT = PRIORITY 1 10 PERIODIC INTERRUPT = PRIORITY 211 PERIODIC INTERRUPT = PRIORITY 3

000 CPU = OSC/8; PCLK = OSC/8001 CPU = OSC/8; PCLK = OSC010 CPU = OSC; PCLK = OSC011 CPU = OSC/2; PCLK = OSC/2100 CPU = 32 kHz; PCLK = 32 kHz;

MAIN OSC ON101 CPU = 32 kHz; PCLK = 32 kHz;

MAIN OSC OFF110 CPU = OSC/4; PCLK = OSC/4111 CPU = OSC/6; PCLK = OSC/6

000 = NO TIMEOUT010 = WATCHDOG TIMEOUT110 = HARDWARE RESET111 = POWER-ON RESET

PERIODIC INTERRUPT = 32 kHz/16 (488 ms)PCLK = PERIPHERAL CLOCKCPU = CPU CLOCKOSC = DOUBLED OR NON-DOUBLED CLOCK

PERIODIC INTERRUPT

OSC

7

0

GLOBAL CONTROL/STATUS REGISTER GCSR (0x0000)

MASTER SYSTEM CONFIGURATION REGISTERMSCR (0x0434)

7

0

0 = CPU CLOCK FROM MAIN OSC1 = CPU CLOCK FROM SYSTEM PLL

00 = ETH PHY CLOCK FROM MAIN OSC1 = ETH PHY CLOCK FROM EXTERNAL PHY OSC

1 = RESET ETH PHY

00 = FIM B DISABLED01 = FIM B CLOCK FROM CPU CLOCK11 = FIM B CLOCK FROM MAIN PLL

00 = FIM A DISABLED01 = FIM A CLOCK FROM CPU CLOCK11 = FIM A CLOCK FROM MAIN PLL

MASTER SYSTEM STATUS REGISTERMSSR (0x0435)

7

0

0

0

0

0

0 = WIFI DIRECT CLOCK1 = WIFI EXTERNAL XTAL0 = USB DIRECT CLOCK1 = USB EXTERNAL XTAL

0 = RD: WIFI PLL NOT READY1 = RD: WIFI PLL READY0 = RD: SYSTEM PLL NOT READY1 = RD: SYSTEM PLL READY

7

0

0

DATA BUS PIN CONTROL REGISTERDDPCR (0x04A1)

00 = 4mA OUTPUT DRIVE01 = 8mA OUTPUT DRIVE10 = 10mA OUTPUT DRIVE11 = 14mA OUTPUT DRIVE

0 = FAST OUTPUT SLEW1 = SLOW OUTPUT SLEW

0

0

0

00 = NO PULLUP/DOWN01 = 75KOHM PULLUP10 = 75KOHM PULLDOWN11 = 75KOHM KEEPER

7

0

0

PIN CONTROL REGISTERSADPCR (0x04A0)CPCR (0x04A2)IOPCR (0x04A3)

00 = 4mA OUTPUT DRIVE01 = 8mA OUTPUT DRIVE10 = 10mA OUTPUT DRIVE11 = 14mA OUTPUT DRIVE

0 = FAST OUTPUT SLEW1 = SLOW OUTPUT SLEW

0

0

0

0

0

Parallel Ports

Error Check and CorrectECC CONTROL REGISTERECCR (0x05C4)

0 = DISABLE/INITIALIZE ECC/CRC1 = ENABLE ECC/CRC7

0

0

000 = ECC, 256-65K BYTE BLOCKS001 = CRC-32 (IEEE 802)010 = CRC-16 IBM (USB)011 = CRC-16 CCITT100 = CRC-15 (CAN)

0

0 = READ DATA NOT INVERTED1 = READ DATA INVERTED0 = INITIAL VALUE ALL ZEROS1 = INITIAL VALUE ALL ONES

ECC DATA x REGISTERECD0R (0x05C0) ECD1R (0x05C1)ECD2R (0x05C2) ECD3R (0x05C3)

07

RD: LP/CRC BITS 31:0 WR: DATA BYTE FOR ECC/CRC

ECC CP READ REGISTERECPR (0x05C5)

07

RD: {00, CP VALUE}WR: {00, CP SET VALUE}

ECC CP READ SHIFTED REGISTERECPSR (0x05C6)

07

RD: {CP VALUE, 00}WR: {00, CP SET VALUE}

ECC WRITE x REGISTERECW0R (0x05C7) ECW1R (0x05C8)ECW2R (0x05C9) ECW3R (0x05A)

07

RD: LP/CRC BITS 0:31 (REVERSE BIT ORDER) WR: DATA BYTE FOR ECC/CRC

ECC COUNT x REGISTERECC0R (0x05C7)ECC1R (0x05C8)

07

RD: ECC COUNTER BITS 15:0 WR: SET ECC COUNTER BITS 15:0

www.digi.com 91001614A1/410

(USES TIMER A9)Pulse Width ModulationPWM 0 REGISTERSPWM0R (0x0089) PWL0R (0x0088)7 0 7 0

10-BIT PWM COUNT

00 = NORMAL PWM OPERATION01 = SUPPRESS PWM OUTPUT

7/8 ITERATIONS10 = SUPPRESS PWM OUTPUT

3/4 ITERATIONS11 = SUPPRESS PWM OUTPUT

1/2 ITERATIONS

00 = INTERRUPTS DISABLED01 = PRIORITY 1 INTERRUPT10 = PRIORITY 2 INTERRUPT11 = PRIORITY 3 INTERRUPT

0 = SINGLE-PULSE PWM1 = SPREAD PWM

0

PWM 2 AND 3 REGISTERSPWM2R (0x008D) PWL2R (0x008C) PWM3R (0x008F) PWL3R (0x008E)7 0 7 0

10-BIT PWM COUNT 00 = NORMAL PWM 1 OPERATION01 = SUPPRESS PWM 1 OUTPUT

7/8 ITERATIONS10 = SUPPRESS PWM 1 OUTPUT 3/4 ITERATIONS11 = SUPPRESS PWM 1 OUTPUT 1/2 ITERATIONS

0 = SINGLE-PULSE PWM1 = SPREAD PWM

0 0 0

PWM BLOCK ACCESS REGISTERPWBAR (0x00E8)

07

ACCESS PWM REGISTER POINTED TO BY PWBPR

PWM BLOCK POINTER REGISTERPWBPR (0x00E9)

07

LSBs OF PWM REGISTER

0001 1

PWM 1 REGISTERSPWM1R (0x008B) PWL1R (0x008A)7 0 7 0

10-BIT PWM

COUNT

00 = NORMAL PWM OPERATION01 = SUPPRESS PWM OUTPUT

7/8 ITERATIONS10 = SUPPRESS PWM OUTPUT

3/4 ITERATIONS11 = SUPPRESS PWM OUTPUT

1/2 ITERATIONS

00 = NORMAL PWM INTERRUPT01 = SUPPRESS PWM INT 7/8 ITERATIONS10 = SUPPRESS PWM INT 3/4 ITERATIONS11 = SUPPRESS PWM INT 1/2 ITERATIONS

0 = SINGLE-PULSE PWM1 = SPREAD PWM

0

Quadrature Decoder(USES TIMER A10)

QUAD DECODE CONTROL/STATUS REGISTERQDCSR (0x0090)

1 = QD2 = INCREMENTED FROM MAX 0x007

0

1 = QD2 = DECREMENTED FROM 0x00 MAX

RESET QD2, NO INTERRUPT

1 = QD1 = INCREMENTED FROM MAX 0x00

1= QD1 = DECREMENTED FROM 0x00 MAX

RESET QD1, NO INTERRUPT

0

0

QUAD DECODE CONTROL REGISTERQDCR (0x0091)

0 = 8-BIT COUNTER1 = 10-BIT COUNTER

00 = QD2 INPUT DISABLED01 = QD2 INPUT FROM PD3 & PD210 = QD2 INPUT FROM PE3 & PE211 = QD2 INPUT FROM PE7 & PE6

7

0

0

00 = QD INTERRUPT DISABLED01 = PRIORITY 1 INTERRUPT10 = PRIORITY 2 INTERRUPT11 = PRIORITY 3 INTERRUPT

00 = QD1 INPUT DISABLED01 = QD1 INPUT FROM PD1 & PD010 = QD1 INPUT FROM PE1 & PE011 = QD1 INPUT FROM PE5 & PE4

QUAD DECODE COUNT REGISTERQDC1R (0x9004) QDC2R (0x0096)

07

BITS 0-7 OF QD COUNT

QUAD DECODE HIGH COUNT REGISTERQDC1HR (0x0095) QDC2HR (0x0097)

07

BITS 8-9 OF QD COUNT

0 0 0 0 0 0

I2C (Serial Port G) NOT ALL REGISTERS DISPLAYED; SEE PROCESSOR MANUAL FOR MORE DETAILS.

SERIAL PORT G CLOCK DIVISION x REGISTERSPGCD0R (0x0588) SPGCD1R (0x0589)SPGCD2R (0x058A)

07

18-BIT DIVIDER FOR I2C CLOCK

SERIAL PORT G MAIN CONTROL REGISTERSPGMCR (0x059F)

7

0

0

00 = I2C INTERRUPT DISABLEDXX = INTERRUPT PRIORITY

0

0

0 = SCL ON PE11 = SCL ON PE5

0 = SDA ON PE01 = SDA ON PE4

7

0

0 = NO INTERRUPT ON ADDRESS MATCH1 = INTERRUPT ON ADDRESS MATCH

0 = NO INTERRUPT ON START CONDITION1 = INTERRUPT ON START CONDITION

0 = NO INTERRUPT ON ARBITRATION LOST1 = INTERRUPT ON ARBITRATION LOST

0 = NO INTERRUPT ON STOP CONDITION1 = INTERRUPT ON STOP CONDITION0 = NO INTERRUPT ON NON-ACK1 = INTERRUPT ON NON-ACK

0 = NO INTERRUPT ON RX COMPLETE1 = INTERRUPT ON RX COMPLETE

SERIAL PORT G CONTROL 1 REGISTERSPG1R (0x0581)

0 = NO INTERRUPT ON TX COMPLETE1 = INTERRUPT ON TX COMPLETE

0

SERIAL PORT G CONTROL 0 REGISTERSGC0R (0x0580)

7

0

0 = PULL SCL LOW1 = READY TO RCV/XMIT

1 = INITIATE STOP CONDITION (MASTER)

0 = SEND ACK1 = SEND NACK

1 = INITIATE START CONDITION (MASTER)0 = NO RESPONSE TO GENERAL CALL1 = ENABLE RESPONSE0 = SLAVE MODE1 = MASTER MODE

1 = RESET I2C (AUTOMATICALLY CLEARED)

0 = DISABLE I2C1 = ENABLE I2C

7

0

0 = NO BYTE RECEIVED1 = BYTE RECEIVED

0 = NO STOP CONDITION1 = STOP CONDITION DETECTED

0 = NO NON-ACK RESPONSE1 = NON-ACK RESPONSE DETECTED

0 = NO BYTE TRANSMITTED1 = BYTE TRANSMITTED0 = I2C BUS NOT BUSY1 = I2C BUS BUSY

0 = I2C CONTROLLER NOT BUSY1 = I2C CONTROLLER BUSY

SERIAL PORT G STATUS 0 REGISTERSPS0R (0x0584)

0 = NO NON-ACK SENT OR RECEIVED1 = NON-ACK SEND OR RECEIVED0 = I2C NOT IN MASTER-RX OR SLAVE-TX1 = I2C IN MASTER-RX OR SLAVE-TX

SERIAL PORT G STATUS 1 REGISTERSPS1R (0x0585)

0 = NO SLAVE ADDRESS MATCH1 = SLAVE ADDRESS MATCH

7

0

0

0 = NO GENERAL CALL ADDRESS MATCH1 = GENERAL CALL ADDRESS MATCH

0

0

0 = NO START CONDITION DETECTED1 = START CONDITION DETECTED0 = ARBITRATION NOT LOST1 = ARBITRATION LOST

0

SERIAL PORT G DATA REGISTERSPGDR (0x058C)

07

RD: BYTE RECEIVED ON I2C BUS WR: BYTE TO BE SENT ON I2C BUS

SERIAL PORT G SLAVE ADDRESS 0 REGISTERSPGSA0R (0x0580)

07

SLAVE ADDRESS BITS 7:0

SERIAL PORT G SLAVE ADDRESS 1 REGISTERSPGSA1R (0x0581)

07

SLAVE ADDRESS BITS 9:8

0 0 0 0 0 0

SERIAL PORT G SLAVE ADDRESS 3 REGISTERSPGSA3R (0x0583)

07

0 = USE 7-BIT ADDRESSING1 = USE 10-BIT ADDRESSING

0 0 0 0 0 0 0

0

Real-Time Clock

REAL-TIME CLOCK CONTROL REGISTERRTCCR (0x0001)

01 = THIS BIT COMBINATION MUST BE USEDWITH EVERY BYTE INCREMENT WRITE

0 = NO EFFECT ON RTC COUNTER1 = INCREMENT CORRESPONDING BYTE

OF RTC (RTCxB)

7

0

RTC5B

RTC4B

RTC3B

RTC2B

RTC1B

RTC0B

RTCCR (SHORTCUTS)

0x00 = NO EFFECT ON RTC COUNTERDISABLE BYTE INCREMENTCANCEL RTC COMMAND

0x40 = ARM RTC FOR RESET OR BYTEINCREMENT. THIS COMMANDMUST BE WRITTEN PRIOR TORTC RESET OR FIRST BYTE RESET

0x80 = RESET ALL SIX BYTES OF RTCTO 0x00. RESET MUST BE PRECEDED BY WRITING0x40 TO ARM RESET FUNCTION

0xC0 = RESET ALL SIX BYTES IN RTC COUNTER TO 0x00 AND REMAININ BYTE INCREMENT MODE

7

0

REAL-TIME CLOCK x REGISTER 7 0

RD = CURRENT VALUE OF 48-BIT RTC HOLDING REGISTER IS RETURNED

W = A WRITE TO RTC0R TRANSFERS CURRENT COUNT OF RTC TO HOLDING REGISTER

RTC0R (0x0002) R/WRTC1R (0x0003) RDRTC2R (0x0004) RDRTC3R (0x0005) RDRTC4R (0x0006) RDRTC5R (0x0007) RD

Slave Port

SPD0R (0x0020) RDSA[1:0]

/SLAVE ATTENTION

/SRD

/SWR

/SCS

SD[7:0]

SLAVE PORT DATA REGISTERSINPUT REGISTERS

OUTPUTREGISTERS

SPD1R (0x0021) RDSPD2R (0x0022) RD

SPD0R (0x0020) WRSPD1R (0x0021) WR

SPD2R (0x0022) WR

MASTER

CONTROLLOGIC

RABBITCPU

SLAVE PORT STATUS REGISTERSPSR (0x0023)

7

0

WRITE CORRESPONDING PORT STATUS0 = EMPTY1 = FULL

READ CORRESPONDING PORT STATUS0 = EMPTY1 = FULL

0 = PROCESSOR WROTE TO SPSR1 = MASTER WROTE TO SPD0R

0 = MASTER WROTE TO STATUS REG1 = PROCESSOR WROTE TO SPD0R

SLAVE PORT CONTROL REGISTERSPCR (0x0024)

0 = PROGRAM FETCH AS A FUNCTION OF SMODE PINS1 = IGNORE SMODE PINS

(RD) = REPORT STATE OF SMODE PINS(WR) = IGNORED FOR WRITE000 = DISABLE SLAVE PORT. PORT A IS BYTE

WIDE INPUT001 = DISABLE SLAVE PORT. PORT A IS BYTE

WIDE OUTPUT010 = ENABLE SLAVE PORT. /SCS ON PE7011 = ENABLE EXT I/O BUS. ADDR BUS ON PB[7:2]110 = ENABLE SLAVE PORT. /SCS ON PB6111 = ENABLE EXT I/O BUS. ADDR BUS ON PB[7:0]

00 = SLAVE PORT INTERRUPT DISABLED01 = PRIORITY 1 INTERRUPT10 = PRIORITY 2 INTERRUPT11 = PRIORITY 3 INTERRUPT

7

0

Flexible Interface ModulesNOT ALL REGISTERS DISPLAYED; SEE PROCESSOR MANUAL FOR MORE DETAILS.

MASTER SYSTEM RESET REGISTERMSCR (0x0436)

7

0

0 = CLEAR FIM B RESET1 = RESET FIM B

0

0

0 = CLEAR FIM A RESET1 = RESET FIM A

0

0

0

0

7

0

0 = NORMAL PORT F1 = FIM CONTROLS PORT F

0 = NORMAL PORT H1 = FIM CONTROLS PORT H

0 = NORMAL PORT G1 = FIM CONTROLS PORT G

0 = NORMAL PORT E1 = FIM CONTROLS PORT E0 = NORMAL PORT D1 = FIM CONTROLS PORT D

0 = NORMAL PORT C1 = FIM CONTROLS PORT C

PORT OVERRIDE CONTROL REGISTERPOCR (0x0438)

0 = NORMAL PORT B1 = FIM CONTROLS PORT B0 = NORMAL PORT A1 = FIM CONTROLS PORT A

External I/O I/O CONTROLBANK REGISTER

IB7CR

IB6CR

IB5CR

IB4CR

IB3CR

IB2CR

IB1CR

IB0CR

(0x0087) I7

(0x0086) I6

(0x0085) I5

(0x0084) I4

(0x0083) I3

(0x0082) I2

(0x0081) I1

(0x0080) I0

PORT SIGNAL

1

1

1

1

0

0

0

0

1

1

0

0

1

1

0

0

1

0

1

0

1

0

1

0

I/O ADDRESSA15 A14 A13

7

0

0 = WRITES NOT ALLOWED1 = WRITES ALLOWED

I/O STROBE FUNCTIONS (IX)00 = I/O /CS01 = I/O /RD STROBE10 = I/O /WR STROBE11 = I/O DATA (/RD OR /WR) STROBE

WAITS STATES00 = 15 WS01 = 7 WS10 = 3 WS11 = 1 WS

I/O BANK x CONTROL REGISTER (IBxCR)

0 = ACTIVE LOW STROBE1 = ACTIVE HIGH STROBE0 = NORMAL I/O TRANSACTION TIMING1 = SHORTEN READ/WRITE STROBES0 = USE I/O BUS IF ENABLED1 = ALWAYS USE MEMORY DATA BUS

I/O HANDSHAKE CONTROL REGISTERIHCR (0x0028)

7

0

0

0

0

0

0 = I/O HANDSHAKE ACTIVE LOW1 = I/O HANDSHAKE ACTIVE HIGH

000 = HANDSHAKE WITH PE0001 = HANDSHAKE WITH PE1010 = HANDSHAKE WITH PE2011 = HANDSHAKE WITH PE3100 = HANDSHAKE WITH PE4101 = HANDSHAKE WITH PE5110 = HANDSHAKE WITH PE6111 = HANDSHAKE WITH PE7

I/O HANDSHAKE SELECT REGISTERIHSR (0x0029)

0 = DISABLE HANDSHAKE FOR I/O BANK1 = ENABLE HANDSHAKE FOR I/O BANK

07

I/O HANDSHAKE TIMEOUT REGISTERIHTR (0x002A)

0 = NO TIMEOUT OCCURRED1 = TIMEOUT OCCURRED

07

HANDSHAKE TIMEOUT COUNTER IN UNITS OF 32 CLOCKS

0

EXTENDEDREGISTER

(0x045F)

(0x045D)

(0x045B)

(0x0459)

(0x0457)

(0x0455)

(0x0453)

(0x0451)

I/O BANK x EXTENDED REGISTER7

0

0

0

0

0

0 = I/O BANK IS 8-BIT1 = I/O BANK IS 16-BIT

000 = USE CPU CLOCK100 = USE CPU CLOCK/2101 = USE CPU CLOCK/4110 = USE CPU CLOCK/8111 = USE CPU CLOCK/16

Timer BTIMER B CONTROL/STATUS REGISTERTBCSR (0x00B0)

7 0

0 0 0 0 0

(WRITE)0 = CORRESPONDING INTERRUPT IS DISABLED1 = CORRESPONDING

INTERRUPT IN ENABLED

0 = TIMMER B CLOCK (PCLK/2) IS DISABLED1 = TIMER B CLOCK (PCLK/2)

IS ENABLED(READ)0 = CORRESPONDING HAS NOT ENCOUNTERED A MATCH1 = CORRESPONDING INT. HAS ENCOUNTERED A MATCH

(STATUS BITS AND INTERUPTS ARE CLEARED BY READ OF THIS REGISTER)

TIMER B MATCH 1 REGISTER

BIT9

BIT7(LSB)

(MSB)

BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

BIT8 0 0 0 0 0 0TBM1R(0x00B2)

TBL1R(0x00B3)

TIMER B MATCH 2 REGISTER

BIT9

BIT7(LSB)

(MSB)

BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

BIT8 0 0 0 0 0 0TBM2R(0x00B4)

TBL2R(0x00B5)

TIMER B COUNT REGISTER

BIT9

BIT7(LSB)

(MSB)

BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

BIT8 0 0 0 0 0 0TBCMR(0x00BE)

TBCLR(0x00BF)

TIMER B CONTROL REGISTERTBCR (0x00B1)

0

70

0 0 = NORMAL B2 OPERATION1 = B2 USES STEP REGS0 = NORMAL B1 OPERATION1 = B1 USES STEP REGS00 = CLOCKED BY PCLK/201 = CLOCKED BY TIMER A110 = CLOCKED BY PCLK/1611 = CLOCKED BY A1100 = INTERRUPTS DISABLED01 = PRIORITY 1 INTERRUPT10 = PRIORITY 2 INTERRUPT11 = PRIORITY 3 INTERRUPT

TIMER B STEP LSB x REGISTERTBSL1R (0x00BA) TBSL2R (0x00BC)

07

LSB OF STEP SIZE FOR COMPARATOR

TIMER B STEP MSB x REGISTERTBSM1R (0x00BB) TBSM2R (0x00BD)

07

MSB OF STEP SIZE FOR COMPARATOR

0 00 00 0

Timer C TIMER C CONTROL/STATUS REGISTERTCCSR (0x0500)

7 0

0 0 0 0 0 0

0 = LIMIT NOT REACHED1 = LIMIT REACHED 0 = TIMER C CLOCK (PCLK/2) IS DISABLED

1 = TIMER C CLOCK (PCLK/2) IS ENABLED

TIMER C DIVIDER LOW REGISTERTCDLR (0x0502)

07

TIMER C DIVIDER HIGH REGISTERTCDHR (0x0503)

815

TIMER C SET x LOW REGISTERTCS0LR (0x0508) TCS1LR (0x050C)TCS2LR (0x0518) TCS3LR (0x051C)

07

TIMER C SET x HIGH REGISTERTCS0HR (0x0509) TCS1HR (0x050D)TCS2HR (0x0519) TCS3HR (0x051D)

815

TIMER C BLOCK ACCESS REGISTERTCBAR (0x00F8)

07

ACCESS REGISTER POINTED TO BY TCBPR

TIMER C BLOCK POINTER REGISTERTCDBPR (0x00F9)

07

LSB OF REGISTER ADDRESS

0 0 0

TIMER C RESET x LOW REGISTERTCR0LR (0x050A) TCR1LR (0x050E)TCR2LR (0x051A) TCR3LR (0x051E)

07

TIMER C RESET x HIGH REGISTERTCR0HR (0x050B) TCR1HR (0x050F)TCR2HR(0x051B) TCR3HR (0x051F)

815

TIMER C CONTROL REGISTERTCCR (0x0501)

00 = CLOCKED BY PCLK/201 = CLOCKED BY TIMER A110 = CLOCKED BY PCLK/1611 = CLOCKED BY A11

00 = INTERRUPTS DISABLED01 = PRIORITY 1 INTERRUPT10 = PRIORITY 2 INTERRUPT11 = PRIORITY 3 INTERRUPT

7 0

0 0 0 0

Timer A

7 0

TMRA7 TMRA6 TMRA5 TMRA4 TMRA3 TMRA2 TMRA1

(WRITE)0 = CORRESPONDING TIMER A INTERRUPT IS DISABLED1 = CORRESPONDING TIMER A

INTERRUPT IS ENABLED

0 = TIMER A CLOCK IS DISABLED

1 = TIMER A CLOCK IS ENABLED

(READ)0 = CORRESPONDING TIMER A HAS NOT REACHED TERM. COUNT1 = CORRESPONDING TIMER A HAS REACHED TERM. COUNT

TIMER A CONTROL/STATUS REGISTER / TACSR (0x00A0)

RESULTS IN ALL TIMER A TIMERS TO BE CLOCKED BY PCLK OR PCLK/2

TIMER A PRESCALE REGISTER / TAPR (0x00A1) 7 0

TIMER A CLOCK DIVIDER

7 0

TMRA7 TMRA6 TMRA5 TMRA4

0 = CORRESPONDING TIMER CLOCKED BY MAIN TIMER A CLK 1 = CORRESPONDING TIMER

CLOCKED BY TIMER A1

00 = INTERRUPTS DISABLED01 = PRIORITY 1 INTERRUPT10 = PRIORITY 2 INTERRUPT11 = PRIORITY 3 INTERRUPT

TIMER A CONTROL REGISTER / TACR (0x00A4)

TMRA3 TMRA2

TIMER A EXTENDED CONTROL REGISTERTAECR (0x00A2)

0

70

0

0 = TIMER A11 CLOCKED BY TAPR1 = TIMER A11 CLOCKED BY A120 = TIMER A10 CLOCKED BY TAPR1 = TIMER A10 CLOCKED BY A12

0

0

0 = TIMER A9 CLOCKED BY TAPR1 = TIMER A9 CLOCKED BY A120 = TIMER A8 CLOCKED BY TAPR1 = TIMER A8 CLOCKED BY A12

TIMER CONSTANT REGISTERS

TIMER

TAT1R (0x00A3)

TAT2R (0x00A5)

TAT3R (0x00A7)

TAT4R (0x00A9)

TAT5R (0x00AB)

TAT6R (0x00AD)

TAT7R (0x00AF)

TAT8R (0x00A6)

TAT9R (0x00A8)

TAT10R (0x00AA)

TAT11R (0x00AC)

TAT12R (0x00AE)

CASCADE FROM PERIPHERAL

VARIOUS

SERIAL PORT E

SERIAL PORT F

SERIAL PORT A

SERIAL PORT B

SERIAL PORT C

SERIAL PORT D

INPUT CAPTURE

PWM

QUADRATURE DECODER

TIMERS B AND C

TIMERS A8-A11

NONE

A1

A1

A1

A1

A1

A1

A12

A12

A12

A12

NONE

BreakpointsBREAKPOINT CONTROL REGISTERB0CR (0x030B) B4CR (0x034B)B1CR (0x031B) B5CR (0x036B)B2CR (0x032B) B6CR (0x037B)B3CR (0x0033B)

0

7

0

0

00 = NO BKPT ON EXECUTE MATCH01 = BKPT ON USER EXECUTE MATCH10 = BKPT ON SYSTEM EXECUTE MATCH11 = BKPT ON SYS OR USER EXECUTE MATCH00 = NO BKPT ON READ MATCH01 = BKPT ON USER READ MATCH10 = BKPT ON SYSTEM READ MATCH11 = BKPT ON SYS OR USER READ MATCH00 = NO BKPT ON WRITE MATCH01 = BKPT ON USER WRITE MATCH10 = BKPT ON SYSTEM WRITE MATCH11 = BKPT ON SYS OR USER WRITE MATCH

RESERVEDMUST = 0

RD = CORRESPONDING BREAKPOINT IS PENDING. CLEARED WHEN THIS REGISTER READWR = MAKE CORRESPONDING BREAKPOINT PENDING

7

0

BREAKPOINT/DEBUG CONTROL REGISTERBDCR (0x001C)

0 = NORMAL RST281 = RST28 = NOP

BREAKPOINT ADDRESS REGISTERSB0A2R (0x030E) B0A1R (0x030D) B0A0R (0x030C)B1A2R (0x031E) B1A1R (0x031D) B1A0R (0x031C)B2A2R (0x032E) B2A1R (0x032D) B2A0R (0x032C)B3A2R (0x033E) B3A1R (0x033D) B3A0R (0x033C)B4A2R (0x034E) B4A1R (0x034D) B4A0R (0x034C)B5A2R (0x036E) B5A1R (0x036D) B5A0R (0x036C)B6A2R (0x037E) B6A1R (0x037D) B6A0R (0x037C)

7 015 823 16

PHYSICAL ADDRESS MASK

BxA2R BxA1R BxA0R

BREAKPOINT MASK REGISTERSB0M2R (0x030A) B0M1R (0x0309) B0M0R (0x0308)B1M2R (0x031A) B1M1R (0x0319) B1M0R (0x0318)B2M2R (0x032A) B2M1R (0x0329) B2M0R (0x0328)B3M2R (0x033A) B3M1R (0x0339) B3M0R (0x0338)B4M2R (0x034A) B4M1R (0x0349) B4M0R (0x0348)B5M2R (0x036A) B5M1R (0x0369) B5M0R (0x0368)B6M2R (0x037A) B6M1R (0x0379) B6M0R (0x0378)

7 015 823 16

PHYSICAL ADDRESS MASK

BxM2R BxM1R BxM0R

PORT x DATA REGISTERSPADR (0x0030) PDDR (0x0060) PBDR (0x0040) PEDR (0x0070) PCDR (0x0050) PHDR (0x0034)

07

READ/WRITE DATA TO PORT

PORT x DATA DIRECTION REGISTERSPBDDR (0x0007) PEDDR (0x0077)PCDDR (0x0051) PHDDR (0x0037)PDDDR (0x0067)

07

0 = CORRESPONDING BIT IS INPUT1 = CORRESPONDING BIT IS OUTPUT

PORT x DRIVE CONTROL REGISTERSPCDCR (0x0054) PEDCR (0x0076)PDDCR (0x0066) PHDCR (0x0036)

07

0 = OUTPUT IS DRIVEN HIGH AND LOW1 = OUTPUT IS OPEN-DRAIN

PORT x FUNCTION REGISTERSPCFR (0x0055) PEFR (0x0075)PDFR (0x0065) PHFR (0x0035)

07

0 = BIT FUNCTIONS AS I/O1 = BIT IS ALTERNATE OUTPUT

PORT x DRIVE CONTROL REGISTERSPCDCR (0x0054) PEDCR (0x0076)PDDCR (0x0066)

07

0 = OUTPUT IS DRIVEN HIGH AND LOW1 = OUTPUT IS OPEN DRAIN

PORT x CONTROL REGISTERPDCR (0x0064) PECR(0x0074)

0

7

UPPER NIBBLE CLOCK IS PERCLK UPPER NIBBLE CLOCK IS TIMER A1UPPER NIBBLE CLOCK IS TIMER B1UPPER NIBBLE CLOCK IS TIMER B2

LOWER NIBBLE CLOCK IS PERCLKLOWER NIBBLE CLOCK IS TIMER A1 LOWER NIBBLE CLOCK IS TIMER B1 LOWER NIBBLE CLOCK IS TIMER B2

0

0

0

0

PORT x ALTERNATE LOW REGISTERSPCALR (0x0052) PEALR (0x0072)PDALR (0x0062) PHALR (0x0032)

0

7

SELECT BIT 3 ALTERNATE OUTPUT

SELECT BIT 2 ALTERNATE OUTPUT

SELECT BIT 1 ALTERNATE OUTPUT

SELECT BIT 0 ALTERNATE OUTPUT

PORT x ALTERNATE HIGH REGISTERSPCAHR (0x0053) PEAHR (0x0073)PDAHR (0x0063)

0

7

SELECT BIT 7 ALTERNATE OUTPUT

SELECT BIT 6 ALTERNATE OUTPUT

SELECT BIT 5 ALTERNATE OUTPUT

SELECT BIT 4 ALTERNATE OUTPUT

PORT x BIT y REGISTERSPDB0R (0x0068) PEB0R (0x0078)PDB1R (0x0069) PEB1R (0x0079)PDB2R (0x006A) PEB2R (0x007A)PDB3R (0x006B) PEB3R (0x007B)PDB4R (0x006C) PEB4R (0x007C)PDB5R (0x006D) PEB5R (0x007D)PDB6R (0x006E) PEB6R (0x007E)PDB7R (0x006F) PEB7R (0x007F)

07

A WRITE TO THE CORRESPONDING BIT CHANGES THAT BIT

PARALLEL PORT C

PIN

PC7

PC6

PC5

PC4

PC3

PC2

PC1

PC0

ALTO ALT1 ALT2 ALT3

TXA

TXA

TXB

TXB

TXC

TXC

TXD

TXD

I7

I6

I5

I4

I3

I2

I1

I0

PWM3

PWM2

PWM1

PWM0

TMRC3

TMRC2

TMRC1

TMRC0

SCLKC

TXE

RCLKE

TCLKE

SCLKD

TXF

RCLKF

TCLKF

ALTERNATE OUTPUT FUNCTIONS: PORTS C, D, E, F-G, H

PARALLEL PORT D

PIN

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

ALT0 ALT1 ALT2 ALT3

IA7

TXA

IA6

TXB

IA7

SCLKC

IA6

SCLKD

I7

I6

I5

I4

I3

I2

I1

I0

PWM3

PWM2

PWM1

PWM0

TMRC3

TMRC2

TMRC1

TMRC0

SCLKC

TXE

RCLKE

TCLKE

SCLKD

TXF

RCLKF

TCLKF

PARALLEL PORT E

PIN ALT0 ALT1 ALT2 ALT3

PE7

PE6

PE5

PE4

PE3

PE2

PE1

PE0

SCLKG

SDATG

USBPWR

SCLKG

SDATG

I7

I6

I5

I4

I3

I2

I1

I0

PWM3

PWM2

PWM1

PWM0

TMRC3

TMRC2

TMRC1

TMRC0

SCLKC

TXE

RCLKE

TCLKE

SCLKD

TXF

RCLKF

TCLKF

RXA

RXB

RXC

RXD

RXE

RCLKE

TCLKE

RXF

RCLKF

TCLKF

YES

YES

YES

YES

ALTERNATE INPUT FUNCTIONS: PORTS C, D, E, F-G, H

SERIALA–D

SERIALE–F

INPUTCAPT

PARALLEL PORT C

PIN

PC7

PC6

PC5

PC4

PC3

PC2

PC1

PC0

PARALLEL PORT D

DREQ1

DREQ0

INT1

INT0

QRD2A

QRD2B

QRD1A

RQD1B

SERIALA–D

SERIALE–F

INPUTCAPT

DMA& INT

QUADDEC

RXA

RXB

RXC

SCLKC

RXD

SCLKD

YES

YES

YES

YES

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

PIN

PARALLEL PORT E

QRD2A

QRD2B

QRD1A

QRD1B

SERIALA–D

SERIALE–F

INPUTCAPT

DMA& INT

QUADDEC

RXA

RXB

RXC

SCLKC

RXD

SCLKD

PE7

PE6

PE5

PE4

PE3

PE2

PE1

PE0

DREQ1

DREQ0

INT1

INT0

DREQ1

DREQ0

INT1

INT0

YES

YES

YES

YES

PIN

RXE

RCLKE

TCLKE

RXF

RCLKF

TCLKF

RXE

RCLKE

TCLKE

RXF

RCLKF

TCLKF

YES

YES

YES

YES

YES

YES

YES

YES

I/OHANDSH

PARALLEL PORT H

PIN ALT0 ALT1 ALT2 ALT3

PH7

PH6

PH5

PH4

PH3

PH2

PH1

PH0

I7

I6

I5

I4

I3

I2

I1

I0

PWM3

PWM2

PWM1

PWM0

TMRC3

TMRC2

TMRC1

TMRC0

SCLKC

TXE

RCLKE

TCLKE

SCLKD

TXF

ACLKF

TCLKF

DATA BUS

16-B

IT D

ATA

BU

S

PARALLEL PORT H

PIN

PH7

PH6

PH5

PH4

PH3

PH2

PH1

PH0

DATA BUS

16-B

IT D

ATA

BU

S

PARALLEL PORT A*

AUX I/OSLAVE I/O

PA7

PA6

PA5

PA4

PA3

PA2

PA1

PA0

PAR

ALL

EL I/

O

SLA

VE

DA

TA

EXT

I/O D

ATA

*SELECTION VIA SPCR

*SELECTION VIA SPCR, SACR, SBCR

PARALLEL PORT B*

PIN

PB7

PB6

PB5

PB4

PB3

PB2

PB1

PB0

AUX I/OSLAVE SERIAL

IA5

IA4

IA3

IA2

IA1

IA0

IA7

IA6

SCLKA

SCLKB

/ATTN

/SCS

SA1

SA0

/SRD

/SWR

PIN

PARALLEL PORTS F-G

PIN

PF7/PG7

PF6/PG6

PF5/PG5

PF4/PG4

PF3/PG3

PF2/PG2

PF1/PG1

PF0/PG0

ALT0 ALT1 ALT2 ALT3

FIMA/B[7]

FIMA/B[6]

FIMA/B[5]

FIMA/B[4]

FIMA/B[3]

FIMA/B[2]

FIMA/B[1]

FIMA/B[0]

I7

I6

I5

I4

I3

I2

I1

I0

PWM3

PWM2

PWM1

PWM0

TMRC3

TMRC2

TMRC1

TMRC0

SCLKC

TXE

RCLKE

TCLKE

SCLKD

TXF

RCLKF

TCLKF

USBOVR

USB

PARALLEL PORTS F-G

PIN

PF7/PG7

PF6/PG6

PF5/PG5

PF4/PG4

PF3/PG3

PF2/PG2

PF1/PG1

PF0/PG0

INT FIM

FIMA/B[7]

FIMA/B[6]

FIMA/B[5]

FIMA/B[4]

FIMA/B[3]

FIMA/B[2]

FIMA/B[1]

FIMA/B[0]

INT2-7

INT2-7

INT2-7

INT2-7

INT2-7

INT2-7

INT2-7

INT2-7

PORT x BIT y CONTROL REGISTER

0 = FAST OUTPUT SLEW1 = SLOW OUTPUT SLEW00 = 4mA OUTPUT DRIVE01 = 8mA OUTPUT DRIVE10 = 10mA OUTPUT DRIVE11 = 14mA OUTPUT DRIVE00 = NO PULLUP/DOWN01 = 75KOHM PULLUP10 = 75KOHM PULLDOWN11 = 75KOHM KEEPER

7

0

PAyCR (0x04By) PByCR (0x04Cy)PCyCR (0x04Dy) PDyCR (0x04Ey)PEyCR (0x04Fy) PFyCR (0x04By+8)PGyCR (0x04Cy+8) PHyCR (0x04Dy+8)

0

0

0

Memory Management Unit

MMU INSTRUCTION/DATA REGISTERMMIDR (0x0010) R/W

0

7

0 = A16, MSB INVERSION INDEPENDENT OF INSTRUCTION/DATA1 = A16, MSB INVERSION FOR DATA ACCESS ONLY. (THIS ENABLES SEPARATE I AND D SPACE)

0 = USE 8-BIT INTERNAL I/O ADDRESSES1 = USE 15-BIT INTERNAL I/O ADDRESSESRESERVED WRITE MUST = 0

0 = NORMAL /CS1 OPERATION1 = FORCE /CS1 ALWAYS ACTIVE

0 = NORMAL1 = INVERT MSB ON DATASEG ACCESS

0 = NORMAL1 = INVERT A16 ON DATASEG ACCESS

0 = NORMAL1 = INVERT BANK SEL ADDR MSB ON ROOT ACCESS

0 = NORMAL1 = INVERT A16 ON ROOT ACCESS

0

RAM SEGMENT REGISTERRAMSR (0x0448)

0

7

00 = DISABLE RAM SEGMENT LIMIT CHECKING

01 = SELECT DATA MMU TRANSLATION IF PC[15:10] = RAMSR[7:2]

10 = SELECT DATA MMU TRANSLATION IF PC[15:11] = RAMSR[7:3]

11 = SELECT DATA MMU TRANSLATION IF PC[15:12] = RAMSR[7:4]

COMPARE VALUE FOR RAM SEGMENT LIMIT CHECKING

MEMORY TIMING CONTROL REGISTERMTCR (0x0019)

0 = NORMAL TIMING 1 = EXTENDED TIMING 0 = NO INTERNAL WRITE

WAIT STATES1 = ADD INTERNAL WRITE WAIT STATE

7 0

0 0 0 /OE1 /OE0 /WE1 /WE0

FFFF

FFFFFF

64 KB

16 MB

0X000

00000

E000

Y000

X000

0000

0347

XMEM

STACKSEGMENT

DATASEGMENT

ROOT

LOGICALADDRESS MAP

PHYSICALADDRESS MAP

Y X SEGSIZE(0X13) R/W

SEGMENT REGISTERS

023

24-BIT PHYSICAL ADDRESS

7811 4 3 0

XPCSEGMENT H/L

015

16-BIT LOGICAL ADDRESS

DATA SEGMENTH/L REGISTERS(0x1E) (0x1F)

7811 4 3 0

XPCDATASEG H/L

DATA SEGMENTREGISTER(0x12)

7811 4 3 0

XPCDATASEG0000

STACK SEGMENTH/L REGISTERS(0x18) (0x1A)

7811 4 3 0

XPCSTACKSEG H/L

STACK SEGMENTREGISTER(0x11)

7811 4 3 0

XPCSTACKSEG0000

EXTENDED PROGRAMCOUNTER REGISTER

7811 4 3 0

XPCLXPC

7811 4 3 0

XPCXPC0000

WRITING TO DATASEG/STACKSEG PUTS 8-BIT VALUE INTO DATASEGL/STACKSEGL AND 0000 INTO DATASEGH/STACKSEGH.

WRITING TO XPC PUTS VALUE INTO LOWER 8 BITS AND 0000 INTO UPPER 4 BITS OF LXPC

X ≤Y ≤0xE

ADVANCED CHIP SELECT CONTROL REGISTERSACS0CR (0x0410) ACS1CR (0x0411)ACS2CR (0x0412)

0

7

000 = 0 EXTRA WS (RD, WR, 1st PAGE READ)001 = 1 EXTRA WS (RD, WR, 1st PAGE READ)010 = 2 EXTRA WS (RD, WR, 1st PAGE READ)011 = 3 EXTRA WS (RD, WR, 1st PAGE READ)100 = 4 EXTRA WS (RD, WR, 1st PAGE READ)101 = 5 EXTRA WS (RD, WR, 1st PAGE READ)110 = 6 EXTRA WS (RD, WR, 1st PAGE READ)111 = 7 EXTRA WS (RD, WR, 1st PAGE READ)

00 = 0 EXTRA WS (LATER PAGE READS)01 = 1 EXTRA WS (LATER PAGE READS)10 = 2 EXTRA WS (LATER PAGE READS)11 = 3 EXTRA WS (LATER PAGE READS)

0 = PAGE SIZE 16 BYTES1 = PAGE SIZE 8 BYTES

0 = DISABLE BYTE WRITES ON 16-BIT BUS1 = ENABLE BYTE WRITES ON 16-BIT BUS

MEMORY ALTERNATE CONTROL REGISTERMACR (0x001D)

7

0

0

0 = NORMAL 8-BIT OPERATION FOR /CS31 = NORMAL 16-BIT OPERATION FOR /CS3

00 = NORMAL 8-BIT OPERATION FOR /CS201 = PAGE-MODE 8-BIT OPERATION FOR /CS210 = NORMAL 16-BIT OPERATION FOR /CS211 = PAGE-MODE 16-BIT OPERATION FOR /CS2

00 = NORMAL 8-BIT OPERATION FOR /CS101 = PAGE-MODE 8-BIT OPERATION FOR /CS110 = NORMAL 16-BIT OPERATION FOR /CS111 = PAGE-MODE 16-BIT OPERATION FOR /CS1

00 = NORMAL 8-BIT OPERATION FOR /CS001 = PAGE-MODE 8-BIT OPERATION FOR /CS010 = NORMAL 16-BIT OPERATION FOR /CS011 = PAGE-MODE 16-BIT OPERATION FOR /CS0

MMU EXPANDED CODE REGISTERMECR (0x0018)

0

7

0000 = NORMAL0100 = USE MB0LCR FOR XPC ACCESS0101 = USE MB1LCR FOR XPC ACCESS0110 = USB MB2LCR FOR XPC ACCESS0111 = USB MB3LCR FOR XPC ACCESS1100 = USB MB0HCR FOR XPC ACCESS 1101 = USB MB1HCR FOR XPC ACCESS1110 = USB MB2HCR FOR XPC ACCESS1111 = USB MB3HCR FOR XPC ACCESS

000 = BANK SELECT ADDRESS IS A [19:18]001 = BANK SELECT ADDRESS IS A [20:19] 010 = BANK SELECT ADDRESS IS A [21:20] 011 = BANK SELECT ADDRESS IS A [22:21] 100 = BANK SELECT ADDRESS IS A [23:22]111 = BANK SELECT ADDRESS IS A [18:17]OTHERS RESERVED 0

0 = NO ADDITIONAL WAIT STATES1 = ADD 8 WAIT STATES

00 = 4 WS (5 FOR WRITES)01 = 2 WS (3 FOR WRITES)10 = 1 WS (2 FOR WRITES)11 = 0 WS (1 FOR WRITES)

MBxCR

MEMORY BANK CONTROL REGISTERS

0

7

00 = /OE0 AND /WE0 ARE ACTIVE01 = /OE1 AND /WE1 ARE ACTIVE10 = /OE0 IS ACTIVE (READ ONLY)11 = /OE1 IS ACTIVE (READ ONLY)00 = /CS0 IS ACTIVE01 = /CS1 IS ACTIVE10 = /CS2 IS ACTIVE11 = /CS3 (INTERNAL MEM) IS ACTIVE

0 = PASS BANK SEL ADDR MSB0 = INVERT BANK SEL ADDR MSB0 = PASS BANK SEL ADDR LSB0 = INVERT BANK SEL ADDR LSB

BANK SELECTBITS00x000001

01x010011

10x100101

11x110111

CONTROLREGISTER USED

MB0CRMB0LCRMB0HCR

MB1CRMB1LCRMB1HCR

MB2CRMB2LCRMB2HCR

MB3CRMB2LCRMB2HCR

ADDRESS(0x0014)(0x0400)(0x0401)

(0x0015)(0x0402)(0x0403)

(0x0016)(0x0404)(0x0405)

(0x0017)(0x0406)(0x0407)

Serial Ports

0 = NORMAL CODING1 = ENABLE RZI CODING (3/16 IrDA)0 = NORMAL BREAK OPERATION1 = FAST BREAK TERMINATION0 = ASYNC CLK = 16 × DATA RATE1 = ASYNC CLK = 8 × DATA RATE0 = CHAR ASSY DURING BREAK1 = NO CHAR ASSY DURING BREAK

SERIAL PORT x EXTENDED REGISTERSAER (0x00C5)SBER (0x00D5)SCER (0x00E5)SDER (0x00F5)SEER (0x00CD)SFER (0x00DD)

ASYNCH MODE (A,B,C,D,E,F)RESERVED000 = DISABLE PARITY100 = ENABLE EVEN PARITY101 = ENABLE ODD PARITY110 = ENABLE SPACE PARITY111 = ENABLE MARK PARITY

7

00

0 = NORMAL CLOCKED SERIAL OPERATION1 = TIMER-SYNCHED CLOCKED SERIAL OPERATION

TERMINATE XMITTERMINATE RECEIVE

0 = TIMED BY TIMER B11 = TIMED BY TIMER B2

00 = NORMAL CLK, INACTIVE HIGH, INT OR EXT CLK01 = NORMAL CLK, INACTIVE LOW, INT CLK10 = INVERTED CLK, INACTIVE LOW, INT OR EXT CLK11 = INVERTED CLK, INACTIVE HIGH, INT CLK

0 = CLOCK INPUT FROM PARALLEL PORT D (SCER, SDER)1 = CLOCK INPUT FROM PARALLEL PORT E (SCER, SDER)

0 = NORMAL DATA BIT ORDER1 = REVERSE DATA BIT ORDER

CLOCKED MODE (A,B,C,D)7

0

0 = NORMAL DATA CODING1 = ENABLE RZI ENCODING (¼-BIT IrDA)

(W/NRZ & INT CLK)0 = IDLE LINE COND. = FLAG1 = IDLE LINE COND. = ONE

0 = XMIT FLAG ON UNDERRUN1 = XMIT ABORT ON UNDERRUN0 = SEPARATE EXTERNAL RCV/XMIT CLOCKS1 = COMBINED EXTERNAL RCV/XMIT CLOCKS

(XMIT PIN)

000 = NRZ DATA CODING010 = NRZI DATA CODING100 = BIPHASE LEVEL CODING (MANCHESTER)110 = BIPHASE SPACE CODING (FM0)111 = BIPHASE MARK CODING (FM1)

HDLC MODE (E,F)7

00

SERIAL PORT x STATUS REGISTER

7

0

7

00 = XMIT IDLE1 = XMIT SENDING BYTE

0 = XMIT BUF EMPTY1 = XMIT BUF FULL

ASYNCH MODE (A,B,C,D,E,F)

0

0

0 = RCV DATA REG EMPTY1 = BYTE IN RCV BUF, INTERRUPT CLEARED WHEN RCV BUF READ0 = BYTE IN RCV BUF IS DATA1 = BYTE IN RCV BUF IS ADDRESS

0 = RCV BUF NOT OVERRUN1 = RCV BUF OVERRUN, CLEARED WHEN RCV BUF READ

0 = BYTE IN RCV BUF PARITY OK1 = BYTE IN RCV BUF PARITY ERROR 0 = XMIT IDLE

1 = XMIT SENDING BYTE

0 = XMIT BUF EMPTY1 = XMIT BUF FULL

CLOCKED MODE (A,B,C,D)

0

0

0 = RCV DATA REG EMPTY1 = BYTE IN RCV BUF, INTERRUPT CLEARED WHEN RCV BUF READ

0 = RCV BUF NOT OVERRUN1 = RCV BUF OVERRUN, CLEARED WHEN RCV BUF READ

0

0

HDLC MODE (E,F)

7

0 00 = XMIT INT, BUF EMPTY01 = XMIT FINISHED SENDING CRC10 = XMIT FINISHED SENDING ABORT11 = XMIT FINISHED SENDING CLOSING FLAG

0 = XMIT BUF EMPTY1 = XMIT BUF FULL

0 = RCV DATA REG EMPTY1 = BYTE IN RCV BUF, INTERRUPT CLEARED WHEN RCV BUF READ

00 = BYTE IN RCV BUF IS DATA01 = BYTE IN RCV BUF FOLLOWED BY ABORT10 = BYTE IN RCV BUF LAST IN FRAME, CRC VALID11 = BYTE IN RCV BUF LAST IN FRAME, CRC ERROR

0 = RCV BUF NOT OVERRUN1 = RCV BUF OVERRUN, CLEARED WHEN RCV BUF READ

BITS

[6,4

]

0 = BYTE IN RCV BUT IS 8 BITS1 = BYTE IN RCV BUF < 8 BITS

SASR (0x00C3)SBSR (0x00D3)SCSR (0x00E3)SDSR (0x00F3)SESR (0x00CB)SFSR (0x00DB)

**ASYNCH ONLY (REFER TO MANUAL FOR CLOCKED SERIAL & HDLC) *** TX INTERRUPTS ARE CLEARED WITH A WRITE TO THE SxSR

SERIAL PORT x DATA REGISTER (SxDR)SADR (0x00C0) SBDR (0x00D0) SCDR (0x00E0) SDDR (0x00F0) SEDR (0x00C8) SFDR (0x00D8)

RD = RETURNS CONTENTS OF RECEIVE BUFFER

WR = LOADS XMIT BUFFER WITH DATA BYTE FOR TRANSMISSION

07 7

SERIAL PORT x ADDRESS REGISTER**SAAR (0x00C1) SBAR (0x00D1) SCAR (0x00E1) SDAR (0x00F1) SEAR (0x00C9) SFAR (0x00D9)

RD = RETURNS CONTENTS OF RECEIVE BUFFERW R = LOADS XMIT BUFFER WITH ADDRESS BYTE

FOR TRANSMISSION (9TH BIT=0)

0

SERIAL PORT x LONG STOP REGISTER (SxLR)SALR (0x00C2) SBLR (0x00D2)SCLR (0x00E2) SDLR (0x00F2)SELR (0x00CA) SFLR (0x00DA)

RD = RETURNS CONTENTS OF RECEIVE BUFFERWR = LOADS XMIT BUFFER WITH ADDRESS BYTE FOR TRANSMISSION

07

SERIAL PORT x CONTROL REGISTER (SxCR)

00 = NO OPERATION. IGNORED IN ASYNCH MODE01 = CLOCKED MODE: START BYTE RCV OPERATION10 = CLOCKED MODE: START BYTE XMIT OPERATION11 = CLOCKED MODE: START SIMULT. BYTE RCV & XMIT00 = PARALLEL PORT C USED FOR INPUT01 = PARALLEL PORT D USED FOR INPUT10 = PARALLEL PORT E USED FOR INPUT11 = DISBALE RCV INPUT00 = ASYNCH MODE: 8 BITS PER CHAR.01 = ASYNCH MODE: 7 BITS PER CHAR.10 = CLOCKED MODE: EXTERNAL CLOCK (INPUT)11 = CLOCKED MODE: INTERNAL CLOCK (OUTPUT)

INTERRUPT 00 = DISABLED01 = PRIORITY 110 = PRIORITY 211 = PRIORITY 3

7

0

SACR (0x00C4) SBCR (0x00D4)SCCR (0x00E4) SDCR (0x00F4)

SECR (0x00CC) SFCR (0x00DC)

00 = NO OPERATION (IGNORED IN ASYNCH MODE)01 = HDLC MODE: FORCE FLAG SEARCH MODE10 = NO OPERATION11 = HDLC MODE: TRANSMIT ABORT PATTERN00 = PARALLEL PORT C USED FOR INPUT01 = PARALLEL PORT D USED FOR INPUT10 = PARALLEL PORT E USED FOR INPUT11 = DISABLE RECEIVE INPUT00 = ASYNCH MODE: 8 BITS PER CHAR.01 = ASYNCH MODE: 7 BITS PER CHAR.10 = HDLC MODE: EXTERNAL CLOCK (INPUT)11 = HDLC MODE: INTERNAL CLOCK (OUTPUT)

INTERRUPT 00 = DISABLED01 = PRIORITY 110 = PRIORITY 211 = PRIORITY 3

7

0

SERIAL PORT x DIVIDER LOW REGISTERSADLR (0x00C6) SBDLR (0x00D6) SCDLR (0x00E6) SDDLR (0x00F6) SEDLR (0x00CE) SFDLR (0x00DE)

07

SERIAL PORT x DIVIDER HIGH REGISTERSADHR (0x00C7) SBDHR (0x00D7) SCDHR (0x00E7) SDDHR (0x00F7) SEDHR (0x00CF) SFDHR (0x00DF)

815

ENABLE DEDICATED SERIAL PORT DIVIDER

15-BIT DIVIDER VALUE

15-BIT DIVIDER VALUE

Tamper-Protect RAMTAMPER -PROTECT BYTE XVRAM00 (0x0600) VRAM08 (0x0608) VRAM16 (0x0610) VRAM24 (0x0618) VRAM01 (0x0601) VRAM09 (0x0609) VRAM17 (0x0611) VRAM25 (0x0619)VRAM02 (0x0602) VRAM10 (0x060A) VRAM18 (0x0612) VRAM26 (0x061A) VRAM03 (0x0603) VRAM11 (0x060B) VRAM19 (0x0613) VRAM27 (0x061B)VRAM04 (0x0604) VRAM12 (0x060C) VRAM20 (0x0614) VRAM28 (0x061C) VRAM05 (0x0605) VRAM13 (0x060D) VRAM21 (0x0615) VRAM29 (0x061D)VRAM06 (0x0606) VRAM14 (0x060E) VRAM22 (0x0616) VRAM30 (0x061E) VRAM07 (0x0607) VRAM15 (0x060F) VRAM23 (0x0617) VRAM31 (0x061F)

7 0

ACCESS TAMPER-PROTECTED BYTE

WATCHDOG TIMER CONTROL REGISTERWDTCR (0x0008)

0x5A = RESET WDT WITH 2-SECOND TIMEOUT0x57 = RESET WDT WITH 1-SECOND TIMEOUT0x59 = RESET WDT WITH 0.5-SECOND TIMEOUT0x53 = RESET WDT WITH 0.25-SECOND TIMEOUT0x5F = RESTART SECONDARY WATCHDOG TIMEROTHER = NO EFFECTREAD = LSB OF CPU CLOCK CYCLE COUNTER

0x54 = DISABLE WDT (MUST BE PRECEDED BY A WRITE OF 0x51,0x52, OR 0x53)

TO THIS REGISTEROTHER = NORMAL, WATCHDOG TIMER

IS CLOCKED BY 32 kHz CLOCKREAD = MSB OF CPU CLOCK CYCLE COUNTER

WATCHDOG TIMER TEST REGISTERWDTTR (0x0009)7 0

7 0

SECONDARY WATCHDOG TIMER TIME CONSTANT DISABLED BY 0x5A - 0x52 - 0x44 TO THIS REGISTER

SECONDARY WATCHDOG TIMERSWDTR (0x000C)7 0

Watchdog Timer

External Interrupts

EXTERNAL INTERRUPT HOLD TIME MUST BE AT LEAST 3 PERIPHERAL CLOCK CYCLES

7

000 = INT0 DISABLED01 = INT0 PRIORITY 110 = INT0 PRIORITY 211 = INT0 PRIORITY 3

00 = DISABLE PD0 INTERRUPT01 = ENABLE PD0 FALLING EDGE 10 = ENABLE PD0 RISING EDGE 11 = ENABLE PD0 BOTH EDGES00 = DISABLE PE4 INTERRUPT01 = ENABLE PE4 FALLING EDGE 10 = ENABLE PE4 RISING EDGE 11 = ENABLE PE4 BOTH EDGES00 = DISABLE PE0 INTERRUPT01 = ENABLE PE0 FALLING EDGE 10 = ENABLE PE0 RISING EDGE 11 = ENABLE PE0 BOTH EDGES

INTERRUPT 0 CONTROL REGISTERI0CR (0x0098)

INTERRUPT 1 CONTROL REGISTERI1CR (0x0099)

7

000 = INT1 DISABLED01 = INT1 PRIORITY 110 = INT1 PRIORITY 211 = INT1 PRIORITY 3

00 = DISABLE PD1 INTERRUPT01 = ENABLE PD1 FALLING EDGE 10 = ENABLE PD1 RISING EDGE 11 = ENABLE PD1 BOTH EDGES00 = DISABLE PE5 INTERRUPT01 = ENABLE PE5 FALLING EDGE 10 = ENABLE PE5 RISING EDGE 11 = ENABLE PE5 BOTH EDGES00 = DISABLE PE1 INTERRUPT01 = ENABLE PE1 FALLING EDGE 10 = ENABLE PE1 RISING EDGE 11 = ENABLE PE1 BOTH EDGES

INTERRUPT 2-7 CONTROL REGISTERI2CR (0x009A) I3CR (0x009B)I4CR (0x009C) I5CR (0x009D)I6CR (0x009E) I7CR (0x009F)

0

70 = INT FROM PORT F

1 = INT FROM PORT G

INTERRUPT PIN ON PORT

00 = INTERRUPT DISABLED01 = INTERRUPT FALLING EDGE10 = INTERRUPT RISING EDGE11 = INTERRUPT BOTH EDGES

00 = INTERRUPT DISABLEDxx = INTERRUPT PRIORITY

Stack Limit ProtectionSTACK LIMIT CONTROL REGISTERSTKCR (0x0444)

07

0 = DISABLE STACK LIMIT CHECKING1 = ENABLE STACK LIMIT CHECKING

0 0 0 0 0 0 0

STACK LOW LIMIT REGISTERSTKLLR (0x445)

07

SET LOWER LIMIT FOR STACK LIMIT CHECKING

IF STACK ACCESS ATTEMPTED BELOW {STKLLR, 0x10} INTERRUPT OCCURS

STACK HIGH LIMIT REGISTERSTKHLR (0x0446)

07

SET UPPER LIMIT FOR STACK LIMIT CHECKING

IF STACK ACCESS ATTEMPTED ABOVE {STKHLR, 0x00EF} INTERRUPT OCCURS

Input Capture

INPUT CAPTURE CONTROL REGISTERICCR (0x0057)

7

0

0

0

0

0 00 = INPUT CAPTURE INTERRUPTS DISABLED

01 = PRIORITY 1 INTERRUPT10 = PRIORITY 2 INTERRUPT11 = PRIORITY 3 INTERRUPT

0 = IC2 CAPTURE OPERATION1 = IC2 COUNTER OPERATION0 = IC1 CAPTURE OPERATION1 = IC1 COUNTER OPERATION

RESERVEDMUST = 0

7

0

INPUT CAPTURE TRIGGER x REGISTERSICT1R (0x0058) — ICT2R (0x005C)

00 = COUNTER DISABLED01 = COUNT RUNS FROM START TO STOP10 = COUNT RUNS CONTINUOUSLY11 = COUNT RUNS UNTIL STOP00 = DISABLE COUNTER LATCH01 = LATCH COUNTER ON STOP10 = LATCH COUNTER ON START11 = LATCH COUNTER ON START OR STOP00 = IGNORE START INPUT01 = START AT START INPUT RISING EDGE10 = START AT START INPUT FALLING EDGE11 = START AT START INPUT EITHER EDGE00 = IGNORE STOP INPUT01 = STOP AT STOP INPUT RISING EDGE10 = STOP AT STOP INPUT FALLING EDGE11 = STOP AT STOP INPUT EITHER EDGE

INPUT CAPTURE SOURCE x REGISTERSICS1R (0x0059) — ICS2R (0x005D)

7

0

00 = PORT C01 = PORT D10 = PORT E11 = RESERVED

AS STARTCONDITIONS INPUT00 = BIT 1

01 = BIT 310 = BIT 511 = BIT 700 = PORT C01 = PORT D10 = PORT E11 = RESERVED00 = BIT 101 = BIT 310 = BIT 511 = BIT 7

AS STOPCONDITIONS INPUT

USE

USE

INPUT CAPTURE COUNTER REGISTERMSB — ICM1R (0x005B)

ICM2R (0x005F)

READ MSB (RE-OPENS LATCH)

7 0

LSB — ICL1R (0x005A)ICL2R (0x005E)

READ LSB (LATCHES MSB)

7 0

0 = IC1 START CONDITION NOT OCCURRED1 = IC1 START CONDITION OCCURRED

0 = IC2 START CONDITION NOT OCCURRED1 = IC2 START CONDITION OCURRED

0 = IC2 START INT. DISABLED1 = IC2 START INT. ENABLED

7

0

0 = IC2 STOP CONDITION NOT OCCURRED1 = IC2 STOP CONDITION OCCURRED

0 = IC1 STOP CONDITION NOT OCCURRED1 = IC1 STOP CONDITION OCCURRED

0 = IC2 NOT ROLLED OVER1 = IC2 ROLLED OVER

0 = IC1 NOT ROLLED OVER1 = IC1 ROLLED OVER

0 = IC1 START INT. DISABLED1 = IC1 START INT. ENABLED0 = IC1 STOP INT. DISABLED1 = IC1 STOP INT. ENABLED

0 = IC2 STOP INT. DISABLED1 = IC2 STOP INT. ENABLED

RESET IC2 COUNTER & ROLLOVER LATCH

RESET IC1 COUNTER & ROLLOVER LATCH0

0

INPUT CAPTURE CONTROL/STATUS REGISTERICCSR (0x0056)

CLE

AR

ED W

HEN

REA

D

RESERVEDMUST = 0

READ WRITE

(USES TIMER A8) Analog NOT ALL REGISTERS DISPLAYED; SEE PROCESSOR MANUAL FOR MORE DETAILS.

ADC COMMAND/STATUS REGISTERADCCSR (0x0543)

7

0

0

1 = START CONVERSION

01 = INTERNAL REFERENCE10 = EXTERNAL REFERENCE

CHANNEL FOR CONVERSION (0-7)

0

ADC LSB REGISTERADCLR (0x0540)

7

0

4 LSB OF CURRENT CHANNEL

0 = NO CONVERSION RUNNING1 = CONVERSION IN PROGRESS

0

0

0 = CONVERSION NOT COMPLETE1 = CONVERSION COMPLETE,

DATA READY

ADC MSB REGISTERADCMR (0x0541)

7

0

8 MSB OF CURRENT CHANNEL

ADC CONTROL REGISTERADCCR (0x0544)

0 = USE PERIPHERAL CLOCK1 = USE PD4 AS CLOCK INPUT000 = DIVIDE CLOCK BY 2001 = DIVIDE CLOCK BY 4010 = DIVIDE CLOCK BY 8011 = DIVIDE CLOCK BY 16100 = DIVIDE CLOCK BY 32101 = DIVIDE CLOCK BY 64110 = DIVIDE CLOCK BY 128111 = DIVIDE CLOCK BY 256

0 = ADC POWERED DOWN1 = ADC ACTIVE

7

0

0

00 = NO ADC INTERRUPTXX = INTERRUPT PRIORITY

Write Protect

7 015 8

WRITE PROTECT CONTROL REGISTERWPCR (0x0440)7 0

0 0 0 0 0 0 00 0 0

0 = ENABLE WRITE PROTECTION IN USER MODE ONLY1 = ENABLE WRITE PROTECTION IN ALL MODES

7 0

WRITE PROTECT LOW/HIGH REGISTERSWP0R (0x0460) – WP31R (0x047F)

0 = DISABLE WRITE PROTECT FOR 64 KB BLOCK1 = ENABLE WRITE PROTECT FOR 64 KB BLOCK

WRITE PROTECT SEGMENT HIGH/LOW REGISTERSWPSAHR (0x0482) WPSALR (0x0481) WPSBHR (0x0486) WPSBLR (0x0485)

0 = DISABLE WRITE PROTECT FOR 4 KB BLOCK1 = ENABLE WRITE PROTECT FOR 4 KB BLOCK

WRITE PROTECT SEGMENT REGISTERSWPSAR (0x0480) WPSBR (0x0484)

WHEN THESE MATCH PHYSICAL ADDRESS [23:16], SUBDIVIDE WRITE PROTECT FOR THAT 64 KB BLOCK INTO 4 KB BLOCKS

7 0

WPSxHR WPSxLR

Direct Memory Access

DMA TIMED REQUEST DIVIDER LOW REGISTERDTRDLR (0x0116)

LSB OF LIMIT VALUE FOR TIMER

07

DMA TIMED REQUEST DIVIDER HIGH REGISTERDTRDHR (0x0117)

MSB OF LIMIT VALUE FOR TIMER

815

DMA MASTER AUTO-LOAD REGISTERDMALLR (0x0110)DMALMR (0x0111)

0 = NO EFFECT1 = AUTO-LOAD CHANNEL

07

00 = REQUESTS DISABLED 01 = REQUEST ENABLED FROM PD2 10 = REQUEST ENABLED FROM PE2 11 = REQUEST ENABLED FROM PE6

REQUEST 0 TO THISDMA CHANNEL

00 = FALLING EDGE TRIGGERED (1 BYTE) 01 = RISING EDGE TRIGGERED (1 BYTE) 10 = ACTIVE LOW 11 = ACTIVE HIGH

DMA MASTER REQUEST 0 CONTROL REGISTERDMR0CR (0x0106)

7

0

00 = REQUESTS DISABLED01 = REQUEST ENABLED FROM PD310 = REQUEST ENABLED FROM PE311 = REQUEST ENABLED FROM PE7

00 = FALLING EDGE TRIGGERED (1 BYTE)01 = RISING EDGE TRIGGERED (1 BYTE)10 = ACTIVE LOW11 = ACTIVE HIGH

REQUEST 1 TO THISDMA CHANNEL

DMA MASTER REQUEST 1 CONTROL REGISTERDMR1CR (0X0107)

7

0

DMA y TERMINATION BYTE REGISTERD0TBR-D7TBR (0x01y8)D8TBR-D15TBR (0x09y8)

MATCH VALUE

07

DMA y TERMINATION MASK REGISTERD0TMR-D7TMR (0x01y9)D8TMR-D15TMR (0x09y9)

TERMINATION BYTE MASK

07

DMA MASTER CONTROL/STATUS REGISTERDMCSLR (0x0100) DMCSMR (0x0101)

WR 0 = NO EFFECTWR 1 = START/RESTART CHANNELRD 0 = CHANNEL DISABLEDRD 1 = CHANNEL ENABLED

07

DMA y BUFFER COMPLETE REGISTERD0BCR-D7BCR(0x01y3)D8BCR-D15BC(0x09y3)

WR = LOAD COUNTERRD = READ COUNTER

07

DMA y BUFFER UNUSED [7:0] REGISTERD0BU0R-D7BU0R (0x01yA)D8BU0R-D15BU0R (0x09yA)

DMA x BUFFER UNUSED [15:8] REGISTERD0BU1R-D7BU1R (0x01yB)D8BU1R-D15BU1R (0x09yB)

STORES BITS OF BUFFER UNUSED LENGTH VALUE

07

000 = MAX 1 BYTE BURST001 = MAX 2 BYTE BURST010 = MAX 3 BYTE BURST011 = MAX 4 BYTE BURST100 = MAX 8 BYTE BURST101 = MAX 16 BYTE BURST110 = MAX 32 BYTE BURST111 = MAX 64 BYTE BURST000 = MIN 12 CLOCKS BETWEEN BURSTS001 = MIN 16 CLOCKS BETWEEN BURSTS010 = MIN 24 CLOCKS BETWEEN BURSTS011 = MIN 32 CLOCKS BETWEEN BURSTS100 = MIN 64 CLOCKS BETWEEN BURSTS101 = MIN 128 CLOCKS BETWEEN BURSTS110 = MIN 256 CLOCKS BETWEEN BURSTS111 = MIN 512 CLOCKS BETWEEN BURSTS

0x = FIXED DMA CHANNEL PRIORITY10 = ROTATE PRIORITY AFTER EVERY BYTE11 = ROTATE PRIORITY AFTER EVERY

REQUEST

DMA MASTER TIMING CONTROL REGISTERDMTCR (0x0105)

7

0

0 = CONTINUE TO NEXT BUFFER DESCRIPTOR 1 = FINAL BUFFER DESCRIPTOR 0 = USE SEQUENTIAL ADDRESS 1 = USE LINK ADDRESS FIELD 0 = NORMAL 1 = SPECIAL LAST BYTE

00 = DESTINATION ADDRESS IS FIXED INTERNAL I/O ADDR01 = DESTINATION ADDRESS IS FIXED EXTERNAL I/O ADDR10 = DESTINATION ADDRESS IS MEMORY ADDR, AUTO DECREMENT11 = DESTINATION ADDRESS IS MEMORY ADDR, AUTO INCREMENT

00 = SOURCE ADDRESS IS FIXED INTERNAL I/O ADDRESS01 = SOURCE ADDRESS IS FIXED EXTERNAL I/O ADDRESS10 = SOURCE ADDRESS IS MEMORY ADDR, AUTO-DECREMENT11 = SOURCE ADDRESS IS MEMORY ADDR, AUTO-INCREMENT

0 = NO INTERRUPT ON COMPLETION 1 = INTERRUPT ON COMPLETION

DMA x CONTROL REGISTERD0CR (0x0181)

DMA DESCRIPTOR REGISTERADD MULTIPLE OF 0x10 FOR CHANNELS 1 THRU 7; ADD 0x800 FOR CHANNELS 8 THRU 15

D0CR (0x0181)

D0L0R (0x0182)

D0SA0R (0x0184)

D0DA0R (0x0188)

D0LA0R (0x0180)

7

0

DMA SOURCE ADDRESS

DMA DEST ADDRESS

DMA LINK ADDRESS

DMA LENGTH

23 16 15 8 7 0

(0x0184)(0x0185)(0x0186)

23 16 15 8

(0x0189)(0x018A)

23 16 15 8

(0x018D)(0x018E)

15 8

(0x183)

7 0

(0x182)

7 0

(0x181) SEE BIT SETTINGS BELOW

7 0

(0x188)

7 0

(0x18C)

DMA MASTER CONTROL REGISTERDMCR (0x0104)

00 = DISABLE INTERRUPT01 = PRIORITY 1 INTERRUPT10 = PRIORITY 2 INTERRUPT11 = PRIORITY 3 INTERRUPT

00 = PRIORITY 0 TRANSFER01 = PRIORITY 1 TRANSFER10 = PRIORITY 2 TRANSFER11 = PRIORITY 3 TRANSFER

07

0000

0 = TIMED REQUEST DISABLED 1 = TIMED REQUEST ENABLED

00 = 1 BYTE PER REQUEST 01 = (RESERVED) 10 = TRANSFER UNTIL BUFFER

DESCRIPTOR IS COMPLETE 11 = (RESERVED)

REQUEST TO THISDMA CHANNEL

7

0

0

DMA TIMED REQUEST CONTROL REGISTERDTRCR (0x0115)

0 = NO EFFECT1 = HALT CHANNEL

07

DMA MASTER HALT REGISTERDMHLR (0x0102)DMHMR (0x0121)

DMA SPECIAL CONTROL REGISTERD0SCR (0x0180) D1SCR (0x0190)D2SCR (0x01A0) D3SCR (0x01B0)D4SCR (0x01C0) D5SCR (0x01D0)D6SCR (0x01E0) D7SCR (0x01F0)

7

0

0

0 = NORMAL DEST ADDRESS1 = FIXED DEST ADDRESS

0 = AUTO-CONNECT DEST DMA REQUEST1 = DISCONNECT DEST DMA REQUEST

0 = NORMAL SOURCE ADDRESS1 = FIXED SOURCE ADDRESS

0 = AUTO-CONNECT SOURCE DMA REQUEST1 = DISCONNECT SOURCE DMA REQUEST

10 = ENABLE DMA FOR USB RX11 = ENABLE DMA FOR USB TX

0X = NORMAL DMA OPERATION

0 = AUTOMATIC SELECTION OF CYCLE-STEAL MODE1 = DISABLE CYCLE-STEAL MODE

0x = FIXED DMA CHANNEL PRIORITY10 = ROTATE PRIORITY AFTER EVERY BYTE11 = ROTATE PRIORITY AFTER EVERY REQUEST

000 = MAX 1 BYTE BURST001 = MAX 2 BYTE BURST010 = MAX 3 BYTE BURST011 = MAX 4 BYTE BURST100 = MAX 8 BYTE BURST101 = MAX 16 BYTE BURST110 = MAX 32 BYTE BURST111 = MAX 64 BYTE BURST

DMA CYCLE-STEAL TIMING CONTROL REGISTERDCSTCR (0x0125)

7

0

0

0

0

NOT ALL REGISTERS DISPLAYED; SEE PROCESSOR MANUAL FOR MORE DETAILS.

Network Ports NOT ALL REGISTERS DISPLAYED; SEE PROCESSOR MANUAL FOR MORE DETAILS.

NETWORK PORT C CPU WAIT REGISTERNCCWR (0x0431)

ONES COMPLIMENT OF WIFI CPUWAIT STATES (0-31)

07

0 0

NETWORK PORT C DMA WAIT REGISTERNCDWR (0x0432)

ONES COMPLIMENT OF WIFI DMAWAIT STATES (0-31)

07

0 0

NETWORK PORT D WAIT REGISTERNDDWR (0x0433)

ONES COMPLIMENT OF USBWAIT STATES (0-31)

07

0 0

USB WRAPPER REGISTERUSBWR (0x1060)

7

0

0

0

0

0 = DISABLE USB OVERCURRENT SIGNAL1 = ENABLE USB OVERCURRENT SIGNAL ON PE3

0 = DISABLE D- PULLDOWN1 = DISABLE D- PULLDOWN

0

0 = DISABLE D+ PULLDOWN1 = ENABLE D+ PULLDOWN

0

ENABLE NETWORK PORT REGISTERENPR (0x0430)

7

0

0

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00 = USB INTERRUPT DISABLEDXX = USB INTERRUPT PRIORITY

0 = DISABLE USB HOST1 = ENABLE USB HOST

0 = DISABLE ETHERNET1 = ENABLE ETHERNET

0 = DISABLE WIFI1 = ENABLE WIFI

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