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Progress report from ALICE ITS3 WP3-4-5
Giacomo ContinUniversità di Trieste and INFN Sezione di Trieste
EIC Silicon Consortium meeting – July 26th 2021
Main ongoing activities within ITS3 WP3-4-5
• MLR1 Testing campaign plans• ALPIDE-based DUT Testbeams• Larger-size chip Thinning,
Bending and Interconnections• Mechanics development
2021-07-26 ITS3 Update @ EICSC - [email protected] 2
MLR1 testing plans• Test system components under production
• First batch of boards ready between now and end of August• Firmware/software being finalized
• MLR1 wafers ready• Dicing is ongoing• Picking will follow• Wire-bonding of samples planned
• Process under study on pad wafers• Chip distribution is under discussion
• First samples to institutes involved in silicon and test system design• After first feedback, larger distribution of samples
• Plans:• Start MLR1 lab testing as soon as chips and test systems are available• Irradiation of MLR1 chips • Beam test of MLR1:
• 18 Oct - 6 Nov @ PS• 10 - 15 November @ SPS• 29 Nov - 6 Dec @ DESY
2021-07-26 ITS3 Update @ EICSC - [email protected] 3
Bent MLR1 testing plans
2021-07-26 ITS3 Update @ EICSC - [email protected] 4
Original single TS carrier
Large chip including multiple TSs
Wire bonding 1• Surface mounted curved base• Board traces re-routed• Long wires
Wire bonding 2• Curved base underneath board• Shorter wires
SpTAB bonding• Surfaced mounted curved base• Microcable re-routing the lines
Bend and characterize test structures• Bend a large area (3.2 x 2.4 cm2) chip• Adhesive tape and/or kapton layer• Detailed curvature measurement of 1.5 x 1.5 mm2 TS
Bent ALPIDE-based DUT testbeams
23-07-2021
PreliminaryFrancesca Carnesecchi,Lukas Lautner,Manuel ColocciWP3 @ ITS3 Plenary
WP3 meeting – Sergey Senyukov
2021-07-26 5ITS3 Update @ EICSC - [email protected]
SPS July 2021
6
µITS with 6 chipsµITS with 6 chips+ Cu target
Chip tested in Dec 2020 new orientation
W-shaped chipFlat chip
WP3 meeting – Sergey Senyukov
2021-07-26 ITS3 Update @ EICSC - [email protected]
Large-size chip bending and interconnectionsALPIDE Super-chips• Idea: cut out large “super chips” from a wafer• about the area of 1/2 ITS3 half-layer 0
• ~140 x 60 mm• 9 x 2 chips
• 9 interconnection areas in z-direction• need individual connections:
• no interconnections on wafer-level• SpTAB or wire-bonding
2021-07-26 ITS3 Update @ EICSC - [email protected] 7
• Dummy-super-ALPIDE (using mini-pad)• Exoskeleton• Exo-FPC• Wire-bonding
2021-07-26 ITS3 Update @ EICSC - [email protected] 8
Super-ALPIDE mock-up assembly
ITS3 WP4 meeting - Domenico Colella
Super-ALPIDE mock-up assemblyR&D on:• Handling and bending large area chip• Gluing procedure FPC on exoskeleton• Wire-bonding in complex and curved geometry
2021-07-26 ITS3 Update @ EICSC - [email protected] 9
ITS3 WP4 meeting - Domenico Colella
Super-ALPIDE Edge-FPC• First prototype of the final front-edge ITS3 interconnections – in production
2021-07-26 ITS3 Update @ EICSC - [email protected] 10
ITS3 WP4 meeting - Domenico Colella
ALICE ITS3 WP5Super-ALPIDE: MuLtiPourpose JIG design compatibility
CAD scheme with super-ALPIDE chip
138.2mm
Super-ALPIDE
S-Alpide : jig for bending/ foam gluing/ wire bonding…compatibility
FPC (temporary approach)
@INFN BARI
DESIGN provided by INFN Bari:Compatibility verified
Full size jig design developed Reduced size jig (S-Alpide) on going
Jig production next
with Bending and Foam gluing
11
ITS3 WP5 meeting – Massimo Angeletti
2021-07-26 ITS3 Update @ EICSC - [email protected]
ALICE ITS3 WP5EM1: Chip held in position by Kapton mask
Carbon foam
Impregnated fleece Siliconkapton
HLS equipped with edge Kapton tape that after bending hold the chip in position 12
ITS3 WP5 meeting – Massimo Angeletti
2021-07-26 ITS3 Update @ EICSC - [email protected]
ALICE ITS3 WP5MultiPurpose JIG , Full size Design HOLDING IN POSITION
Kapton tape
Or vacuum mandrel
JIG design for full size chip 13
ITS3 WP5 meeting – Massimo Angeletti
chip
mylar foil
2021-07-26 ITS3 Update @ EICSC - [email protected]
ALICE ITS3 WP5
HLS Full scale mandrels in productionAssembly EM2 (Silicon) and Super-ALPIDEAim EM2: Verify the obtained assembly precision using mandrels and carbon foam supports with quality similar to the final ones
EM2: Chip held in position by Kapton mask
14
Large bending test with Kapton
Carbon foam
Impregnated fleece
SiliconKapton
3-4mm
D 40mm
@CERN, P. Ijzermans
Silicon 40 µm
ITS3 WP5 meeting – Massimo Angeletti
2021-07-26 ITS3 Update @ EICSC - [email protected]
Plans for the upcoming weeks
• Testing and characterization• Continue analysis of bent ALPIDEs beam test. Paper in preparation.• Start MLR1 testing in lab and beam
• Thinning, bending and interconnections• Super-ALPIDE wire-bonding: exoskeleton and edge-FPC• SpTAB bonding• Mechanical characterization of bent structures
• Mechanics• FOAM/glue characterization• Vacuum mandrel development
2021-07-26 ITS3 Update @ EICSC - [email protected] 15
Backup
2021-07-26 ITS3 Update @ EICSC - [email protected] 16
17
ALPIDE chips and superchips testing
~1 year toprepare the next
test system
<6 months forMLR1 test system
~2 years for the “final” test system
MLR1testing ER1 testing
Full-scale chip testing Final chip testing
* Testing periods are approximate
ITS3 project timeline: testing
2021-07-26 ITS3 Update @ EICSC - [email protected]