Precision Rail-to-Rail Input and Output Operational ... · Precision Rail-to-Rail Input and Output Operational Amplifiers OP184/OP284/OP484 Rev. J Information furnished by Analog

Precision Rail-to-Rail Input and Output Operational Amplifiers

OP184/OP284/OP484

Rev. J Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©1996–2011 Analog Devices, Inc. All rights reserved.

FEATURES Single-supply operation Wide bandwidth: 4 MHz Low offset voltage: 65 μV Unity-gain stable High slew rate: 4.0 V/ μs Low noise: 3.9 nV/√Hz

APPLICATIONS Battery-powered instrumentation Power supply control and protection Telecommunications DAC output amplifier ADC input buffer

GENERAL DESCRIPTION The OP184/OP284/OP484 are single, dual, and quad single-supply, 4 MHz bandwidth amplifiers featuring rail-to-rail inputs and outputs. They are guaranteed to operate from 3 V to 36 V (or ±1.5 V to ±18 V).

These amplifiers are superb for single-supply applications requiring both ac and precision dc performance. The combination of wide bandwidth, low noise, and precision makes the OP184/OP284/ OP484 useful in a wide variety of applications, including filters and instrumentation.

Other applications for these amplifiers include portable telecom-munications equipment, power supply control and protection, and use as amplifiers or buffers for transducers with wide output ranges. Sensors requiring a rail-to-rail input amplifier include Hall effect, piezoelectric, and resistive transducers.

The ability to swing rail-to-rail at both the input and output enables designers to build multistage filters in single-supply systems and to maintain high signal-to-noise ratios.

The OP184/OP284/OP484 are specified over the hot extended industrial temperature range of −40°C to +125°C. The single OP184 is available in 8-lead SOIC surface mount packages. The dual OP284 is available in 8-lead PDIP and SOIC surface mount packages. The quad OP484 is available in 14-lead PDIP and 14-lead, narrow-body SOIC packages.

PIN CONFIGURATIONS

1

2

3

4

OUT A

V+

DNC

NCDNC

–IN A

+IN A

V–

8

7

6

5

NOTES1. NC = NO CONNECT2. DNC = DO NOT CONNECT

–

+

0029

3-00

1

TOP VIEW(Not to Scale)

OP184

Figure 1. 8-Lead SOIC (S-Suffix)

0029

3-00

2

1

2

3

4

8

7

6

5

OUT B

–IN B

+IN B

V+OUT A

–IN A

+IN A

V–

OP284

TOP VIEW(Not to Scale)

Figure 2. 8-Lead PDIP (P-Suffix)

8-Lead SOIC (S-Suffix)

14

13

12

11

10

9

8

1

2

3

4

5

6

7

OUT A

–IN A

+IN A

V+

+IN B

–IN B

OUT B

OUT D

–IN D

+IN D

V–

+IN C

–IN C

OUT C

OP484TOP VIEW

(Not to Scale)

0029

3-00

3

Figure 3. 14-Lead PDIP (P-Suffix)

14-Lead Narrow-Body SOIC (S-Suffix)

Table 1. Low Noise Op Amps Voltage Noise 0.9 nV 1.1 nV 1.8 nV 2.8 nV 3.2 nV 3.8 nV 3.9 nV Single AD797 AD8597 ADA4004-1 AD8675/ADA4075-2 OP27 AD8671 OP184 Dual AD8599 ADA4004-2 AD8676 OP270 AD8672 OP284 Quad ADA4004-4 OP470 AD8674 OP484

http://www.analog.com/

http://www.analog.com/OP184









http://www.analog.com/AD797


http://www.analog.com/ADA4004-1
















OP184/OP284/OP484

Rev. J | Page 2 of 24

TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Pin Configurations ........................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3

Electrical Characteristics ............................................................. 3 Absolute Maximum Ratings ............................................................ 6

Thermal Resistance ...................................................................... 6 ESD Caution .................................................................................. 6

Typical Performance Characteristics ............................................. 7 Applications Information .............................................................. 14

Functional Description .............................................................. 14 Input Overvoltage Protection ................................................... 14

Output Phase Reversal ............................................................... 15 Designing Low Noise Circuits in Single-Supply Applications....................................................................................................... 15 Overdrive Recovery ................................................................... 16 Single-Supply, 3 V Instrumentation Amplifier ...................... 16 2.5 V Reference from a 3 V Supply .......................................... 17 5 V Only, 12-Bit DAC Swings Rail-to-Rail ............................. 17 High-Side Current Monitor ...................................................... 18 Capacitive Load Drive Capability ............................................ 18 Low Dropout Regulator with Current Limiting ..................... 19 3 V, 50 Hz/60 Hz Active Notch Filter with False Ground ..... 20

Outline Dimensions ....................................................................... 21 Ordering Guide .......................................................................... 23

REVISION HISTORY 4/11—Rev. I to Rev J Change to Figure 27 ....................................................................... 10 10/10—Rev. H to Rev I Change to Output Characteristics, Output Voltage High Parameter, Table 2 ............................................................................. 3 Change to Output Characteristics, Output Voltage High Parameter, Table 3 ............................................................................. 4 7/10—Rev. G to Rev. H Added Table 1 .................................................................................... 1 2/09—Rev. F to Rev. G Change to Large Signal Voltage Gain, Table 3 .............................. 5 Updated Outline Dimensions ....................................................... 21 Changes to Ordering Guide .......................................................... 22

9/08—Rev. E to Rev. F

Changes to General Description .................................................... 1 Changes to Figure 4 .......................................................................... 6 Changes to Low Dropout Regulator with Current Limiting .... 20

7/08—Rev. D to Rev. E

Changes to Figure 1 .......................................................................... 1 Changes to Figure 12 ........................................................................ 8 Changes to Figure 36 and Figure 37 ............................................. 12 Changes to Designing Low Noise Circuits in Single-Supply Applications Section ....................................................................... 15 Updated Outline Dimensions ....................................................... 21 Changes to Ordering Guide .......................................................... 22

4/06—Rev. C to Rev. D

Changes to Table 1 ............................................................................. 3 Changes to Table 2 ............................................................................. 4 Changes to Table 3 ............................................................................. 5 Deleted Reference to 1993 System Applications Guide .............. 15

3/06—Rev. B to Rev. C

Changes to Figure 1 Caption............................................................ 1 Changes to Table 1 ............................................................................. 3 Changes to Table 2 ............................................................................. 4 Changes to Table 3 ............................................................................. 5 Changes to Table 4 ............................................................................. 6 Changes to Figure 5 through Figure 9 ............................................ 7 Changes to Functional Description Section ............................... 14 Deleted SPICE Macro Model ........................................................ 21 Updated Outline Dimensions ....................................................... 21 Changes to Ordering Guide .......................................................... 22

9/02—Rev. A to Rev. B

Changes to Pin Configurations ....................................................... 1 Changes to Specifications, Input Bias Current Maximum .......... 2 Changes to Ordering Guide ............................................................. 5 Updated Outline Dimensions ....................................................... 19

6/02—Rev. 0 to Rev. A

10/96—Revision 0: Initial Version

OP184/OP284/OP484


SPECIFICATIONS ELECTRICAL CHARACTERISTICS VS = 5.0 V, VCM = 2.5 V, TA = 25°C, unless otherwise noted.

Table 2. Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS

Offset Voltage, OP184/OP284E Grade1 VOS 65 μV −40°C ≤ TA ≤ +125°C 165 μV Offset Voltage, OP184/OP284F Grade1 VOS 125 μV −40°C ≤ TA ≤ +125°C 350 μV Offset Voltage, OP484E Grade1 VOS 75 μV –40°C ≤ TA ≤ +125°C 175 μV Offset Voltage, OP484F Grade1 VOS 150 μV –40°C ≤ TA ≤ +125°C 450 μV Input Bias Current IB 60 450 nA –40°C ≤ TA ≤ +125°C 600 nA Input Offset Current IOS 2 50 nA –40°C ≤ TA ≤ +125°C 50 nA Input Voltage Range 0 5 V Common-Mode Rejection Ratio CMRR VCM = 0 V to 5 V 60 dB VCM = 1.0 V to 4.0 V, −40°C ≤ TA ≤ +125°C 86 dB Large Signal Voltage Gain AVO RL = 2 kΩ, 1 V ≤ VO ≤ 4 V 50 240 V/mV RL = 2 kΩ, −40°C ≤ TA ≤ +125°C 25 V/mV Bias Current Drift ΔIB/ΔT 150 pA/°C

OUTPUT CHARACTERISTICS Output Voltage High VOH IL = 1.0 mA 4.80 V Output Voltage Low VOL IL = 1.0 mA 125 mV Output Current IOUT ±6.5 mA

POWER SUPPLY Power Supply Rejection Ratio PSRR VS = 2.0 V to 10 V, −40°C ≤ TA ≤ +125°C 76 dB Supply Current/Amplifier ISY VO = 2.5 V, −40°C ≤ TA ≤ +125°C 1.45 mA Supply Voltage Range VS 3 36 V

DYNAMIC PERFORMANCE Slew Rate SR RL = 2 kΩ 1.65 2.4 V/µs Settling Time tS To 0.01%, 1.0 V step 2.5 µs Gain Bandwidth Product GBP 3.25 MHz Phase Margin ΦM 45 Degrees

NOISE PERFORMANCE Voltage Noise en p-p 0.1 Hz to 10 Hz 0.3 μV p-p Voltage Noise Density en f = 1 kHz 3.9 nV/√Hz Current Noise Density in 0.4 pA/√Hz

1 Input offset voltage measurements are performed by automated test equipment approximately 0.5 seconds after application of power.

OP184/OP284/OP484


VS = 3.0 V, VCM = 1.5 V, TA = 25°C, unless otherwise noted.


Offset Voltage, OP184/OP284E Grade1 VOS 65 μV −40°C ≤ TA ≤ +125°C 165 μV Offset Voltage, OP184/OP284F Grade1 VOS 125 μV −40°C ≤ TA ≤ +125°C 350 μV Offset Voltage, OP484E Grade1 VOS 100 μV –40°C ≤ TA ≤ +125°C 200 μV Offset Voltage, OP484F Grade1 VOS 150 μV –40°C ≤ TA ≤ +125°C 450 μV Input Bias Current IB 60 450 nA −40°C ≤ TA ≤ +125°C 600 nA Input Offset Current IOS −40°C ≤ TA ≤ +125°C 50 nA Input Voltage Range 0 3 V Common-Mode Rejection Ratio CMRR VCM = 0 V to 3 V 60 dB VCM = 0 V to 3 V, −40°C ≤ TA ≤ +125°C 56 dB

OUTPUT CHARACTERISTICS Output Voltage High VOH IL = 1.0 mA 2.80 V Output Voltage Low VOL IL = 1.0 mA 125 mV

POWER SUPPLY Power Supply Rejection Ratio PSRR VS = ±1.25 V to ±1.75 V 76 dB Supply Current/Amplifier ISY VO = 1.5 V, −40°C ≤ TA ≤ +125°C 1.35 mA

DYNAMIC PERFORMANCE Gain Bandwidth Product GBP 3 MHz

NOISE PERFORMANCE Voltage Noise Density en f = 1 kHz 3.9 nV/√Hz


OP184/OP284/OP484


VS = ±15.0 V, VCM = 0 V, TA = 25°C, unless otherwise noted.


Offset Voltage, OP184/OP284E Grade1 VOS 100 μV −40°C ≤ TA ≤ +125°C 200 μV Offset Voltage, OP184/OP284F Grade1 VOS 175 μV −40°C ≤ TA ≤ +125°C 375 μV Offset Voltage, OP484E Grade1 VOS 150 μV −40°C ≤ TA ≤ +125°C 300 μV Offset Voltage, OP484F Grade1 VOS 250 μV −40°C ≤ TA ≤ +125°C 500 μV Input Bias Current IB 80 450 nA −40°C ≤ TA ≤ +125°C 575 nA Input Offset Current IOS −40°C ≤ TA ≤ +125°C 50 nA Input Voltage Range −15 +15 V Common-Mode Rejection Ratio CMRR VCM = −14.0 V to +14.0 V, −40°C ≤ TA ≤ +125°C 86 90 dB VCM = −15.0 V to +15.0 V 80 dB Large Signal Voltage Gain AVO RL = 2 kΩ, −10 V ≤ VO ≤ 10 V 150 1000 V/mV

RL = 2 kΩ, −40°C ≤ TA ≤ +125°C 75 V/mV Offset Voltage Drift E Grade ΔVOS/ΔT 0.2 2.00 μV/°C Bias Current Drift ΔVB/ΔT 150 pA/°C

OUTPUT CHARACTERISTICS Output Voltage High VOH IL = 1.0 mA 14.8 V Output Voltage Low VOL IL = 1.0 mA −14.875 V Output Current IOUT ±10 mA

POWER SUPPLY Power Supply Rejection Ratio PSRR VS = ±2.0 V to ±18 V, −40°C ≤ TA ≤ +125°C 90 dB Supply Current/Amplifier ISY VO = 0 V, −40°C ≤ TA ≤ +125°C 2.0 mA Supply Current/Amplifier ISY VS = ±18 V, −40°C ≤ TA ≤ +125°C 2.25 mA

DYNAMIC PERFORMANCE Slew Rate SR RL = 2 kΩ 2.4 4.0 V/µs Full-Power Bandwidth BWp 1% distortion, RL = 2 kΩ, VO = 29 V p-p 35 kHz Settling Time tS To 0.01%, 10 V step 4 µs Gain Bandwidth Product GBP 4.25 MHz Phase Margin ΦM 50 Degrees

NOISE PERFORMANCE Voltage Noise en p-p 0.1 Hz to 10 Hz 0.3 µV p-p Voltage Noise Density en f = 1 kHz 3.9 nV/√Hz Current Noise Density in 0.4 pA/√Hz


OP184/OP284/OP484


ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Rating Supply Voltage ±18 V Input Voltage ±18 V Differential Input Voltage1 ±0.6 V Output Short-Circuit Duration to GND Indefinite Storage Temperature Range

P-Suffix, S-Suffix Packages −65°C to +150°C Operating Temperature Range

OP184/OP284/OP484E/OP484F −40°C to +125°C Junction Temperature Range

P-Suffix, S-Suffix Packages −65°C to +150°C Lead Temperature

(Soldering 60 sec) 300°C

1 For input voltages greater than 0.6 V, the input current should be limited to less than 5 mA to prevent degradation or destruction of the input devices.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Absolute maximum ratings apply to both DICE and packaged parts, unless otherwise noted.

THERMAL RESISTANCE θJA is specified for the worst-case conditions; that is, θJA is specified for a device in socket for PDIP. θJA is specified for a device soldered in the circuit board for SOIC packages.

Table 6. Thermal Resistance Package Type θJA θJC Unit 8-Lead PDIP (P-Suffix) 103 43 °C/W 8-Lead SOIC (S-Suffix) 158 43 °C/W 14-Lead PDIP (P-Suffix) 83 39 °C/W 14-Lead SOIC (S-Suffix) 92 27 °C/W

ESD CAUTION

R3

Q1

–IN +IN

QL1

QL2

Q4Q3 Q2

QB5QB6

RB2QB3

R1

Q5

R2

QB4

JB2

QB1

N+CB1

P+M

QB2

CC1

Q9

Q7

Q11Q8

Q6

Q10

Q12

QB7QB8

QB9

RB1

JB1

TP

R4

R5

R6

RB3

FFC

R7

R8

Q13 Q14

R10

Q15

RB4

QB10CC2

C O

Q17Q16

R11

Q18

VCC

OUT

VEE

R9

0029

3-00

4

Figure 4. Simplified Schematic

OP184/OP284/OP484


TYPICAL PERFORMANCE CHARACTERISTICS

INPUT OFFSET VOLTAGE (µV)

QU

AN

TITY

300

0

270

180

90

60

30

240

210

120

150

–100 –75 –50 –25 0 25 50 75 100

0029

3-00

5

VS = 3VTA = 25°CVCM = 1.5V

Figure 5. Input Offset Voltage Distribution 00

293-

006


QU

AN

TITY

300

0

270

180

90

60

30

240

210

120

150

–100 –75 –50 –25 0 25 50 75 100

VS = 5VTA = 25°CVCM = 2.5V

Figure 6. Input Offset Voltage Distribution

0029

3-00

7


QU

AN

TITY

200

0

175

100

75

50

25

150

125

–125 –100 –75 –50 –25 0 25 10050 75 125

VS = ±15VTA = 25°C

Figure 7. Input Offset Voltage Distribution

300

250

200

150

100

50

00 0.25 0.50 0.75 1.00 1.25 1.50

QU

AN

TITY

OFFSET VOLTAGE DRIFT, TCVOS (µV/°C)

0029

3-00

8

VS = 5V–40°C ≤ TA ≤ +125°C

Figure 8. Input Offset Voltage Drift Distribution

300

250

200

150

100

50

00 0.25 0.50 0.75 1.00 1.25 1.50

QU

AN

TITY

OFFSET VOLTAGE DRIFT, TCVOS (µV/°C)

0029

3-00

9

VS = ±15V–40°C ≤ TA ≤ +125°C

Figure 9. Input Offset Voltage Drift Distribution

–40

–45

–50

–55

–60

–65

–70

–75

–80–40 25 85 125

VCM = VS/2

VS = +5V

VS = ±15V

INPU

T B

IAS

CU

RR

ENT

(nA

)

TEMPERATURE (°C)

0029

3-01

0

Figure 10. Bias Current vs. Temperature

OP184/OP284/OP484


500

–500

–400

–300

–200

–100

0

100

200

300

400

–15 –10 –5 0 5 10 15

INPU

T B

IAS

CU

RR

ENT

(nA

)

COMMON-MODE VOLTAGE (V)

0029

3-01

1

VS = ±15V

Figure 11. Input Bias Current vs. Common-Mode Voltage

1000

10

100

0.01 0.1 1 10

OU

TPU

T VO

LTA

GE

(mV)

LOAD CURRENT (mA)

0029

3-01

2

SOURCE

SINK

VS = ±15V

Figure 12. Output Voltage to Supply Rail vs. Load Current

1.2

1.1

1.0

0.9

0.8

0.7

0.6

0.5–40 25 85 125

SUPP

LY C

UR

REN

T/A

MPL

IFIE

R (m

A)

TEMPERATURE (°C)

0029

3-01

3

VS = ±15V

VS = +5V

VS = +3V

Figure 13. Supply Current vs. Temperature

1.50

1.25

1.00

0.75

0.50

0.25

00 ±2.5 ±5.0 ±7.5 ±10.0 ±12.5 ±15.0 ±17.5 ±20.0

SUPP

LY C

UR

REN

T/PE

R A

MPL

IFIE

R (m

A)

SUPPLY VOLTAGE (V)

0029

3-01

4

TA = 25°C

Figure 14. Supply Current vs. Supply Voltage

50

40

30

20

10

0–50 –25 0 25 50 75 100 125

SHO

RT-

CIR

CU

IT C

UR

REN

T (m

A)

TEMPERATURE (°C)

0029

3-01

5

VS = ±15V

+ISC

–ISC

+ISC

–ISC

VS = +5V, VCM = +2.5V

Figure 15. Short-Circuit Current vs. Temperature

70

60

50

40

30

20

10

0

–10

–20

–30

0

45

90

135

180

225

270

10k 100k 1M 10M

OPE

N-L

OO

P G

AIN

(dB

)

PHA

SE S

HIF

T (D

egre

es)

FREQUENCY (Hz)

0029

3-01

6

VS = 5VTA = 25°CNO LOAD

Figure 16. Open-Loop Gain and Phase vs. Frequency (No Load)

OP184/OP284/OP484


70

60

50

40

30

20

10

0

–10

–20

–30

0

45

90

135

180

225

270

10k 100k 1M 10M

OPE

N-L

OO

P G

AIN

(dB

)

PHA

SE S

HIF

T (D

egre

es)

FREQUENCY (Hz)

0029

3-01

7

VS = 3VTA = 25°CNO LOAD


70

60

50

40

30

20

10

0

–10

–20

–30

0

45

90

135

180

225

270

10k 100k 1M 10M

OPE

N-L

OO

P G

AIN

(dB

)

PHA

SE S

HIF

T (D

egre

es)

FREQUENCY (Hz)

0029

3-01

8

VS = ±15VTA = 25°CNO LOAD


2500

2000

1500

1000

500

0–50 1251007550250–25

OPE

N-L

OO

P G

AIN

(V/m

V)

TEMPERATURE (°C)

0029

3-01

9

VS = ±15V–10V < VO < +10VRL = 2kΩ

VS = +5V+1V < VO < +10VRL = 2kΩ

Figure 19. Open-Loop Gain vs. Temperature

60

50

40

30

20

10

0

–10

–20

–40

–30

10 1k 100k 10M100 10k 1M

CLO

SED

-LO

OP

GA

IN (d

B)

FREQUENCY (Hz)

0029

3-02

0

VS = 5VRL = 2kΩTA = 25°C

Figure 20. Closed-Loop Gain vs. Frequency (2 kΩ Load)

60

50

40

30

20

10

0

–10

–20

–40

–30

10 1k 100k 10M100 10k 1M

CLO

SED

-LO

OP

GA

IN (d

B)

FREQUENCY (Hz)

0029

3-02

0

VS = ±15VRL = 2kΩTA = 25°C


60

50

40

30

20

10

0

–10

–20

–40

–30

10 1k 100k 10M100 10k 1M

CLO

SED

-LO

OP

GA

IN (d

B)

FREQUENCY (Hz)

0029

3-02

0

VS = 3VRL = 2kΩTA = 25°C


OP184/OP284/OP484


300

270

240

210

180

150

120

90

60

0

30

10 1k 100k 10M100 10k 1M

OU

TPU

T IM

PED

AN

CE

(Ω)

FREQUENCY (Hz)

0029

3-02

3

VS = 5VTA = 25°C

AV = +100

AV = +10

AV = +1

Figure 23. Output Impedance vs. Frequency

300

270

240

210

180

150

120

90

60

0

30

10 1k 100k 10M100 10k 1M

OU

TPU

T IM

PED

AN

CE

(Ω)

FREQUENCY (Hz)

0029

3-02

4

VS = 15VTA = 25°C

AV = +100 AV = +10

AV = +1


300

270

240

210

180

150

120

90

60

0

30

10 1k 100k 10M100 10k 1M

OU

TPU

T IM

PED

AN

CE

(Ω)

FREQUENCY (Hz)

0029

3-02

5

VS = 3VTA = 25°C

AV = +100

AV = +10

AV = +1


5

4

3

2

1

01k 100k 10M10k 1M

MA

XIM

UM

OU

TPU

T SW

ING

(V p

-p)

FREQUENCY (Hz)

0029

3-02

6

VS = 5VVIN = 0.5V TO 4.5VRL = 2kΩTA = 25°C

Figure 26. Maximum Output Swing vs. Frequency

30

25

20

15

10

5

01k 100k 10M10k 1M

VOU

T (V

)

FREQUENCY (Hz) 0029

3-02

7

VS = ±15VVIN = ±14VRL = 2kΩTA = 25°C

Figure 27. Maximum Output Swing vs. Frequency

180

160

140

120

100

80

60

40

20

0

–2010 100k 10M1k100 10k 1M

CM

RR

(dB

)

FREQUENCY (Hz)

0029

3-02

8

VS = ±15V

VS = +5V

VS = +3V

TA = 25°C

Figure 28. CMRR vs. Frequency

OP184/OP284/OP484


160

140

120

100

80

60

40

20

0

–40

–20

10 100k 10M1k100 10k 1M

PSR

R (d

B)

FREQUENCY (Hz)

0029

3-02

9

VS = ±15V

VS = +5V

VS = +3V

TA = 25°C

Figure 29. PSRR vs. Frequency

80

70

60

50

40

30

20

10

010 1000100

OVE

RSH

OO

T (%

)

CAPACITIVE LOAD (pF)

0029

3-03

0

+OS

–OS

VS = ±2.5VTA = 25°C, AVCL = 1VIN = ±50mV

Figure 30. Small Signal Overshoot vs. Capacitive Load

7

6

5

4

3

2

1

0–50 –25 0 25 50 75 100 125

SLEW

RA

TE (V

/µs)

TEMPERATURE (°C)

0029

3-03

1

VS = ±15VRL = 2kΩ

VS = ±5VRL = 2kΩ

+SLEW RATE

–SLEW RATE

+SLEW RATE

–SLEW RATE

Figure 31. Slew Rate vs. Temperature

30

25

20

15

10

5

01 10 100 1000

NO

ISE

DEN

SITY

(nV/

Hz)

FREQUENCY (Hz)

0029

3-03

2

±2.5V ≤ VS ≤ ±15VTA = 25°C

Figure 32. Voltage Noise Density vs. Frequency

10

8

6

4

2

01 10 100 1000

CU

RR

ENT

NO

ISE

DEN

SITY

(pA

/ H

z)

FREQUENCY (Hz)

0029

3-03

3

±2.5V ≤ VS ≤ ±15VTA = 25°C

Figure 33. Current Noise Density vs. Frequency

5

4

3

2

1

–5

–4

–3

–2

–1

0

0 654321

STEP

SIZ

E (V

)

SETTLING TIME (µs)

0029

3-03

4

VS = 5VTA = 25°C

0.1% 0.01%

Figure 34. Step Size vs. Settling Time

OP184/OP284/OP484


10

8

6

4

2

–10

–8

–6

–4

–2

0

0 654321

STEP

SIZ

E (V

)

SETTLING TIME (µs)

0029

3-03

5

VS = ±15VTA = 25°C

0.1% 0.01%

Figure 35. Step Size vs. Settling Time

0.3

0.2

0.1

0

–0.1

–0.2

–0.3–5 –4 –3 –2 –1 0 1 2 3 4 5

TIME

NO

ISE

(µV)

0029

3-03

6

VS = ±2.5VAV = 10M

Figure 36. 0.1 Hz to 10 Hz Noise

0.3

0.2

0.1

0

–0.1

–0.2

–0.3–5 –4 –3 –2 –1 0 1 2 3 4 5

TIME

NO

ISE

(µV)

0029

3-03

7

VS = ±15VAV = 10M

Figure 37. 0.1 Hz to 10 Hz Noise

160

140

120

100

80

–40

–20

0

20

40

60

100 10M1M100k10k1k

CH

AN

NEL

SEP

AR

ATI

ON

(dB

)

FREQUENCY (Hz)

0029

3-03

8

TA = 25°C

VS = ±15V

VS = +3V

Figure 38. Channel Separation vs. Frequency

0029

3-03

9

VS = 5VAV = +1RL = OPENCL = 300pFTA = 25°C

1µs

100

90

10

0%

100mV

400mV

0V

Figure 39. Small Signal Transient Response

0029

3-04

0

VS = 5VAV = +1RL = 2kΩCL = 300pFTA = 25°C

1µs

100

90

10

0%

100mV

400mV

0V


OP184/OP284/OP484


0029

3-04

1

VS = ±1.5VAV = +1NO LOADTA = 25°C

500ns

100

90

10

0%

100mV

+200mV

0V

–200mV


0029

3-04

2

VS = ±0.75VAV = +1NO LOADTA = 25°C

1µs

100

90

10

0%

100mV

+200mV

0V

–200mV


0.1

0.0005

0.001

0.01

20 1k 20k100 10k

THD

+N (%

)

FREQUENCY (Hz)

0029

3-04

3

VO = ±0.75V

VO = ±2.5V

VO = ±1.5V

AV = +1000VS = ±2.5VRL = 2kΩ

Figure 43. Total Harmonic Distortion + Noise vs. Frequency

OP184/OP284/OP484


APPLICATIONS INFORMATION FUNCTIONAL DESCRIPTION The OP184/OP284/OP484 are precision single-supply, rail-to-rail operational amplifiers. Intended for the portable instrumentation marketplace, the OPx84 family of devices combine the attributes of precision, wide bandwidth, and low noise to make them a superb choice in single-supply applications that require both ac and precision dc performance. Other low supply voltage appli-cations for which the OP284 is well suited are active filters, audio microphone preamplifiers, power supply control, and telecommunications. To combine all of these attributes with rail-to-rail input/output operation, novel circuit design techniques are used.

D1

D2

Q4

V+

I1

Q3 2Q1Q

I2

V01

V02

–IN x

V–

+IN x

0029

3-04

4

–

–

R43kΩ

R33kΩ

R24kΩ

R14kΩ

Figure 44. OP284 Equivalent Input Circuit

For example, Figure 44 illustrates a simplified equivalent circuit for the input stage of the OP184/OP284/OP484. It comprises an NPN differential pair, Q1→Q2, and a PNP differential pair, Q3→Q4, operating concurrently. Diode Network D1→Diode Network D2 serves to clamp the applied differential input voltage to the OP284, thereby protecting the input transistors against avalanche damage. Input stage voltage gains are kept low for input rail-to-rail operation. The two pairs of differential output voltages are connected to the second stage of the OP284, which is a compound folded cascade gain stage. It is also in the second gain stage, where the two pairs of differential output voltages are combined into a single-ended, output signal voltage used to drive the output stage. A key issue in the input stage is the behavior of the input bias currents over the input common-mode voltage range. Input bias currents in the OP284 are the arithmetic sum of the base currents in Q1→Q3 and in Q2→Q4. As a result of this design approach, the input bias currents in the OP284 not only exhibit different amplitudes; they also exhibit different polarities. This effect is best illustrated by Figure 10. It is, therefore, of paramount importance that the effective source impedances connected to the OP284 inputs be balanced for optimum dc and ac performance.

To achieve rail-to-rail output, the OP284 output stage design employs a unique topology for both sourcing and sinking current. This circuit topology is illustrated in Figure 45. The output stage is voltage-driven from the second gain stage. The signal path through the output stage is inverting; that is, for positive input signals, Q1 provides the base current drive to Q6 so that it conducts (sinks) current. For negative input signals, the signal path via Q1→Q2→D1→Q4→Q3 provides the base current drive for Q5 to conduct (source) current. Both amplifiers provide output current until they are forced into saturation, which occurs at approxi-mately 20 mV from the negative supply rail and 100 mV from the positive supply rail.

0029

3-04

5

V+

I2

I1

Q1 Q3

Q4

Q2

V–

Q5

VOUT

Q6

R6R3

R2

R1

R4

R5

D1

INPUT FROMSECOND GAIN

STAGE

Figure 45. OP284 Equivalent Output Circuit

Thus, the saturation voltage of the output transistors sets the limit on the OP284 maximum output voltage swing. Output short-circuit current limiting is determined by the maximum signal current into the base of Q1 from the second gain stage. Under output short-circuit conditions, this input current level is approximately 100 µA. With transistor current gains around 200, the short-circuit current limits are typically 20 mA. The output stage also exhibits voltage gain. This is accomplished by the use of common-emitter amplifiers, and, as a result, the voltage gain of the output stage (thus, the open-loop gain of the device) exhibits a dependence to the total load resistance at the output of the OP284.

INPUT OVERVOLTAGE PROTECTION As with any semiconductor device, if conditions exist where the applied input voltages to the device exceed either supply voltage, the input overvoltage I-V characteristic of the device must be considered. When an overvoltage occurs, the amplifier could be damaged, depending on the magnitude of the applied voltage and the magnitude of the fault current. Figure 46 illustrates the overvoltage I-V characteristic of the OP284. This graph was generated with the supply pins connected to GND and a curve tracer’s collector output drive connected to the input.

OP184/OP284/OP484


0029

3-04

6

5

4

–5

–4

–3

–2

–1

0

1

2

3

–5 –4 –3 –2 –1 0 1 2 3 4 5

INPU

T C

UR

REN

T (m

A)

INPUT VOLTAGE (V) Figure 46. Input Overvoltage I-V Characteristics of the OP284

As shown in Figure 46, internal p-n junctions to the OP284 energize and permit current flow from the inputs to the supplies when the input is 1.8 V more positive and 0.6 V more negative than the respective supply rails. As illustrated in the simplified equivalent circuit shown in Figure 44, the OP284 does not have any internal current limiting resistors; thus, fault currents can quickly rise to damaging levels.

This input current is not inherently damaging to the device, provided that it is limited to 5 mA or less. For the OP284, once the input exceeds the negative supply by 0.6 V, the input current quickly exceeds 5 mA. If this condition continues to exist, an external series resistor should be added at the expense of addi-tional thermal noise. Figure 47 illustrates a typical noninverting configuration for an overvoltage-protected amplifier where the series resistance, RS, is chosen such that

( )

mA5SUPPLYMAXIN

S

VVR

−=

For example, a 1 kΩ resistor protects the OP284 against input signals up to 5 V above and below the supplies. For other configu-rations where both inputs are used, each input should be protected against abuse with a series resistor. Again, to ensure optimum dc and ac performance, it is recommended that source impedance levels be balanced.

R1

R2

VIN

VOUT1/2

OP284

0029

3-04

7

Figure 47. Resistance in Series with Input Limits Overvoltage Currents

to Safe Values

OUTPUT PHASE REVERSAL Some operational amplifiers designed for single-supply operation exhibit an output voltage phase reversal when their inputs are driven beyond their useful common-mode range. Typically, for single-supply bipolar op amps, the negative supply determines the lower limit of their common-mode range. With these devices,

external clamping diodes, with the anode connected to ground and the cathode to the inputs, prevent input signal excursions from exceeding the negative supply of the device (that is, GND), preventing a condition that causes the output voltage to change phase. JFET-input amplifiers can also exhibit phase reversal; and, if so, a series input resistor is usually required to prevent it.

The OP284 is free from reasonable input voltage range restrictions, provided that input voltages no greater than the supply voltages are applied. Although device output does not change phase, large currents can flow through the input protection diodes, as shown in Figure 46. Therefore, the technique recommended in the Input Overvoltage Protection section should be applied to those appli-cations where the likelihood of input voltages exceeding the supply voltages is high.

DESIGNING LOW NOISE CIRCUITS IN SINGLE-SUPPLY APPLICATIONS In single-supply applications, devices like the OP284 extend the dynamic range of the application through the use of rail-to-rail operation. In fact, the OPx84 family is the first of its kind to combine single-supply, rail-to-rail operation, and low noise in one device. It is the first device in the industry to exhibit an input noise voltage spectral density of less than 4 nV/√Hz at 1 kHz. It was also designed specifically for low-noise, single-supply applications, and as such, some discussion on circuit noise concepts in single-supply applications is appropriate.

Referring to the op amp noise model circuit configuration illustrated in Figure 48, the expression for an amplifier’s total equivalent input noise voltage for a source resistance level, RS, is given by

[ ] 222 )()()(2 nOASnOAnRnT eee Ri +×+= , units in HzV

where: RS = 2R is the effective, or equivalent, circuit source resistance. (enR)2 is the source resistance thermal noise voltage power (4kTR). k is the Boltzmann’s constant = 1.38 × 10–23 J/K. T is the ambient temperature in Kelvins of the circuit = 273.15 + TA (°C). (inOA)2 is the op amp equivalent input noise current spectral power (1 Hz bandwidth). (enOA)2 is the op amp equivalent input noise voltage spectral power (1 Hz bandwidth).

enR

enR

enOA

inOA

inOA

R

NOISELESS

R

NOISELESS

0029

3-04

8

IDEALNOISELESS

OP AMPRS = 2R

Figure 48. Op Amp Noise Circuit Model Used to Determine Total Circuit

Equivalent Input Noise Voltage and Noise Figure

OP184/OP284/OP484


As a design aid, Figure 49 shows the total equivalent input noise of the OP284 and the total thermal noise of a resistor for com-parison. Note that for source resistance less than 1 kΩ, the equivalent input noise voltage of the OP284 is dominant.

TOTAL SOURCE RESISTANCE, RS (Ω)

100

1

EQU

IVA

LEN

T TH

ERM

AL

NO

ISE

(nV/

Hz)

10

10k

OP284 TOTALEQUIVALENT NOISE

RESISTOR THERMALNOISE ONLY

0029

3-04

9

100 1k 100k

FREQUENCY = 1kHzTA = 25°C

Figure 49. OP284 Equivalent Thermal Noise vs. Total Source Resistance

Because circuit SNR is the critical parameter in the final analysis, the noise behavior of a circuit is often expressed in terms of its noise figure, NF. The noise figure is defined as the ratio of a circuit’s output signal-to-noise to its input signal-to-noise.

An expression of a circuit NF in dB, and in terms of the operational amplifier voltage and current noise parameters defined previously, is given by

( ) ( ) ( )( )

×++= 2

22

1log10dBnRS

SnOAnOA

eRie

NF

where: NF (dB) is the noise figure of the circuit, expressed in decibels. (enOA)2 is the OP284 noise voltage spectral power (1 Hz bandwidth). (inOA)2 is the OP284 noise current spectral power (1 Hz bandwidth). (enRS)2 is the source resistance thermal noise voltage power = (4kTRS). RS is the effective, or equivalent, source resistance presented to the amplifier.

Calculation of the circuit noise figure is straightforward because the signal level in the application is not required to determine it. However, many designers using NF calculations as the basis for achieving optimum SNR believe that a low noise figure is equal to low total noise. In fact, the opposite is true, as shown in Figure 50.The noise figure of the OP284 is expressed as a function of the source resistance level. Note that the lowest noise figure for the OP284 occurs at a source resistance level of 10 kΩ. However, Figure 49 shows that this source resistance level and the OP284 generate approximately 14 nV/ √Hz of total equivalent circuit noise. Signal levels in the application invariably increase to maximize circuit SNR, which is not an option in low voltage, single-supply applications.

TOTAL SOURCE RESISTANCE, RS (Ω)

10

100

NO

ISE

FIG

UR

E (d

B)

5

10k 100k1k0

9

8

7

6

4

3

2

1

0029

3-05

0

FREQUENCY = 1kHzTA = 25°C

Figure 50. OP284 Noise Figure vs. Source Resistance

Therefore, to achieve optimum circuit SNR in single-supply applications, it is recommended that an operational amplifier with the lowest equivalent input noise voltage be chosen, along with source resistance levels that are consistent with maintaining low total circuit noise.

OVERDRIVE RECOVERY The overdrive recovery time of an operational amplifier is the time required for the output voltage to recover to its linear region from a saturated condition. The recovery time is important in applications where the amplifier must recover quickly after a large transient event. The circuit shown in Figure 51 was used to evaluate the OP284 overload recovery time. The OP284 takes approximately 2 µs to recover from positive saturation and approximately 1 µs to recover from negative saturation.

2

31

+5V

8

4

R110kΩ

R39kΩ

R210kΩ

VIN10V STEP

–5V

VOUT1/2OP284

0029

3-05

1

Figure 51. Output Overload Recovery Test Circuit

SINGLE-SUPPLY, 3 V INSTRUMENTATION AMPLIFIER The low noise, wide bandwidth, and rail-to-rail input/output operation of the OP284 make it ideal for low supply voltage applications such as in the two op amp instrumentation amplifier shown in Figure 52. The circuit uses the classic two op amp instrumentation amplifier topology with four resistors to set the gain. The transfer equation of the circuit is identical to that of a noninverting amplifier. Resistor R2 and Resistor R3 should be closely matched to each other, as well as to Resistors (R1 + P1) and Resistor R4 to ensure good common-mode rejection performance.

OP184/OP284/OP484


Resistor networks should be used in this circuit for R2 and R3 because they exhibit the necessary relative tolerance matching for good performance. Matched networks also exhibit tight relative resistor temperature coefficients for good circuit temperature stability. Trimming Potentiometer P1 is used for optimum dc CMR adjustment, and C1 is used to optimize ac CMR. With the circuit values as shown, Circuit CMR is better than 80 dB over the frequency range of 20 Hz to 20 kHz. Circuit referred-to-input (RTI) noise in the 0.1 Hz to 10 Hz band is an impressively low 0.45 μV p-p. Resistor RP1 and Resistor RP2 serve to protect the OP284 inputs against input overvoltage abuse. Capacitor C2 can be included to the limit circuit bandwidth and, therefore, wide bandwidth noise in sensitive applications. The value of this capacitor should be adjusted, depending on the required closed-loop bandwidth of the circuit. The R4 to C2 time constant creates a pole at a frequency equal to

( )242

13CR

dBfπ

=

2.5 V REFERENCE FROM A 3 V SUPPLY In many single-supply applications, the need for a 2.5 V reference often arises. Many commercially available monolithic 2.5 V references require at least a minimum operating supply of 4 V. The problem is exacerbated when the minimum operating supply voltage is 3 V. The circuit illustrated in Figure 53 is an example of a 2.5 V reference that operates from a single 3 V supply. The circuit takes advantage of the OP284 rail-to-rail input/output voltage ranges to amplify an AD589 1.235 V output to 2.5 V.

0029

3-05

2

VOUT

5

67

3V

A1, A2 = 1/2 OP284

GAIN = 1 + R4R3

SET R2 = R3R1 + P1 = R4

8

4

C2

RP11kΩ

RP21kΩ

R19.53kΩ

R21.1kΩ

R31.1kΩ

R410kΩ

P1500Ω

3

21

VIN

A1

+

– A2

C1AC CMRR

TRIM5pF TO 40pF

Figure 52. Single Supply, 3 V Low Noise Instrumentation Amplifier

The low TCVOS of the OP284 at 1.5 μV/°C helps maintain an output voltage temperature coefficient that is dominated by the temperature coefficients of R2 and R3. In this circuit with 100 ppm/°C TCR resistors, the output voltage exhibits a tempera-ture coefficient of 200 ppm/°C. Lower tempco resistors are recommended for more accurate performance over temperature.

One measure of the performance of a voltage reference is its capacity to recover from sudden changes in load current. While sourcing a steady-state load current of 1 mA, this circuit recovers to 0.01% of the programmed output voltage in 1.5 μs for a total change in load current of ±1 mA.

0029

3-05

3

2.5VREF

3

21

3V

8

4

R3100kΩ

R2100kΩ

P15kΩ

R117.4kΩ

3V

0.1µF

AD589

1/2OP284+

–

RESISTORS = 1%, 100ppm/°CPOTENTIOMETER = 10 TURN, 100ppm/°C

Figure 53. 2.5 V Reference That Operates on a Single 3 V Supply

5 V ONLY, 12-BIT DAC SWINGS RAIL-TO-RAIL The OP284 is ideal for use with a CMOS DAC to generate a digitally controlled voltage with a wide output range. Figure 54 shows a DAC8043 used in conjunction with the AD589 to gen-erate a voltage output from 0 V to 1.23 V. The DAC is actually operating in voltage switching mode, where the reference is connected to the current output, IOUT, and the output voltage is taken from the VREF pin. This topology is inherently noninverting, as opposed to the classic current output mode, which is inverting and not usable in single-supply applications.

3

21

5V

5V

8

4

R3232Ω1%

R232.4Ω

1%

R117.8kΩ

R4100kΩ

1%

AD589 GND CLK SR1 LD

VREF

RRBVDD

IOUT1.23V

4

82

13 DAC8043

DIGITALCONTROL

7 6 5 1/2OP284 VOUT =

D4096 (5V)

0029

3-05

4

Figure 54. 5 V Only, 12-Bit DAC Swings Rail-to-Rail

In this application, the OP284 serves two functions. First, it buffers the high output impedance of the DAC VREF pin, which is on the order of 10 kΩ. The op amp provides a low impedance output to drive any following circuitry.

Second, the op amp amplifies the output signal to provide a rail-to-rail output swing. In this particular case, the gain is set to 4.1 so that the circuit generates a 5 V output when the DAC output is at full scale. If other output voltage ranges are needed, such as 0 V ≤ VOUT ≤ 4.095 V, the gain can be easily changed by adjusting the values of R2 and R3.


OP184/OP284/OP484


HIGH-SIDE CURRENT MONITOR In the design of power supply control circuits, a great deal of design effort is focused on ensuring the long-term reliability of a pass transistor over a wide range of load current conditions. As a result, monitoring and limiting device power dissipation is of prime importance in these designs. The circuit shown in Figure 55 is an example of a 3 V, single-supply, high-side current monitor that can be incorporated into the design of a voltage regulator with fold-back current limiting or a high current power supply with crowbar protection. This design uses an OP284 rail-to-rail input voltage range to sense the voltage drop across a 0.1 Ω current shunt. A P-channel MOSFET, used as the feedback element in the circuit, converts the differential input voltage of the op amp into a current. This current is applied to R2 to generate a voltage that is a linear representation of the load current. The transfer equation for the current monitor is given by

Monitor Output = LSENSE IR1

RR2 ×

×

For the element values shown, the transfer characteristic of the monitor output is 2.5 V/A.

0029

3-05

5

RSENSE0.1Ω IL

81

4

3

3V

3V

GS

D

2

M1SI9433

MONITOROUTPUT

3V

1/2OP284

R1100Ω

R22.49kΩ

0.1µF

Figure 55. High-Side Load Current Monitor

CAPACITIVE LOAD DRIVE CAPABILITY The OP284 exhibits excellent capacitive load driving capabilities. It can drive up to 1 nF, as shown in Figure 30. Even though the device is stable, a capacitive load does not come without penalty in bandwidth. The bandwidth is reduced to less than 1 MHz for loads greater than 2 nF. A snubber network on the output does not increase the bandwidth, but it does significantly reduce the amount of overshoot for a given capacitive load.

A snubber consists of a series R-C network (RS, CS), as shown in Figure 56, connected from the output of the device to ground. This network operates in parallel with the load capacitor, CL, to provide the necessary phase lag compensation. The value of the resistor and capacitor is best determined empirically.

0029

3-05

6

RS50Ω

0.1µF

CL1nFCS

100nF

5V

VIN100mV p-p

VOUT1/2OP284

Figure 56. Snubber Network Compensates for Capacitive Load

The first step is to determine the value of Resistor RS. A good starting value is 100 Ω (typically, the optimum value is less than 100 Ω). This value is reduced until the small-signal transient response is optimized. Next, CS is determined; 10 μF is a good starting point. This value is reduced to the smallest value for acceptable performance (typically, 1 μF). For the case of a 10 nF load capacitor on the OP284, the optimal snubber network is a 20 Ω in series with 1 μF. The benefit is immediately apparent, as shown in the scope photo in Figure 57. The top trace was taken with a 1 nF load, and the bottom trace was taken with the 50 Ω, 100 nF snubber network in place. The amount of overshoot and ringing is dramatically reduced. Table 7 shows a few sample snubber networks for large load capacitors.

0029

3-05

7

2µs

100

90

10

0%

50mV

1nF LOADONLY

SNUBBERIN

CIRCUIT

DLY 5.49µs

50mV BW

Figure 57. Overshoot and Ringing Are Reduced by Adding a Snubber Network in Parallel with the 1 nF Load

Table 7. Snubber Networks for Large Capacitive Loads Load Capacitance (CL) Snubber Network (RS, CS) 1 nF 50 Ω, 100 nF 10 nF 20 Ω, 1 µF 100 nF 5 Ω, 10 µF

OP184/OP284/OP484


LOW DROPOUT REGULATOR WITH CURRENT LIMITING Many circuits require stable, regulated voltages relatively close in potential to an unregulated input source. This low dropout type of regulator is readily implemented with a rail-to-rail output op amp, such as the OP284, because the wide output swing allows easy drive to a low saturation voltage pass device. Furthermore, it is particularly useful when the op amp also employs a rail-to-rail input feature because this factor allows it to perform high-side current sensing for positive rail current limiting. Typical examples are voltages developed from 3 V to 9 V range system sources or anywhere that low dropout performance is required for power efficiency. This 4.5 V example works from 5 V nominal sources with worst-case levels down to 4.6 V or less. Figure 58 shows such a regulator set up, using an OP284 plus a low RDS(ON), P-channel MOSFET pass device. Part of the low dropout perform-ance of this circuit is provided by Q1, which has a rating of 0.11 Ω with a gate drive voltage of only 2.7 V. This relatively low gate drive threshold allows operation of the regulator on supplies as low as 3 V without compromising overall performance.

The main voltage control loop operation of the circuit is provided by U1B, half of the OP284. This voltage control amplifier amplifies the 2.5 V reference voltage produced by Three Terminal U2, a REF192. The regulated output voltage, VOUT, is then

+=

31

RR2VV 2OUTOUT

For this example, because VOUT of 4.5 V with VOUT2 = 2.5 V requires a U1B gain of 1.8 times, R3 and R2 are chosen for a ratio of 1.2:1 or 10.0 kΩ:8.06 kΩ (using closest 1% values). Note that for the lowest VOUT dc error, R2||R3 should be maintained equal to R1 (as in this example), and the R2 to R3 resistors should be stable, close tolerance metal film types. The table in Figure 58 summarizes R1 to R3 values for some popular voltages. However, note that, in general, the output can be anywhere between VOUT2 and the 12 V maximum rating of Q1.

While the low voltage saturation characteristic of Q1 is a key part of the low dropout, another component is a low current sense com-parison threshold with good dc accuracy. Here, this is provided by Current Sense Amplifier U1A, which is provided by a 20 mV reference from the 1.235 V, AD589 Reference Diode D2, and the R7 to R8 divider. When the product of the output current and the RS value match this voltage threshold, the current control loop is activated, and U1A drives the Q1 gate through D1. This causes the overall circuit operation to enter current mode control with a current limit, ILIMIT, defined as

( )

+

=

R8RR7

RV

IS

D2RLIMIT 7

3

21

8

4

U1AOP284

U1BOP284

D2AD589

D11N4148

Q1SI9433DY

6

57

D31N4148

26

4

3

U2REF192

R310kΩVC

VIN COMMON

+VSVS > VOUT + 0.1V

C40.1µF

C50.01µF

C21µF

C10.01µF

C610µF

VOUT COMMON

VOUT =4.5V @ 350mA(SEE TABLE)

C20.1µF

OPTIONALON/OFF CONTROL INPUTCMOS HI (OR OPEN) = ON

LO = OFF

VOUT R1kΩ R2kΩ R3kΩOUTPUT TABLE

5.0V 4.99 10.0 10.04.5V 4.53 8.08 10.03.3V 2.43 3.24 10.03.0V 1.69 2.00 10.0

R522.1kΩ

R42.21kΩ

R64.99kΩ

R927.4kΩ

R111kΩ

R101kΩ

R14.53kΩ

VOUT22.5V

R74.99kΩ

R8301kΩ

R28.06kΩ

RS0.05Ω

0029

3-05

8

Figure 58. Low Dropout Regulator with Current Limiting\

http://www.analog.com/AD589l

OP184/OP284/OP484


Obviously, it is desirable to keep this comparison voltage small because it becomes a significant portion of the overall dropout voltage. Here, the 20 mV reference is higher than the typical offset of the OP284 but is still reasonably low as a percentage of VOUT (<0.5%). In adapting the limiter for other ILIMIT levels, Sense Resistor RS should be adjusted along with R7 to R8, to maintain this threshold voltage between 20 mV and 50 mV.

Performance of the circuit is excellent. For the 4.5 V output version, the measured dc output change for a 225 mA load change was on the order of a few microvolts, while the dropout voltage at this same current level was about 30 mV. The current limit, as shown in Figure 58, is 400 mA, allowing the circuit to be used at levels up to 300 mA or more. While the Q1 device can actually support currents of several amperes, a practical current rating takes into account the 2.5 W, 25°C dissipation of the 8-lead SOIC device. Because a short-circuit current of 400 mA at an input level of 5 V causes a 2 W dissipation in Q1, other input conditions must be considered carefully in terms of potential overheating of Q1. Of course, if higher powered devices are used for Q1, this circuit can support outputs of tens of amperes as well as the higher VOUT levels already noted.

The circuit shown can either be used as a standard low dropout regulator, or it can be used with on/off control. By driving Pin 3 of U2 with the optional logic control signal, VC, the output is switched between on and off. Note that when the output is off in this circuit, it is still active (that is, not an open circuit). This is because the off state simply reduces the voltage input to R1, leaving the U1A/U1B amplifiers and Q1 still active.

When the on/off control is used, Resistor R10 should be used with U2 to speed on/off switching and to allow the output of the circuit to settle to a nominal zero voltage. Component D3 and Component R11 also aid in speeding up the on/off transition by providing a dynamic discharge path for C2. Off/on transition time is less than 1 ms, while the on/off transition is longer, but less than 10 ms.

3 V, 50 HZ/60 HZ ACTIVE NOTCH FILTER WITH FALSE GROUND To process signals in a single-supply system, it is often best to use a false ground biasing scheme. A circuit that uses this approach is shown in Figure 59. In this circuit, a false ground circuit biases an active notch filter used to reject 50 Hz/60 Hz power line interference in portable patient monitoring equipment.

Notch filters are commonly used to reject power line frequency interference that often obscures low frequency physiological signals, such as heart rates, blood pressure readings, EEGs, and EKGs. This notch filter effectively squelches 60 Hz pickup at a Filter Q of 0.75. Substituting 3.16 kΩ resistors for the 2.67 kΩ resistor in the twin-T section (R1 through R5) configures the active filter to reject 50 Hz interference.

0029

3-05

9

R22.67kΩ

R610kΩ R7

1kΩR81kΩ

R1110kΩ

R920kΩ

R12150Ω

R1020kΩ

13

5

6711

2

3V

VOVIN A2A1

8A3

4

10

9

3V

A1, A2, A3 = OP484

Q = 0.75

NOTE: FOR 50Hz APPLICATIONSCHANGE R1, R2, R3, AND R4 TO 3.1kΩAND R5 TO 1.58kΩ (3.16kΩ ÷ 2).

R32.67kΩ

R12.67kΩ

R42.67kΩ

R51.33kΩ(2.68kΩ ÷ 2)

C32µF

(1µF × 2)

C50.03µF

C11µF

C21µF

C41µF

C61µF1.5V

Figure 59. A 3 V Single-Supply, 50Hz to 60 Hz Active Notch Filter

with False Ground

Amplifier A3 is the heart of the false ground bias circuit. It buffers the voltage developed at R9 and R10 and is the reference for the active notch filter. Because the OP484 exhibits a rail-to-rail input common-mode range, R9 and R10 are chosen to split the 3 V supply symmetrically. An in-the-loop compensation scheme is used around the OP484 that allows the op amp to drive C6, a 1 μF capacitor, without oscillation. C6 maintains a low impedance ac ground over the operating frequency range of the filter.

The filter section uses an OP484 in a Twin-T configuration whose frequency selectivity is very sensitive to the relative matching of the capacitors and resistors in the twin-T section. Mylar is the material of choice for the capacitors, and the relative matching of the capacitors and resistors determines the pass band symmetry of the filter. Using 1% resistors and 5% capacitors produces satis-factory results.

OP184/OP284/OP484


OUTLINE DIMENSIONS

COMPLIANT TO JEDEC STANDARDS MS-001CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FORREFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS. 07

0606

-A

0.022 (0.56)0.018 (0.46)0.014 (0.36)

SEATINGPLANE

0.015(0.38)MIN

0.210 (5.33)MAX

0.150 (3.81)0.130 (3.30)0.115 (2.92)

0.070 (1.78)0.060 (1.52)0.045 (1.14)

8

1 4

5 0.280 (7.11)0.250 (6.35)0.240 (6.10)

0.100 (2.54)BSC

0.400 (10.16)0.365 (9.27)0.355 (9.02)

0.060 (1.52)MAX

0.430 (10.92)MAX

0.014 (0.36)0.010 (0.25)0.008 (0.20)

0.325 (8.26)0.310 (7.87)0.300 (7.62)

0.195 (4.95)0.130 (3.30)0.115 (2.92)

0.015 (0.38)GAUGEPLANE

0.005 (0.13)MIN

Figure 60. 8-Lead Plastic Dual In-Line Package [PDIP]

(N-8) P-Suffix

Dimensions shown in inches and (millimeters)

COMPLIANT TO JEDEC STANDARDS MS-001CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FORREFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS. 07

0606

-A

0.022 (0.56)0.018 (0.46)0.014 (0.36)

0.150 (3.81)0.130 (3.30)0.110 (2.79)

0.070 (1.78)0.050 (1.27)0.045 (1.14)

14

1 7

8

0.100 (2.54)BSC

0.775 (19.69)0.750 (19.05)0.735 (18.67)

0.060 (1.52)MAX

0.430 (10.92)MAX

0.014 (0.36)0.010 (0.25)0.008 (0.20)

0.325 (8.26)0.310 (7.87)0.300 (7.62)

0.015 (0.38)GAUGEPLANE

0.210 (5.33)MAX

SEATINGPLANE

0.015(0.38)MIN

0.005 (0.13)MIN

0.280 (7.11)0.250 (6.35)0.240 (6.10)

0.195 (4.95)0.130 (3.30)0.115 (2.92)

Figure 61. 14-Lead Plastic Dual In-Line Package [PDIP]

(N-14) P-Suffix

Dimensions shown in inches and (millimeters)

OP184/OP284/OP484


CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FORREFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

COMPLIANT TO JEDEC STANDARDS MS-012-AA

0124

07-A

0.25 (0.0098)0.17 (0.0067)

1.27 (0.0500)0.40 (0.0157)

0.50 (0.0196)0.25 (0.0099) 45°

8°0°

1.75 (0.0688)1.35 (0.0532)

SEATINGPLANE

0.25 (0.0098)0.10 (0.0040)

41

8 5

5.00 (0.1968)4.80 (0.1890)

4.00 (0.1574)3.80 (0.1497)

1.27 (0.0500)BSC

6.20 (0.2441)5.80 (0.2284)

0.51 (0.0201)0.31 (0.0122)

COPLANARITY0.10

Figure 62. 8-Lead Standard Small Outline Package [SOIC_N]

Narrow Body (R-8)

S-Suffix Dimensions shown in millimeters and (inches)

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FORREFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

COMPLIANT TO JEDEC STANDARDS MS-012-AB06

0606

-A

14 8

71

6.20 (0.2441)5.80 (0.2283)

4.00 (0.1575)3.80 (0.1496)

8.75 (0.3445)8.55 (0.3366)

1.27 (0.0500)BSC

SEATINGPLANE

0.25 (0.0098)0.10 (0.0039)

0.51 (0.0201)0.31 (0.0122)

1.75 (0.0689)1.35 (0.0531)

0.50 (0.0197)0.25 (0.0098)

1.27 (0.0500)0.40 (0.0157)

0.25 (0.0098)0.17 (0.0067)

COPLANARITY0.10

8°0°

45°

Figure 63. 14-Lead Standard Small Outline Package [SOIC_N]

Narrow Body (R-14)

S-Suffix Dimensions shown in millimeters and (inches)

OP184/OP284/OP484


ORDERING GUIDE Model1 Temperature Range Package Description Package Option OP184ES −40°C to +125°C 8-Lead SOIC_N S-Suffix (R-8) OP184ES-REEL −40°C to +125°C 8-Lead SOIC_N S-Suffix (R-8) OP184ES-REEL7 −40°C to +125°C 8-Lead SOIC_N S-Suffix (R-8) OP184ESZ −40°C to +125°C 8-Lead SOIC_N S-Suffix (R-8) OP184ESZ-REEL −40°C to +125°C 8-Lead SOIC_N S-Suffix (R-8) OP184ESZ-REEL7 −40°C to +125°C 8-Lead SOIC_N S-Suffix (R-8) OP184FS −40°C to +125°C 8-Lead SOIC_N S-Suffix (R-8) OP184FS-REEL −40°C to +125°C 8-Lead SOIC_N S-Suffix (R-8) OP184FS–REEL7 −40°C to +125°C 8-Lead SOIC_N S-Suffix (R-8) OP184FSZ −40°C to +125°C 8-Lead SOIC_N S-Suffix (R-8) OP184FSZ-REEL −40°C to +125°C 8-Lead SOIC_N S-Suffix (R-8) OP184FSZ-REEL7 −40°C to +125°C 8-Lead SOIC_N S-Suffix (R-8) OP284EP −40°C to +125°C 8-Lead PDIP P-Suffix (N-8) OP284EPZ −40°C to +125°C 8-Lead PDIP P-Suffix (N-8) OP284ES −40°C to +125°C 8-Lead SOIC_N S-Suffix (R-8) OP284ES-REEL −40°C to +125°C 8-Lead SOIC_N S-Suffix (R-8) OP284ES-REEL7 −40°C to +125°C 8-Lead SOIC_N S-Suffix (R-8) OP284ESZ −40°C to +125°C 8-Lead SOIC_N S-Suffix (R-8) OP284ESZ-REEL −40°C to +125°C 8-Lead SOIC_N S-Suffix (R-8) OP284ESZ-REEL7 −40°C to +125°C 8-Lead SOIC_N S-Suffix (R-8) OP284FS −40°C to +125°C 8-Lead SOIC_N S-Suffix (R-8) OP284FS-REEL −40°C to +125°C 8-Lead SOIC_N S-Suffix (R-8) OP284FS-REEL7 −40°C to +125°C 8-Lead SOIC_N S-Suffix (R-8) OP284FSZ −40°C to +125°C 8-Lead SOIC_N S-Suffix (R-8) OP284FSZ-REEL −40°C to +125°C 8-Lead SOIC_N S-Suffix (R-8) OP284FSZ-REEL7 −40°C to +125°C 8-Lead SOIC_N S-Suffix (R-8) OP484ES −40°C to +125°C 14-Lead SOIC_N S-Suffix (R-14) OP484ES-REEL −40°C to +125°C 14-Lead SOIC_N S-Suffix (R-14) OP484ESZ −40°C to +125°C 14-Lead SOIC_N S-Suffix (R-14) OP484ESZ-REEL −40°C to +125°C 14-Lead SOIC_N S-Suffix (R-14) OP484FPZ −40°C to +125°C 14-Lead PDIP P-Suffix (N-14) OP484FS −40°C to +125°C 14-Lead SOIC_N S-Suffix (R-14) OP484FS-REEL −40°C to +125°C 14-Lead SOIC_N S-Suffix (R-14) OP484FS-REEL7 −40°C to +125°C 14-Lead SOIC_N S-Suffix (R-14) OP484FSZ −40°C to +125°C 14-Lead SOIC_N S-Suffix (R-14) OP484FSZ-REEL −40°C to +125°C 14-Lead SOIC_N S-Suffix (R-14) OP484FSZ-REEL7 −40°C to +125°C 14-Lead SOIC_N S-Suffix (R-14) 1 Z = RoHS Compliant Part.

OP184/OP284/OP484


NOTES

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