[PPT]W5 of Computer Engineering (Why, What, When, Where, … · Web viewProf. Swati Sharma [email protected] Microprocessor & Interfacing - 2150707 Darshan Institute of Engineering

Unit-8 Advanced Microprocessor Darshan Institute of Engineering & Technology1

Prof. Swati [email protected]

Microprocessor & Interfacing - 2150707 Darshan Institute of Engineering & Technology

Unit-8Advanced Microprocessor

Unit-8 Advanced Microprocessor Darshan Institute of Engineering & Technology 2

Subject OverviewSr. No. Unit % Weightage

1 Introduction to Microprocessor 8%2 Microprocessor Architecture and Operations 7%

3 8085 Microprocessor 10%

4 Assembly Language Basics 10% 5 8085 Assembly Language Programs 10%6 Stack & Subroutines 10%7 I/O Interfacing 15%

8 Advanced Microprocessors 20%

9 SUN SPARC Microprocessor 5%

10 ARM Processor 5%


Subject OverviewReference Book:

Sr. No.

Unit Reference Book

1 Introduction to Microprocessor Microprocessor Architecture, Programming, and Applications with the 8085Ramesh S. Gaonkar Publication: Penram International

2 Microprocessor Architecture and Operations3 8085 Microprocessor 4 Assembly Language Programming Basics5 8085 Assembly Language Programs6 Stack & Subroutines7 I/O Interfacing 8 Advanced Microprocessors Microprocessor & Interfacing

Douglas Hall, TMH9 SUN SPARC Microprocessor Advanced Microprocessors,

Daniel Tabak, McGrawHill10 ARM Processor

Unit-8 Advanced Microprocessor Darshan Institute of Engineering & Technology

Introduction to 8086 8086 is a 16-bit processor, which implies that

• 16-bit data bus• 16-bit ALU• 16-bit registers

8086 has a 20 bit address bus can access up to 220 memory locations.( 220=1048576 bytes =1 MB)

It can support up to 64K I/O ports. (216 I/O ports-> 216=65536) 8086 has 256 vectored interrupt 8086 contains powerful instruction set , that supports Multiply

and Divide operation

4


Introduction to 8086 8086 can operate in 2 modes

i. Minimum mode: A system with only one processor i.e.8086ii. Maximum mode: A system with multiple processors.e.g. 8086 + math co-processor(8087),

8086+ I/O processor (8089)

8086 uses memory segmentation Segmentation means dividing memory into logical components. In 8086 memory is divided into 16 segments of capacity 216 bytes

each and used as code, stack, data and extra segment respectively.

5


8086 Architecture

Block Diagram

6

7

8086 Architecture

• In 8086 CPU is divided into two independent functional parts BIU and EU.

• Dividing the work between these two units speeds up the processing.


8086 Architecture: BIU

8

Components of BIU(Bus Interface Unit)1. Instruction queue2. Segment Registers It holds the instruction

bytes of the next instruction to be executed by EU

Four 16-bit register that provides powerful memory management mechanismES (extra segment), CS (code segment), SS (stack segment) , DS (data segment).


8086 Architecture:BIU

9

Components of BIU(Bus Interface Unit)1. Instruction queue2. Segment Registers3. Instruction pointer (IP)4. Address Generation and bus control

Register that holds 16-bit address or offset of next code byte within code segmentGeneration of

20-bit physical address


8086 Architecture: BIU

10

Task carried out by BIU

1. Fetch instruction from memory

2. Read/ Write instruction to/from the memory

3. Input/ Output of data to/from peripheral ports

4. Write the data to memory.

5. Address generation for memory reference

6. Queuing of instruction

7. Thus, BUI handles all transfer of data and address


8086 Architecture: EU Components of EU1. ALU (Arithmetic logic Unit)2. CU (Control Unit)3. General Purpose Registers (GPR)Contains 16-bit ALU, that performs add, subtract, increment, decrement, compliment,shift binary numbers, AND, OR, XOR etc.

Directs internal operation

EU has 4 general purpose 16-bit registeri.e. AX, BX, CX, DXeach register is the combination of two 8-bit register


8086 Architecture: EU Components of EU1. ALU (Arithmetic logic Unit)2. CU (Control Unit)3. General Purpose Registers4. Pointer Register 5. Index Register

Stack pointer : It always points to the top of the stack. Used for sequential access of stack segment.Base pointer : is used when we need to pass parameter through stack

SI (Source Index) and DI (Destination Index) are used for string related operation and for moving block of memory from one location to the other.


8086 Architecture: EU Components of EU1. ALU (Arithmetic logic Unit)2. CU (Control Unit)3. General Purpose Registers4. Pointer Register 5. Index Register6. Flag Register

The 16-bit flag register of 8086 contains 9 active flags (6 conditional & 3 control flags), other 7 flags are undefined.

1. CF- Carry Flag2. PF- Parity Flag3. AF- Auxiliary Flag4. ZF- Zero Flag5. SF- Sign Flag6. TF- Trap Flag 7. IF- Interrupt Flag 8. DF- Direction Flag 9. OF- Overflow Flag


8086 Architecture: EU Task carried out by EU

- Decodes the instruction

- It executes instructions ( executes decoded instructions)

- Tells BIU from where to fetch the instruction

- EU takes care of performing operation on the data

- EU is also known as execution heart of the processor


Segment Register in 8086

15


Segment Register in 8086Types of Segment registers are as follows:-1. Code Segment (CS): executable program is

stored in CS2. Data Segment (DS): The DS contains most

data used by program. Data are accessed in the Data Segment by an offset address or the content of other register that holds the offset address.

3. Stack Segment (SS): SS defined the area of memory used for the stack.

4. Extra Segment (ES): ES is additional data segment.

16


Segmentation in 8086

17


Segmentation in 8086What is Segment?Segment is just an area in memory.

What is Segmentation?The process of dividing memory into segments of various sizes is called Segmentation.

18


Segmentation in 8086What is the need of segmentation in 8086? Memory is huge collection of bytes. In order to organize these bytes in an efficient manner

Segmentation is used.

Segment = Total memory available/size of each Segment = 1MB/64KB

= 1024KB/64KB = 16 segments

19

64KB

1 MB


Segmentation in 8086 Intel 8086 has 20 lines address bus. With 20 address lines, the memory that can be addressed is 220

bytes.220 = 1,048,576 bytes 1 MB = 1111 1111 1111 1111 1111 = FFFFF H

20


Segmentation in 8086How many segments can be accessed at a time in 8086? At a time 8086 can only access 4 segments.

i.e. 64 KB * 4=256 KB of segments can be accessed at a time.

8086 memory with address ranging from 000000 H to FFFFFF H. Size of each Segment Register is 16-bit

216 = 65535 bytes = 64K [size of each segment ]

21


Segmentation in 8086How to calculate physical address from segment address Segment Registers are used to hold the upper 16-bit of the

starting address for each of the segment. The 16-bit address is the starting address of the segment from

where the BIU is currently fetching instruction code bytes. The BIU always inserts zero's for the LSB of the 20-bit address for a

segment, as the segment registers cannot store 20 bits, they only store the upper 16 bits.

22


Segmentation in 8086How is a 20-bit physical address obtained if data bus is of 16-bit? The 20-bit address is called its Physical Address (PA). PA= Base Address : Offset Offset is the displacement of the memory location from the

starting location of the segment.

23


Segmentation in 8086E.g. Base address DS=2222 H

Step-1: Convert DS 16-bit address to 20-bit address

- the BIU appends 0H to the LSBs of the base address.

22220 H

Step-2: Retrieve offset address

- Assuming offset address = 0016 H

PA= Base Address : Offset

PA= 2222 H: 0016 H

24


Segmentation in 8086Step-3: To calculate the effective address of the memoryPhysical Address = Starting Address of Segment(20-bit) + Offset

EA = 2 2 2 2 0 H+ 0 0 1 6 H----------------2 2 2 3 6 H

25


8086 Flag Register

26


8086 Flag Register

27

• The 16-bit flag register of 8086 contains 9 active flags (6 conditional & 3 control flags), other 7 flags are undefined.

U- Undefined CF- Carry FlagTF- Trap Flag PF- Parity FlagIF- Interrupt Flag AF- Auxiliary FlagDF- Direction Flag ZF- Zero FlagOF- Overflow Flag SF- Sign Flag


8086 Flag Register

28


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

U U U U OF DF IF TF SF ZF U AF U PF U CF

Trap Flag is used for single step control.TF=0 ; Whole program will be executed TF=1 ; Program will run in single step mode.

Interrupt Flag IF=0 ; Disable Maskable InterruptIF=1 ; Enable Maskable Interrupt


8086 Flag Register

29


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

U U U U OF DF IF TF SF ZF U AF U PF U CF

Direction Flag DF=0 ; String bytes are accessed from lower to higher memory address.DF=1 ; String bytes are accessed from higher to lower memory address.

Overflow Flag It occurs when signed numbers are added or subtracted.OF=0 ; result has not exceeded the capacity of machine.OF=1 ; result has exceeded the capacity of machine.


8086 Flag Register Carry Flag (CF): This flag indicates an overflow condition for unsigned integer

arithmetic. Auxiliary Flag (AF): If an operation performed in ALU generates a

carry/barrow from lower nibble (i.e. D0 – D3) to upper nibble (i.e. D4 – D7), the AF flag is set i.e. carry given by D3 bit to D4 is AF flag. This is not a general-purpose flag, it is used internally by the processor to perform Binary to BCD conversion.

Parity Flag (PF): This flag is used to indicate the parity of result. If lower order 8-bits of the result contains even number of 1’s, the Parity Flag is set and for odd number of 1’s, the Parity Flag is reset.

Zero Flag (ZF): It is set; if the result of arithmetic or logical operation is zero else it is reset.

Sign Flag (SF): In sign magnitude format the sign of number is indicated by MSB bit. If the result of operation is negative, sign flag is set.

30


8086 pin diagram

31

32

8086 pin diagramAddress and Data pinsAD0-AD15 (bidirectional)

• These lines are multiplexed bidirectional address/data bus.

• AD0-AD7 carry lower order byte of data and AD8-AD15 carry higher order byte of data.

• When ALE=1, then Address bus gets enabled, else Data bus will get enabled.

33

8086 pin diagramAddress and Data pinsA16/S3- A19/S6 (unidirectional)• These lines are multiplexed and

unidirectional address and status bus.• During T1, they carry higher order 4-bit

address.• In the remaining clock cycles, they carry

status signals.• S5 gives the status of Interrupt Flag (IF)• S6 goes low, when 8086 controls the

shared system bus.• S3 and S4 indicates the segment register

S4 S3 Register

0 0 ES

0 1 SS

1 0 CS

1 1 DS

34

8086 pin diagramBHE/S7

• BHE stands for Bus High Enable.

• Active low output signal.

• BHE signal is used to indicate the

transfer of data over higher order data

bus (D8 – D15).

• 8-bit I/O devices use this signal.

• S7 is reserved for future development.

35

8086 pin diagramInterrupt Related pinsNMI• It is an active high input signal• It is a non-mask able interrupt signal.

INTR• It is an active high input signal• It is an interrupt request signal.

INTA• It is an active low output signal.• This is an interrupt acknowledge signal.• When microprocessor receives INTR

signal, it acknowledges the interrupt by generating this signal.

36

8086 pin diagramClock Related pins

CLK

Generates clock signals that synchronize

the operation of processor.

37

8086 pin diagramClock Related pinsRESET: Active high input signalWhen high, microprocessor enters into reset state and Terminates activity of processorProcessor requires 4 clock cycle to reset. Thus RESET signal must be 1 for at least 4 clock cycles

READY: Active high input signalThis is an acknowledgement signal from I/O devices or memory.When READY= high; it indicates that the device is ready to transfer data.When READY=low; microprocessor is in wait state.

38

8086 pin diagramControl PinsTEST• Active low input signal.• It is used to test the status of math

coprocessor 8087.• The BUSY pin of 8087 is connected to

this pin of 8086.• If low, execution continues, else

microprocessor is in wait state.

39

8086 pin diagramControl PinsMN/MX8086 works in two modes:1. Minimum Mode [Active high i/p signal]2. Maximum Mode [Active low i/p signal]• If MN/MX is high, it works in minimum

mode.• If MN/MX is low, it works in maximum

mode.• Pins 24 to 31 issue two different sets of

signals.• One set of signals is issued when CPU

operates in minimum mode.• Other set of signals is issued when CPU

operates in maximum mode.

40

8086 pin diagramMode Multiplexed pins

S2 S1 S0 Machine Language

0 0 0 Interrupt acknowledgement

0 0 1 Read I/O

0 1 0 Write I/O

0 1 1 HALT

1 0 0 Code Access

1 0 1 Read Memory

1 1 0 Write Memory

1 1 1 Passive

41

8086 pin diagramMode Multiplexed pinsDEN It is an active low output signalThis is a Data Enable signalThis signal is used to enable the transceiver

DT/R This is a Data Transmit/Receive signal.When high=>data is transmitted out

low=>data is received in

M/IOThis signal is issued by the microprocessor to distinguish memory access from I/O access.When high=> memory is accessed. low=> I/O devices are accessed

42


QS1 QS0 Characteristics

0 0 No operation

0 1 First byte of opcode from queue

1 0 Empty the queue

1 1 Subsequent byte from queue

43


LOCK

• It is an active low output signal.

• This signal indicates that other

processors should not ask CPU (8086) to

hand over the system bus.

• This pin is activated by using LOCK prefix

on any instruction.

• It is an active low output signal.

• It is used to write data in memory or

output signal, depending on status of

M/IO signal.

44

8086 pin diagramMode Multiplexed pinsHOLD • It is an active high input signal.• When DMA controller needs to use

address/data bus, it sends a request to the CPU through this pin.

• When microprocessor receives HOLD signal, it issues HLDA signal to the DMA controller.

HLDA • It is an active high output signal.• It is a Hold Acknowledge signal.• It is issued after receiving the HOLD

signal.

45


RQ/GT0 and RQ/GT1

• These are Request/Grant bi-directional

pins.

• Other processors request the CPU

through these lines to release the

system bus.

• After receiving the request, CPU sends

acknowledge signal on the same lines.

• RQ/GT0 has higher priority than RQ/GT1


80286

46


Introduction:80286 The Intel 80286 had a 24-bit address bus and was able to address

up to 16 MB of RAM, compared to 1 MB for its predecessor. It was designed for multi-user systems with multitasking

applications, including communications and real-time process control.

80286 is the advanced microprocessors with memory management and protection abilities.

47


Introduction:80286 80286 have two operating modes namely real address mode and

virtual address mode. In real address mode, the 80286 can address up to 1Mb of

physical memory address like 8086. In virtual address mode, it can address up to 16 Mb of physical

memory address space and 1 GB of virtual memory address space. The performance of 80286 is five times faster than the standard

8086.

48


80286 Architecture


80286 Architecture80286 Architecture contains 4 separate processing units1. Bus Unit (BU)2. Instruction Unit (IU)3. Address Unit (AU)4. Execution Unit (EU)

50


80286 ArchitectureBus Unit (BU)Components1. address latches2. data transceivers3. bus interface and circuitry4. Instruction pre-fetcher5. Processor extension interface 6. 6 byte instruction queue.

51


80286 ArchitectureBus Unit (BU) To perform all memory and I/O read and write. To pre-fetch the instruction bytes. To control the transfer of data to and from

processor extension devices like 80287 math co-processor.

Whenever BU is not using the buses for the operation, it pre-fetches the instruction bytes and put them is a 6 byte pre-fetch queue.

Take care of communication b/w CPU and a coprocessor.

52


80286 ArchitectureInstruction Unit (IU): It has 3 decoded instruction queue and instruction decoder.Functions : It fully decodes up to three prefetched instructions and holds

them in a queue, So that EU can access them. It helps the processor to speed up, as pipelining of instruction is

done.

53


80286 ArchitectureExecution Unit (EU) It includes ALU, registers and the Control unit. Registers are general purpose, index, pointer, flag register and 16 –

bit Machine Status Word (MSW).Functions : To sequentially execute the instructions received from the

instruction unit. ALU result is either stored in register bank or sent over the data bus.

54


80286 ArchitectureAddress Unit It consists of segment registers, offset address and a physical address adder. It Computes the physical address that will be sent out to the memory or I/O

by BU. 80286 operate in two different modes

1. Real address mode 2. Protected virtual address mode.

55


Register Organization of 80286

56


80286 Register Organization1. Eight 16-bit general purpose registers (AX, BX, CX, DX, SP, BP, SI, DI)2. Four 16-bit segment registers (CS, SS, DS, ES)3. 16-bit Instruction Pointer (IP)4. 16-bit Flag Registerplus5. one new 16-bit machine status word (MSW) register

57


80286 Register Organization

58

General Register


80286 Flag Register

59

Flag Register and Machine Status Word

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

U NT IOPL OF DF IF TF SF ZF U AF U PF U CF

New to 80286

Input Output Privilege Level flag (IOPL) • Used in protected mode operation to select the privilege level

for I/O devices. • 00,01,10 and 11 are various bits of privilege level; 00 is the

highest and 11 is the lowest privilege level respectively.


80286 Flag Register

60

Flag Register and Machine Status Word• The 16-bit flag register of 8086 contains 9 active flags (6

conditional & 3 control flags), other 7 flags are undefined.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


Nested Task (NT) flag• It is used in protected mode. • Bit is set when one task invokes another task.


80286 Flag RegisterMachine Status Word (MSW) Register

61

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

TS EM MP PE

Protected Mode EnablePE=1; Places 80286 in protected modePE=0; It can be only cleared by resetting CPU

Used to indicate whether a processor extension (co-processor) is present in the system or not


80286 Flag RegisterMachine Status Word (MSW) Register

62

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

TS EM MP PE

Monitor processor extension If set, this flag allows WAIT instruction to generate a processor extension not present exception

EMulate processor extension flagIf set, The EMulate coprocessor bit is set to cause all coprocessor opcodes to generate a Coprocessor Not Available fault.

Task SwitchTS is automatically set whenever a task switch operation is performed.

Instructions used to load and store MSW:1. LMSW instruction (Load Machine Status Word)2. SMSW instruction (Store Machine Status Word)


80286: Real Address ModeReal Mode Address Unit computes the address with segment base and offset

like 8086. Maximum physical space allowed in this mode is 1MB. When 80286 get reset, it always starts execution in real mode.Task of 80286 in Real Mode Initializes IP and other registers of 80286 Initializes the peripheral Enables interrupts Set up the descriptor table Prepares for entering in PVAM(Protected Virtual Address Mode)

63


80286: Protected Virtual Address Mode 286 is the 1st processor to support the concept of Virtual memory

and Memory management. Here, the address unit acts as MMU. All 24 address lines are used and can access up to 16MB of

physical memory. If descriptor table scheme is used it can address up to 1GB of

virtual memory.

64


80286: Protected Virtual Address ModeWhat is the role of MMU? Memory Management Unit (MMU) translates the virtual memory

address into the physical memory address. Virtual memory can be many times larger than the physical

memory. Only the programs currently required are brought from the

secondary storage such as a hard disk to, the physical memory (RAM) for execution.

This is desirable as a microprocessor is supposed to store large programs and data which cannot be accommodated in the physical memory space.

65


80286: Protected Virtual Address ModeWhat is the role of MMU? The hard disk is in the virtual or logical address space but not in

the physical address space. Faster memory such as RAM is used as the physical memory When a microprocessor is to execute a program, it checks whether

the program is available in the physical memory (RAM). If the program is not available in the physical memory, it is brought

from the secondary memory to the physical memory for execution.

If available space is inadequate in the physical memory, some less important/unused program can be swapped back to the secondary memory to create space.

66


80286: Protected Virtual Address Mode The complete virtual memory is mapped on to the 16Mbyte

physical memory. If a program larger than 16Mbyte is stored on the hard disk and is

to be executed by swapping sequentially as per sequence of execution.

The huge programs are divided in smaller segments or pages arranged in appropriate sequence.

67


80286: Protected Virtual Address ModeDescriptor This smaller segments or pages have been associated with data

structure called a Descriptor. It contains information of program segment or pages. The data structure Descriptor is essentially one such identifier of

particular program or segment. The set of such descriptor arranged in a proper sequence

describes a complete program.

68


80286: Protected Virtual Address ModeDescriptor Table The set of descriptor is called Descriptor Table All the sets of descriptor/Descriptor Table are prepared and

Managed by Operating System. Descriptor carry all the relevant information regarding a segment

and its access rights.Types of Descriptor Table

69

Data Segment Descriptor Used for Data Segment Code Segment Descriptor Used for Code Segment System Segment Descriptor Used for System Programs Gate Segment Descriptor Used for Subroutine and ISR


80286 Modes

70

Real Address Mode Protected Virtual Address ModeCan only address 1 MB of system memory and act as fast 8086.

Can address till 16MB of System Memory

Initially every processor is in Real Mode i.e MSW PE =0

Microprocessor will Switch to this mode by setting MSW PE-bit

Doesn’t Supports the concept of Virtual Memory

Supports the concept of Virtual Memory

Real mode provides no support for memory protection, multitasking, or code privilege levels.

Protected mode provides support for memory protection, multitasking, or code privilege levels.


Real Address Mode Address Calculation Total 1MB of Memory, divided among 16-

segments with each of size 64kb. 80286 reserves two fixed areas for

i. System Initialization ii. IVT (Interrupt Vector Table)

71

IVT-1KB of Starting address

00000H – 003FFH

System Initialization FFFF0H – FFFFFH


Memory Access in GDT and LDT

72


Protected Virtual Address Mode Address Calculation

73

Points to the entry of Descriptor table


PVAM : Selector

74

Selector RPLTI

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit 3-15 points to the Entry of Descriptor Table

TI-Table IndicatorTI=0 : GDT(Global Descriptor Table)TI=1 : LDT(Local Descriptor Table)

00 Kernel Level

01 OS Services

10 OS Extension

11 Application Level


Translating Logical Address

75


80286 Privilege Level

76


80286 Privilege Level

77

0 0 Kernel Level

(highest)

0 1OS Service

1 0OS

Extension

1 1Applications

(Lowest Privilege Level)


Descriptor Table

GDT and LDT

78


Descriptor Table: GDT,LDT A segment cannot be accessed, if its descriptor does not exist in

either LDT or GDT. Set of descriptor (descriptor table) arranged in a proper sequence

describes the complete program. Each Descriptor is 8-byte long

79


Descriptor Table The descriptor is a block of contiguous memory location

containing information of a segment, likei. Segment base addressii. Segment limitiii. Segment typeiv. Privilege level – prevents unauthorized access v. Segment availability in physical memoryvi. Descriptor typevii. Segment use by another task

80


Descriptor Table The GDT contains information about segments that are global in

nature, that is, available to all programs and normally used most

heavily by the operating system.

The LDT contains descriptors that are application specific.

A global descriptor might be called a system descriptor, and local

descriptor an application descriptor The global descriptor table’s base address is stored in GDTR The local descriptor table’s base address is stored in LDTR

81


Differentiate GDT and LDT LDT, Local Descriptor Table, acts similar to GDT, which also saves

segments descriptor. The main differences between GDT and LDT is:

1. GDT have only one copy in system while LDT can have many2. GDT may not changed during execution which LDT often changes when

task switches3. Entry of LDT is saved in GDT. 4. Entries in GDT and LDT have the same structure.

82


Data or Code Segment Descriptor

83

Access Rights Byte



84

7 6 5 4 3 2 1 0

P DPL S E ED/C R/W A

TYPE

P=0: Descriptor is undefined, no mapping to physical memory exists

P=1: Valid Descriptor info, Segment is mapped into physical memory



85

7 6 5 4 3 2 1 0


Sets the Descriptor Privilege Level (DPL) necessary for protection

S=0: System descriptor(GDT)S=1: Application Descriptor(LDT)



86

7 6 5 4 3 2 1 0


ExecutableE=0: Data SegmentE=1: Code Segment

TYPE



87

7 6 5 4 3 2 1 0


TYPE

Expansion Direction: Data Segment {when E=0}ED=0 Segment expands upward (Data segment)ED=1 Segment expands downward (Stack Segment)

Conforming: Code Segment {when E=1}C=0 Ignore DPLC=1 Code segment will only be executed when

CPL > DPL


Data /Code Segment Descriptor

88

7 6 5 4 3 2 1 0


Write : Data Segment W=0 Data segment not writableW=1 Data segment writable

Read : Code Segment R=0 Code Segment execute only, not readable R=1 Code Segment both executable & readable


Data /Code Segment Descriptor

89

7 6 5 4 3 2 1 0


AccessedA=0 Segment not accessedA=1 Segment has been accessed


80386

90


Introduction : 80386 Enhanced version of the 80286 microprocessor 32-bit processor

• i.e 32-bit data bus, 32-bit registers, 32-bit address bus

Addressable physical memory is 232= 4GB 80386 CPU supports 16k of segments, thus total virtual memory

space = 4GB * 16K = 64TB The 80386 memory manager is similar to the 80286, except the

physical addresses generated by the MMU are 32 bits wide instead of 24-bits.

The concept of paging is introduced in 80386

91


Introduction : 80386 386 was capable of performing more than five million instructions

every second (MIPS) 80386 support three operating modes:

1. Real Mode (default)2. Protected Virtual Address Mode (PVAM)3. Virtual Mode

The memory management section of 80386 supports virtual memory, paging and four levels of protection.

The 80386 includes special hardware for task switching.

92


80386 Architecture

93


80386 Architecture

94


80386 Architecture The Bus Interface Unit connects the 80386 with

memory and I/O. Based on internal requests for fetching

instructions and transferring data from the code pre-fetch unit, the 80386 generates the address, data and control signals for the current bus cycles.

95


80386 Architecture

96


80386 Architecture The code pre-fetch unit pre-fetches

instructions when the bus interface unit is not executing the bus cycles.

It then stores them in a 16-byte instruction queue for decoding by the instruction decode unit.

97


80386 Architecture

98


80386 Architecture The instruction decode unit translates

instructions from the pre-fetch queue into micro-codes.

The decoded instructions are then stored in an instruction queue (FIFO) for processing by the execution unit.

99


80386 Architecture

100


80386 Architecture Execution unit has 8 General purpose

registers which are either used for handling data or calculating offset addresses.

The execution unit processes the instructions from the instruction queue.

It contains a control unit, a data unit and a protection test unit.

The barrel shifter increases the speed of all shift and rotate operations.

101


80386 Architecture

102


80386 Architecture The segmentation unit calculates and

translates the logical address into linear addresses at the request of the execution unit.

103


80386 Architecture

104


80386 Architecture The translated linear address is sent to the

paging unit. Upon enabling the paging mechanism, the

80386 translates these linear addresses into physical addresses.

If paging is not enabled, the physical address is identical to the linear address and no translation is necessary.

105


80386 Architecture

106



107



108



109

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

VM RF

Virtual Mode EnableWhen VM=1; 386 will switch from Protected to virtual mode

Flag Register



110

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

VM RF

Resume Flag• It is used in conjunction with the debug register breakpoints. • When RF is set, it causes any debug fault to be ignored on the next

instruction. • RF is then automatically reset at the successful completion of every

instruction.


Operating Modes of 80386

111


Operating Modes of 803861. Real Address Mode

2. Protected Virtual Address Mode(Non-Paged Mode)

3. Virtual Mode (Paged Mode)

112


Operating Modes of 80386Real Address Mode When 80386 resets, the initial operating mode is Real Address Mode In real address mode, 80386 works as a fast 8086 with 32 bit registers

and data types. Real-address mode is in effect after a signal on the RESET pin. Even if the system is going to be used in protected mode, the start-up

program will execute in real-address mode temporarily while initializing for protected mode.

The addressing techniques, memory size, interrupt handling in this mode of 80386 are similar to the real addressing mode of 80286.

In real address mode, the default operand size is 16 bit but 32 bit operands and addressing modes may be used with the help of override prefixed instructions.

Maximum physical memory = 1Mega byte (1MB)

113


Operating Modes of 80386 :PVAM MMU operates similar to 80286. Virtual addresses are represented with a selector component and an

offset component. The selector component is used to index a descriptor in a descriptor

table. The descriptor contains the 32 bit physical base address for the

segment. The offset part of the virtual address is added to the base address to

produce the actual physical address. The offset part of a virtual address can be 16 or 32 bits so segment

can be as large as 4 gigabytes. Hence the virtual memory size is 64 Terabytes.

114


Operating Modes of 80386 :PVAM Advantage of segmentation of memory: Segments corresponds to

code and data structures in the program. Hence segmentation is

useful.

Limitation of segmentation of memory: If we need only a part of

memory, even then we have to swap the whole segment content.

This will increase the time for execution.

115


Operating Modes of 80386 :PVAM

116

Memory Access in PVAM


Operating Modes of 80386:VMVirtual Mode (Paged Mode) In virtual mode, 8086 can address 1Mbytes of physical memory

that may be anywhere in the 4Gbytes address space of the protected mode of 80386.

In this mode, instead of segments, 4 Kbytes of fixed page length are used.

117


Operating Modes of 80386:VMTotal m/m available for paging = 1MB = 1024KB

Size of one page = 4KB

How many pages can be addressable with 1MB of memory?

Total pages= 1024KB/4KB = 256 pages(4KB each)

Paged Mode

Limitation : Pages do not correspond to the logical structure of the program.

Advantage : Pages can be quickly swapped.

118


80386 Memory Access in Virtual Mode

119


Memory Access in Virtual Mode

120


Operating Modes of 80386:VMPage Directory EntryEach directory entry is of 4 byte

121


Operating Modes of 80386:VMPage Table EntryEach directory entry is of 4 byte

122

• Read/Write and User/Supervisor are both used in the protection scheme.

• Both bits combine to develop paging priority level protection for level 3, the lowest user level.



123

P: Present bit• If logic 1 indicates that the entry can be used in address

translation. • If P = 0, the entry cannot be used for translation. • When P = 0, the remaining bits of the entry can be used to

indicate the location of the page on the disk memory system.



124

D: Dirty bit • Dirty bit is set before any write operation to the page. • Dirty bit is undefined for page directory entries. A :Accessed bit A = 0 page is not accessed A = 1 page is accessed


Page Translation Mechanism in 80386

125


Page Translation MechanismFormat of Linear AddressA linear address refers indirectly to a physical address by specifying a page table, a page within that table, and an offset within that page

126


Page Translation MechanismPage Translation

127

Enables processor to translate linear addresses into physical addresses by locating the page directory and page tables for the current task


Page Translation MechanismPage Translation

128

Here processor converts the DIR, PAGE, and OFFSET fields of a linear address into the physical address by consulting two levels of page tables.


80486

129


Features of 80486 The 32-bit 80486 is the next evolutionary step up from the 80386. 40 million instructions per second (MIPS) and offered roughly twice

the performance of the 386. Clock speed: 100-133MHz Efficient pipelined architecture significantly reduces execution speed. One of the most obvious feature included in a 80486 is a built-in

math coprocessor(FPU unit). This coprocessor is essentially the same as the 80387 processor used

with a 80386, but being integrated on the chip allows it to execute math instructions about three times as fast as a 80386/387 combination.

80486 is an 8Kbyte code and data cache.

130


Features of 80486 To make room for the additional signals, the 80486 is packaged in

a 168 pin. A new feature found in the 80486

1. BIST (built-in self-test) that tests the microprocessor2. 8KB Code and data cache3. On-chip FPU(Floating Point Unit)

131


Pentium

Architecture and versions

132


Features : Pentium Processors It consists of all the features that 80486 has. The additional enhancements that Pentium provides are:Wider data bus width : It has 64 bit data bus and 32 bit address bus. It allows 8 byte of data info to be transferred to and from memory.Improved Cache Structure: Cache is organized in a 2 way set associate cache with 32 byte line. The Pentium processor has two separate 8-kilobyte (KB) caches on

chip, one for instructions and one for data.

133


Features : Pentium Processors Faster floating point unit : The floating point unit has been completely redesigned over 80486. Faster algorithms provide up to ten times speed – up for common

operations including add, multiply etc.Branch prediction logic: The Pentium uses technology called branch prediction. To implement this Pentium has two pre-fetch buffers, one to pre-

fetch code in linear fashion, and one that pre-fetches code according to the Branch Target Buffer (BTB).

Therefore, needed code is almost pre-fetched before it is required for execution.

134


Features : Pentium Processors Data Integrity and Error Detection: Data parity checking is byte-by-byte basis. Address parity checking has also been added. Super Scalar Architecture : Processor is capable of parallel instruction execution of multiple

instructions are known as superscalar processors.Two parallel integer execution unit : It allows the execution of two instructions to be executed

simultaneously in a single processor clock.

135


Features : Pentium Processors Functional Redundancy Checking: (provide maximum error detection) Two or more Pentium Processor can participate in functional

redundancy checking. One processor (the master) fetching the instruction and executes the

instruction in normal fashion. Other processor (the checker) (connected directly to the master

processor’s buses)verify correctness of master processor. Checker executes the instruction same as the master but doesn’t

drive the buses. Checker samples master’s output and compares the values with the

internal computed values. An error signal is asserted in case if mismatch occurs.

136


Comparison of different Processors

137

Parameter 8085 8086 80286 80386 80486 PentiumN-bit Processor (data bus) 8-bit 16-bit 16-bit 32-bit 32-bit 64-bitAddress bus 16-bit 20-bit 24-bit 32-bit 32-bit 32-bitAddressable Memory 64KB 1MB 16MB 4GB 4GB 4GB

Supports Paging NO NO NO YES YES YES

Max. Clock Speed(MHz) 2 10 25 30 33 66Support Virtual Memory NO NO YES YES YES YESSupport Segmentation NO YES YES YES YES YES

Support Cache Memory NO NO NO NO YES YESOperating Modes 1 2 3 3 3 3

Contains on-chip FPU NO NO NO NO YES YESSupports Instruction Queue NO YES YES YES YES YES

Introduced in Year 1976 1978 1982 1985 1989 1993

Supports Instruction Queue NO YES YES YES YES YES

Documents

[PPT]W5 of Computer Engineering (Why, What, When, Where, … · Web viewProf. Swati Sharma [email protected] Microprocessor & Interfacing - 2150707 Darshan Institute of Engineering