AM15540v4

D(5, 6, 7, 8)

G(4)

S(1, 2, 3)

FeaturesOrder code VDS RDS(on) max. ID

STLD257N4F7AG 40 V 1.1 mΩ 120 A

• AEC-Q101 qualified • Among the lowest RDS(on) on the market• Excellent FoM (figure of merit)• Low Crss/Ciss ratio for EMI immunity• High avalanche ruggedness• Wettable flank package

Applications• Switching applications

DescriptionThis N-channel Power MOSFET utilizes STripFET™ F7 technology with anenhanced trench gate structure that results in very low on-state resistance, while alsoreducing internal capacitance and gate charge for faster and more efficient switching.

Product status link

STLD257N4F7AG

Product summary

Order code STLD257N4F7AG

Marking 257

PackagePowerFLAT™ 5x6

dual side cooling

Packing Tape and reel

Automotive-grade N-channel 40 V, 0.82 mΩ typ., 120 A, STripFET™ F7 Power MOSFET in a PowerFLAT™ 5x6 DSC package

STLD257N4F7AG

Datasheet

DS12565 - Rev 4 - March 2019For further information contact your local STMicroelectronics sales office.

www.st.com

1 Electrical ratings

Table 1. Absolute maximum ratings

Symbol Parameter Value Unit

VDS Drain-source voltage 40 V

VGS Gate-source voltage ±20 V

ID(1)(2) Drain current (continuous) at TC = 25 °C 120 A

ID(1)(2) Drain current (continuous) at TC = 100 °C 120 A

IDM(2)(3) Drain current (pulsed) 480 A

PTOT(2) Total power dissipation at TC = 25 °C 158 W

TJ Operating junction temperature range-55 to 175 °C

Tstg Storage temperature range

1. Limited by package2. The value is rated according to Rthj-case bottom side.

3. Pulse width limited by safe operating area

Table 2. Thermal data

Symbol Parameter Value Unit

Rthj-c top side Thermal resistance junction-case top side 2.90

°C/WRthj-c bottom side Thermal resistance junction-case bottom side 0.95

Rthj-pcb(1) Thermal resistance junction-pcb 31.3

1. When mounted on an 1-inch² 2 Oz, Cu board, t ≤ 10 s

Table 3. Avalanche characteristics

Symbol Parameter Value Unit

IAVAvalanche current, repetitive or not repetitive (pulse width limited bymaximum junction temperature) 50 A

EASSingle pulse avalanche energy (starting Tj = 25 °C, ID = IAV,VDD = 25 V) 608 mJ

STLD257N4F7AGElectrical ratings

DS12565 - Rev 4 page 2/13

2 Electrical characteristics

(TC = 25 °C unless otherwise specified)

Table 4. On/off states

Symbol Parameter Test conditions Min. Typ. Max. Unit

V(BR)DSSDrain-source breakdownvoltage VGS = 0 V, ID = 1 mA 40 V

IDSSZero gate voltage draincurrent

VGS = 0 V, VDS = 40 V 1 µA

VGS = 0 V, VDS = 16 V, Tj = 125 °C(1) 300 μA

IGSS Gate-body leakage current VDS = 0 V, VGS = 20 V 100 nA

VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA 2.0 4.0 V

RDS(on)Static drain-source

on-resistance

VGS = 10 V, ID = 60 A 0.82 1.1mΩ

VGS = 6.5 V, ID = 60 A 3.1 4.8

1. Defined by design, not subject to production test.

Table 5. Dynamic

Symbol Parameter Test conditions Min. Typ. Max. Unit

Ciss Input capacitance

VDS= 25 V, f = 1 MHz, VGS = 0 V

- 5400 - pF

Coss Output capacitance - 1870 - pF

Crss Reverse transfer capacitance - 45 - pF

Qg Total gate charge VDD = 20 V, ID = 120 A,

VGS = 0 to 10 V

(see Figure 13. Test circuit for gatecharge behavior)

- 66.5 - nC

Qgs Gate-source charge - 33.5 - nC

Qgd Gate-drain charge - 13 - nC

Table 6. Switching times

Symbol Parameter Test conditions Min. Typ. Max. Unit

td(on) Turn-on delay time VDD = 20 V, ID = 60 A,

RG = 4.7 Ω, VGS = 10 V

(see Figure 12. Test circuit forresistive load switching times andFigure 17. Switching time waveform)

- 28 - ns

tr Rise time - 19 - ns

td(off) Turn-off delay time - 58 - ns

tf Fall time - 32 - ns

STLD257N4F7AGElectrical characteristics

DS12565 - Rev 4 page 3/13

Table 7. Source-drain diode

Symbol Parameter Test conditions Min. Typ. Max. Unit

ISD(1) Source-drain current - 120 A

ISDM(1)(2) Source-drain current (pulsed) - 480 A

VSD (3) Forward on voltage VGS = 0 V, ISD = 90 A - 1.1 V

trr Reverse recovery time ISD = 120 A, di/dt = 100 A/µs,

VDD = 20 V

(see Figure 14. Test circuit forinductive load switching and dioderecovery times)

- 54 ns

Qrr Reverse recovery charge - 53 nC

IRRM Reverse recovery current - 1.9 A

1. Limited by package.2. Pulse width is limited by safe operating area.3. Pulse test: pulse duration = 300 µs, duty cycle 1.5%

STLD257N4F7AGElectrical characteristics

DS12565 - Rev 4 page 4/13

2.1 Electrical characteristics (curves)

Figure 1. Safe operating areaGIPG240420181309SOA

102

101

100

10-1

10-2

10-1 100 101

ID (A)

VDS (V)

tp =100 µs

tp =1 ms

tp =10 mssingle pulse

TJ≤175 °CTC=25 °CVGS=10 V

Operation in this areais limited by R DS(on)

Figure 2. Thermal impedance

GIPG240420181308ZTH

10 -1

10 -2

10 -5 10 -4 10 -3 10 -2 10 -1

K

tp (s)

0.05

Figure 3. Output characteristics

GIPG240420181307OCH

250

200

150

100

50

00 2 4

ID (A)

VDS (V)

VGS =5 V

VGS =7, 8, 9, 10 V

VGS =6 V

VGS =4 V

Figure 4. Transfer characteristics

GADG260720181336TCH

100

80

60

40

20

03 3.5 4 4.5 5 5.5

ID (A)

VGS (V)

VDS = 5 V

Tj = -55 °C

Tj = 25 °C

Tj = 175 °C

Figure 5. Gate charge vs gate-source voltage

GIPG240420181308QVG

12

10

8

6

4

2

00 20 40 60 80

VGS (V)

Qg (nC)

VDD = 20 VID = 120 A

Figure 6. Static drain-source on-resistance

GADG200620181612RID

0.9

0.8

0.7

0.60 20 40 60 80

RDS(on) (mΩ)

ID (A)

VGS = 10 V

STLD257N4F7AGElectrical characteristics (curves)

DS12565 - Rev 4 page 5/13

Figure 7. Capacitance variations

GIPG240420181307CVR

10 4

10 3

10 2

10 1 0 10 20 30 40

C (pF)

VDS (V)

CISS

COSS

CRSS

f = 1 MHz

Figure 8. Normalized gate threshold voltage vstemperature

GADG060820180915VTH

1.2

1

0.8

0.6

0.4

0.2-75 -25 25 75 125 175

VGS(th) (norm.)

Tj (°C)

ID = 250 µA

Figure 9. Normalized on-resistance vs temperature

GADG060820180915RON

1.8

1.6

1.4

1.2

1.0

0.8

0.6-75 -25 25 75 125 175

RDS(on) (norm.)

VGS = 10 VID = 60 A

TJ (°C)

Figure 10. Normalized V(BR)DSS vs temperature

GIPG240420181302BDV

1.06

1.04

1.02

1.00

0.98

0.96

0.94-75 -25 25 75 125 175

V(BR)DSS (norm.)

ID = 1 mA

Tj (°C)

Figure 11. Source-drain diode forward characteristics

GIPG240420181303SDF

1.0

0.9

0.8

0.7

0.6

0.5

0.410 30 50 70 90

VSD (V)

ISD (A)

Tj = -55 °C

Tj = 25 °C

Tj = 175 °C

STLD257N4F7AGElectrical characteristics (curves)

DS12565 - Rev 4 page 6/13

3 Test circuits

Figure 12. Test circuit for resistive load switching times

AM01468v1

VD

RG

RL

D.U.T.

2200μF VDD

3.3μF+

pulse width

VGS

Figure 13. Test circuit for gate charge behavior

AM01469v1

47 kΩ1 kΩ

47 kΩ

2.7 kΩ

1 kΩ

12 V

IG= CONST100 Ω

100 nF

D.U.T.

+pulse width

VGS

2200μF

VG

VDD

Figure 14. Test circuit for inductive load switching anddiode recovery times

AM01470v1

AD

D.U.T.S

B

G

25 Ω

A A

B B

RG

GD

S

100 µH

µF3.3 1000

µF VDD

D.U.T.

+

_

+

fastdiode

Figure 15. Unclamped inductive load test circuit

AM01471v1

VD

ID

D.U.T.

L

VDD+

pulse width

Vi

3.3µF

2200µF

Figure 16. Unclamped inductive waveform

AM01472v1

V(BR)DSS

VDDVDD

VD

IDM

ID

Figure 17. Switching time waveform

AM01473v1

0

VGS 90%

VDS

90%

10%

90%

10%

10%

ton

td(on) tr

0

toff

td(off) tf

STLD257N4F7AGTest circuits

DS12565 - Rev 4 page 7/13

4 Package information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,depending on their level of environmental compliance. ECOPACK specifications, grade definitions and productstatus are available at: www.st.com. ECOPACK is an ST trademark.

4.1 PowerFLAT™ 5x6 dual side cooling package information

Figure 18. PowerFLAT™ 5x6 dual side cooling package outline

8548760_2

Plated Area

STLD257N4F7AGPackage information

DS12565 - Rev 4 page 8/13

Table 8. PowerFLAT™ 5x6 dual side cooling mechanical data

Dim.mm

Min. Typ. Max.

A 0.66 0.71 0.76

A1 0.60 0.75

b 0.33 0.43 0.53

c 0.15 0.203 0.30

D 5.00 BSC

D1 4.06 4.21 4.36

D2 2.40 BSC

D3 2.80 3.30 3.80

E 6.00 BSC

E1 3.525 3.675 3.825

E2 1.05 1.20 1.35

E3 3.80 BSC

E4 4.20 4.70 5.20

e 1.27 BSC

I 0.15

L 0.15 0.25 0.35

L1 0.925 1.05 1.175

L2 0.45 0.575 0.70

ϑ 12° BSC

ϑ1 7° BSC

j 0.20 BSC

Figure 19. PowerFLAT™ 5x6 dual side cooling recommended footprint (dimensions are in mm)

STLD257N4F7AGPowerFLAT™ 5x6 dual side cooling package information

DS12565 - Rev 4 page 9/13

4.2 PowerFLAT™ 5x6 dual side cooling packing information

Figure 20. PowerFLAT™ 5x6 dual side cooling tape (dimensions are in mm)

8548087_REV1

Figure 21. PowerFLAT™ 5x6 dual side cooling reel (dimensions are in mm)

STLD257N4F7AGPowerFLAT™ 5x6 dual side cooling packing information

DS12565 - Rev 4 page 10/13

Revision history

Table 9. Document revision history

Date Revision Changes

02-May-2018 1 Initial release.

26-Jul-2018 2

Document status promoted from preliminary to production data.

Updated Table 4. On/off states.

Updated Section 2.1 Electrical characteristics (curves).

Minor text changes

6-Aug-2018 3

Updated Table 5. Dynamic.

Updated Section 2.1 Electrical characteristics (curves)

Minor text changes

21-Mar-2019 4

Modified Table 4. On/off states.

Modified Figure 1. Safe operating area, Figure 4. Transfer characteristics,Figure 6. Static drain-source on-resistance and Figure 9. Normalized on-resistance vs temperature.

Minor text changes.

STLD257N4F7AG

DS12565 - Rev 4 page 11/13

Contents

1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

4.1 PowerFLAT™ 5x6 dual side cooling package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4.2 PowerFLAT™ 5x6 dual side cooling packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

STLD257N4F7AGContents

DS12565 - Rev 4 page 12/13

IMPORTANT NOTICE – PLEASE READ CAREFULLY

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© 2019 STMicroelectronics – All rights reserved

STLD257N4F7AG

DS12565 - Rev 4 page 13/13