Embed Size (px)
Citation preview
Follow-Up Webinar:
Packaging and Substrate Workshop
Potential Collaboration
Opportunities
June 11, 2014
About iNEMI
International Electronics Manufacturing Initiative (iNEMI) is an industry-led
consortium of 110 global manufacturers, suppliers, industry associations,
government agencies and universities. A Non Profit Fully Funded by Member
Dues; In Operation Since 1994.
Visit us at www.inemi.org
5 Key Deliverables:
• Technology Roadmaps
• Collaborative Deployment
Projects
• Research Priorities Document
• Proactive Forums
• Position Papers
Mission: Forecast and Accelerate improvements in the Electronics
Manufacturing Industry for a Sustainable Future.
2014 Packaging & Substrate Workshop
• Summary of Workshop; Goals and
Agenda/Contents
• Brief look at key Gaps and Challenges from the
iNEMI and ITRS Packaging & Substrate Sections
• Key Collaboration Opportunities
• A Call to Action
3
Workshop Objectives
• Clear assessment of substrate and packaging technology capabilities and gaps.
– Example of iNEMI package roadmap were highlighted as below:
• 3DIC TSV & SiP related:
– Cost effective 2.1D/2.5D interposer technology
– High efficiency and multi task capable assembly and SMD equipment including WLP, FOWLP and SiP
– Wafer thinning technology for SiP
• EPADs Substrate related;
– Cost effective EPADs substrate/PCB
• Power Electronics related;
– High thermal conductive material
• Identify key areas where collaboration efforts are needed, supported and will deliver key learning and business impact.
• Feedback to iNEMI Package roadmap development
4
Day 1 Morning
5
08:15 Welcome tea and coffee
08:30 Welcome and Workshop introduction Bill Bader, iNEMI CEO
09:00 – 09:45 Current Technologies and Future Developments in Advanced Packaging
Rozalia Beica, Yole
09:45 ~ 10:15 Challenge of Packaging Technology in the Era of Cognitive Computer Yasumitsu Orii, IBM Japan
10:15 ~ 10:45 Challenges of Organic Substrates from EMS Perspective Weifeng Liu , Flextronics
10:45 ~ 11:00 Tea and coffee break
11:00 ~ 11:30 Key Technology Challenges in Computing Package and Assembly Kinya Ichikawa, Intel
11:30 ~ 12:00 Trends and challenges of electronic packaging for Huawei John Wen, Huawei
12:00 ~ 12:30 Trends of the Processor Module Packaging structure Masateru Koide, Fujitsu
12:30 – 13:15 Lunch Break
13:15 ~ 13:40 iNEMI Roadmap Highlight and Technology Gap (tentative) Bill Bottoms, PKG RM chair
13:40 – 14:05 Challenges to Consider in Organic Interposer HVM Tim Lenihan, TechSearch
14:10 ~ 14:35 3D package technologies review with gap analysis for mobile application requirements
Toshihiko Nishio, STATS ChipPAC
14:40 ~ 15:05 Expectation of embedded device technology and key challenging area Takashi Kariya, Ibiden
15:10 ~ 15:35 Tea and coffee break
15:35 ~ 16:00 The Requirements of Future IC Substrate, a Maker Point of View D.C. Hu, Unimicron
16:00 ~ 16:25 Development of Organic Multi Chip Package for High Performance Application
Shoji Watanabe, Shinko
16:30 ~ 16:55 Can we prepare organic materials for 2.1 D next generation interposers?
Hikari Murai, Hitachi Chemical
17:00 ~ 17:25 Substrate technology discussions of 2.1/2.5D IC packaging process Kazuaki Ano, Shinkawa
17:30 ~ 17:55 3D-IC standardization activity in Japan Haruo Shimamoto, SEMI
3DIC Co-Leader
17:55 ~ 18:10 Day 1 Wrap-up Bill Bader
18:15 ~ 21:00 Cocktail Reception and Networking
15 presentations Over the Full Day
Day 1 Afternoon
6
08:15 Welcome tea and coffee
08:30 Welcome and Workshop introduction Bill Bader, iNEMI CEO
09:00 – 09:45 Current Technologies and Future Developments in Advanced Packaging
Rozalia Beica, Yole
09:45 ~ 10:15 Challenge of Packaging Technology in the Era of Cognitive Computer Yasumitsu Orii, IBM Japan
10:15 ~ 10:45 Challenges of Organic Substrates from EMS Perspective Weifeng Liu , Flextronics
10:45 ~ 11:00 Tea and coffee break
11:00 ~ 11:30 Key Technology Challenges in Computing Package and Assembly Kinya Ichikawa, Intel
11:30 ~ 12:00 Trends and challenges of electronic packaging for Huawei John Wen, Huawei
12:00 ~ 12:30 Trends of the Processor Module Packaging structure Masateru Koide, Fujitsu
12:30 – 13:15 Lunch Break
13:15 ~ 13:40 iNEMI Roadmap Highlight and Technology Gap (tentative) Bill Bottoms, PKG RM chair
13:40 – 14:05 Challenges to Consider in Organic Interposer HVM Tim Lenihan, TechSearch
14:10 ~ 14:35 3D package technologies review with gap analysis for mobile application requirements
Toshihiko Nishio, STATS ChipPAC
14:40 ~ 15:05 Expectation of embedded device technology and key challenging area Takashi Kariya, Ibiden
15:10 ~ 15:35 Tea and coffee break
15:35 ~ 16:00 The Requirements of Future IC Substrate, a Maker Point of View D.C. Hu, Unimicron
16:00 ~ 16:25 Development of Organic Multi Chip Package for High Performance Application
Shoji Watanabe, Shinko
16:30 ~ 16:55 Can we prepare organic materials for 2.1 D next generation interposers?
Hikari Murai, Hitachi Chemical
17:00 ~ 17:25 Substrate technology discussions of 2.1/2.5D IC packaging process Kazuaki Ano, Shinkawa
17:30 ~ 17:55 3D-IC standardization activity in Japan Haruo Shimamoto, SEMI
3DIC Co-Leader
17:55 ~ 18:10 Day 1 Wrap-up Bill Bader
18:15 ~ 21:00 Cocktail Reception and Networking
Day 2
7
8:15 Welcome Coffee
8:30 ~ 9:00 Day 1 Recap
9:00 ~ 11:00 Break out session (one group < 10 people) – Themes will be
determined after all inputs from Day 1
Group A: (Orii-san)
Group B: (Ichikawa-san)
Group C: (Nishio-san)
Group D: (moderator)
11:00 ~ 11:40 Present the Highlights from Each Group (10 min/ group)
11:40 ~ 12:00 Wrap-up Collaboration Plan; Workshop Feedback; Next Steps
Keys to Success; Your Role
• Key outcomes will be prioritized key gaps and collaboration
opportunities.
• Keep that goal in mind throughout the 1.5 days
• We have a GREAT collection of industry expertise and
leadership participating in this workshop
• Keys to success for all people will be to both listen and to
provide inputs.
• Success will be best realized when we have a total supply
chain approach.
8
Substrate & Package Technology workshopApril 22-23, 2014
Gaps and Technical Limitations for
Future Packaging Requirements
Presented by:
Dr. W. R. Bottoms
The Most Important Part of our Work
Accurately predict Gaps and Showstoppers over a 10 year horizon
Recommendation of alternative strategies that may close these identified Gaps and resolve the difficult challenges before they become showstoppers
These tasks are more challenging today than ever before due to demands for
revolutionary new Packaging Solutions
Substrate & Package Technology workshopApril 22-23, 2014
Forces Driving this Packaging Revolution
The impending end of Moore’s Law Scaling
Dominance of smart phones and tablets in electronics markets
The emergence of the Internet of Things
Movement of data, logic, and applications to the Cloud
Substrate & Package Technology workshopApril 22-23, 2014
The end of Moore’s Law is coming and Packaging is the only near term solution to
Maintain the pace of Progress
IoT With Trillions of Sensors
Medical
Industrial
Agricultural
????
IP Data Traffic Drives Network Requirements
Global IP traffic will pass 1.4 Zettabytes (1021) by 2017
Wireless traffic will surpass wired traffic by 2016
Smart phones will grow >80% CAGR
The number of mobile-connected devices will exceed the number of people on earth by the end of this year
The Yottabyte era is rapidly approaching
Substrate & Package Technology workshopApril 22-23, 2014
Requirements To Support This View Of The Future
High bandwidth density
Low latency
Expanded data processing
Expanded data storage
Substrate & Package Technology workshopApril 22-23, 2014
Specific Gaps for Consideration by the Breakout Groups
Component substrates with improved thermal and electrical conductivity, greater wiring density and incorporation of photonic signals
Conductors with higher thermal and electrical conductivity and lower CTE
Low power, high density O to E conversion on package through sub-wavelength confinement of photon energy
Cost reduction in assembly and packaging
Outcomes of 3 Breakout
Groups Follow
Team A
Long Term Integration &
Miniaturization
Team A participants
• Yasumitsu Orii – IBM
• Gori Yoshinori – Alent and Alpha Metals
• Bill Bottoms – 3 MTS
• Norihiko Ikai – NGK
• Toshitake Seki – NGK
• Kazuaki Ano – Shinkawa
• Bill Bader – iNEMI
19
Problem Statement
20
The explosive growth of the cloud and the data and processing
needs drive the need for very high density and very low power
computer systems
Group Target : 10um pitch to realize super parallel processing, at
very low power (high conductivity)
• Current capability best case at 50 um pitch substrates
21
The oceans of data to be produced in the world
The size of data generated per Day in 2010 is “1ZB”,
which is equal to 2.7 trillion years News Paper Data.
Inte
rn
et
Com
pu
ter
Tel
eph
on
e
Prin
tin
g
Pap
er
Cave P
rin
tin
g
M.Kitsuregawa, J.IEICE, Vol.94, No.8, 2011
Massive Demand Growth Info-Plosion
2222
3 40
zettabytes zettabytes
2012 2020
Source: IDC Digital Universe
Data volume is increasing !
2323
11 42% %
2005 2020
Ratio of the data generated by sensors
Source: IDC Digital Universe
Big data to be accelerated by IoT
Equipment/Process/Materials Challenges
24
5 u pillars and 5 u spaces requires 0.5um accuracy of TCB equipment
and process.
Also requires Low Temperature Bonding
– Sintering Method using Cu Nano Particle a possible option
with tailored Youngs Modulus
– Control porosity level
Low CTE Interposer will be mandatory. Optional approaches as a
starter:
– Glass Interposer (CTE Tailored)
– Alternative Cu line
Vibration Sensitivity for machines and factory will be key at this level
– Factory floor
– Back end machines and automation
Inspection and Test capabilities for ultra fine pitch also must be studied
and established
Team B
Substrate
Team B participants
• Ichikawa / Intel
• Dyi-Chung Hu / Unimicron
• Shimamoto /AIST
• Torii / NGK spark plug (NTK)
• Nagatomo / Hitachi Metals
• Nishimura / Ajinomoto
• Watanabe / Shinko
• Kurihara / Mitsui Mining and smelting
• Tsuriya/ INEMI
Problem statement
• There is no clear cost effective CPU and next generation
high speed I/O memory interface substrate solution.
– This is coupled by an apparent major investment
needed in equipment for future substrate generations
Current situation
• Technology needs to be ready in next two-three years including
material for 2 um line & space.
– Use dry process pending investment
• The working team short listed the technology options for process /
material and equipment to enable 2/2 then 1/1 micron line & spacing
– Clean room, Litho, sputter, CMP, Excimer laser
– Tools are expensive and ramping for HVM challenging
– Need to invest for the next step
– Cost effective solution needed. Demand will support the
investment
Level set Case study
CPU / Memory Integration
- Required Localized Hi density interface
Key Challenges: 1) Signal Integrity
• Precise performance metrics need to be defined
• Low power and ultra high bandwidth needed
• Cost effective solutions need to be identified and then developed
through collaboration
• Trade off for performance and cost
– Rough design rule+ additional layer stack
– Fine design rules + fewer layer stack
• New materials likely needed to minimize warpage and maximize
electrical conductivity.
2.) Substrate equipment environment
• Substrate large panel process can be cost effective
– But must develop CMP, sputtering and likely clean
room.
– Cost effective solution
• Cost competitive with existing build up substrate long
term solution (>5 years target)
• Starting hi-end and increasing the volume for future
Top priority Key Challenge Area
• Material development
– Collaborate to develop material and process priorities and
jointly evaluate / narrow down options
– Example
• Filler loading material vs non filler material
• Photo definable vs Laser drilling
• Liquid vs film
• Low DK, Hi DK
• Integrated passives
Summary of Goals and Objectives
– Define the targeted design rules, performance and
cost targets for organic substrate
– Collaborative team to utilize the iNEMI platform to
develop material and process requirements & priority.
– Then jointly evaluate / narrow down options
Team C
Warpage
Team C participants
• Nishio-san (STATSChipPAC)
• Tokuyama (Towa)
• Shimizu (Dow)
• John Wenxiao (Huawei)
• Liu (Flextronics)
• Koide (Fujitsu)
• Lenihan (Techsearch)
• Fu (iNEMI)
36
Warpage Problem Statement(s)/Concerns
• Concerns & Issues, the list is long and challenging
– Some material behavior is not clear - mold problem
– Plated copper onto substrate may cause internal stress
– JEDEC spec is not adequate: Categorizing packages size
(>15mm or < 15mm) into only 2 groups is too general. Need
more detailed categories
– Warpage correlation with long term reliability studies lacking
– Key factors to warpage should be understood by package type
– Variation of warpage measurement data: different lot, locations
on the panel also needs to be understood
– Warpage failures due to double reflow are reported - to be
investigated
– 80% PoP failures reported (not verified) to come from warpage
37
Proposals
1. First to review the previous/existing work at iNEMI on warpage –
iNEMI to organize a webinar to communicate
2. Two potential areas for study
a) Design experiment to collect reliability data of different package sizes
and/or types
• Ideally use dummy design to obtain repeatable warpage data
• Correlation between component warpage and 2nd level reliability
• Categorize packages in more detail, e.g. Pkg size (10, 20, 30, etc), solder ball size,
solder pitch, solder material, over mold
• Give recommendations to spec update based on the experiment output
b) Need to understand the factors that cause warpage, e.g. design
dependent, copper traces, vias, thermals
• Refer to output from iNEMI project on Primary Factors to warpage
• Select appropriate package type
• Design experiment to investigate the impact of key factors
38
Summary
• Three High Impact Areas Explored
– Break away miniaturization focus
– Cost Effective substrate solutions to CPU/Memory interface
– Warpage at 2nd level interconnect
• We are communicating needs and opportunities internally within the iNEMI membership
• Call for engagement webinar requests your participation
Please contact:
…with your interest
39
