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Organic Packaging Substrate Workshop Overview

Organized by: International Electronics Manufacturing Initiative (iNEMI)Mario A. BolanosNovember 17-18, 2009

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Organic Packaging Substrate WorkshopWork Shop Coordination Team

–Jie Xue Cisco–John Savic Cisco–Hamid Azimi Intel–Charan Gurumurthy Intel–Kazuko Inaba Intel–Mario Bolanos TI–Luis Rivera TI–Bob Pfahl iNEMI–Haley Fu iNEMI

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Organic Packaging Substrate WorkshopSpeakers and Companies

–Jie Xue Cisco–Hamid Azimi Intel–Hirofumi Nakajima NEC–Luis Rivera TI–Bernd Appelt ASE–JaeYoon Kim Amkor–Kenny Lee STATS ChipPAC–Masaru Takada Ibiden–Koichi Nonomura Kyocera–Kozo Yamasaki NTK–Steve Yang NanYa–Richard Sheridan UMTC

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A CASE FOR ACTION

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Organic Substrate – Potential show stopper?• ITRS Assembly and Packaging Difficult Challenges

(>32nm) – Near Term– Close Gap between Chip and Substrate – Improved Organic

Substrate (increased wire ability at low cost; increased via density in substrate core ….)

• ITRS Assembly and Packaging Difficult Challenges (<32nm) – Long Term– Package Cost Does not follow the Die Cost Reduction Curve

(increased device complexity requires higher cost packagingsolutions) – Substrate cost is >> 50% of total package cost

• iNEMI 2007 Roadmap Organic Substrate Research Needs– High performance laminates that are competitively priced: low

dielectric constant; low loss

• iNEMI 2007 Roadmap – Identified Gaps and Showstoppers– The major showstopper affecting the interconnect industry is the

precipitous decline in substrate R&D investmentSource: Mario A. Bolanos, Packaging Technology Challenges for Future CMOS Cu Ultra Low K Devices, IMEC October 2007

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Anantha Chandrakasan

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Work Shop Objectives• Main Objectives:

–Identify gaps in organic substrate technology that need to be addressed to facilitate the continued advancement of electronics packaging.

–Identify issues and needs that are potentially best solved by consortium activities.

–Set the priorities and direction for future collaborative efforts on organic packaging substrates.

–Form action groups to execute the required industrial collaborative programs.

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Packaging Assembly

Companies

SubstrateProviders

OEMs and ICCompanies

Organic Substrate Technology Gaps

and Roadmap

R&D Pre-Competitive Collaboration Model

Collaboration

iNEMI Provides the Opportunity for International Consortia Collaboration

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R&D Pre-Competitive Collaboration ModelNTK

UMTCNANYA

KYOCERAIBIDEN

Organic Substrate Suppliers

Substrate Focus

STATSChipPAC

AMKOR

ASE

Packaging Assembly HousesPackaging Focus

NECCISCO

TEXAS INSTRUMENTS

Future Products and Packaging Technology Roadmap Requirements• Microprocessor - FCBGA• Portable Handset –FCCSP and POP• Networking Products• Minimize High Temp. Package Warpage

Required Organic Substrate and Packaging Technology Needs to Support New Products• Assembly Challenges using Organic Substrate Technology• Advanced Package Solutions for Graphics and Chipset • Mobile platform packaging challenges

Organic Substrate Technology Roadmap to Support Future Packaging Technology• Strip format CSP/POP applications• Large body organic FCBGA• PBGAs and strip format CSPs• Small/mid body size FCBGA organic, CSP/POP• Low inductance embedded capacitance Technology

INTEL

OEM’s and ICCompanies

Product Focus

OEM’s and IC Companies

PackagingHouses

SubstrateSuppliers

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Key Themes and Focus• Three key themes were identified as a means to guide speakers in preparing their presentations. –Aligning Substrate Roadmaps and Bridging

Gaps–Standardized Evaluation of Key Substrate

Performance Outputs and Reliability–Priorities for Consortia Activities

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Key Themes and FocusAligning Substrate Technology RoadmapsGeneral needs: • Finer lines and spaces, PTH/via pitch, meet iNEMI roadmap• Cost parity and/or immediate cost effectiveness for new technologyFC-CSP/POP:• Warpage on POP applications - understanding interactions with assembly processes and mold materials• Standardization of pad surface finish• Speed of time to entitlement of yield and cost with advanced design rules (<20/20 um)• Roadmap and implementation plan for 15/15um line/spaces• Inspection (AVI) and Test

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Key Themes and FocusAligning Substrate Technology RoadmapsFCBGA:• Minimizing package inductance: enabling reliable thin substrate technology and

fully stacked micro-via interconnects for large package size applications.• Manufacturing strategy for thin core and core-less.• Advanced materials/processes: Lower loss, improved impedance control, lower

CTE mismatch, and improved reliability.• Warpage minimization with thin core and large body size packages.• Embedded actives/passives: Current capability for core power decoupling, test

challenges.• With the emergence of 3D TSV stacking products, what is the organic substrate

roadmap to accommodate TSV stacked modules and potential new key challenges (e.g. power dissipation).

• Larger package size roadmap for CMOS 28nm nodes and beyond.• What are the realistic limits from manufacturability, warpage, etc. of package

body sizes larger than 55mm organic?. • Package level EMI shielding.

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Key Themes and FocusStandardized Evaluation of Key Substrate Performance Outputs and Reliability:

–Convergence of materials and processes.–Measurement and reporting of key substrate

electrical. –Performance attributes.–Reliability testing and process characterization.–Balancing convergence strategies for high

volume with adaptability for low volume.–Speed of process yield entitlement.

Consortia Activities:–Areas of engagement and collaboration.

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Organic Substrate Technology R&D NeedsResearch Needs• High performance laminates, with low

dielectric constant, low loss that are competitively priced.

• Integral materials for resistors, capacitors, inductors.

• Self reinforced materials.• Liquid crystal polymer compatible with

current PCB manufacturing.• New non-contact testing techniques.• Boards without surface finishes.• Improved dimensional stability materials• Waveguide materials and manufacturing

techniques.• Alternate patterning processes

(imprinting, inkjet printing, mask less patterning).

• Non solder based interconnects.• Novel lower cost materials and high

output, high yield processes

Development Needs• Microvia technology improvement.• Microvia metallization.• Continuous cycle time reduction for

quick turn substrates.• Flexible circuit quick turn facilities.• Improved design tools for emerging

technologies like embedded passives and optoelectronics PCB’s.

• Layer alignment accuracy.• Finer line and space development.• Improved drilling for less roughness

and less run out.• Pad surface finish alternatives• Flip Chip pad design for non solder

bump interconnect. • Silicon carriers development. • Fast time to yield entitlement with new

advanced design rules.

Source: iNEMI Roadmap

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Major Opportunity for Improvement – NOW! • Faster time to process yield entitlement when new

substrate technology and design rules are implemented– Speed of yield entitlement and sustaining high yields over time is a major

concern. It affects substrate cost, capacity, cycle time and time to market. – To be cost competitive, substrate process yields at high volume need to be

in the 90’s– Time to yield entitlement from prototypes to high volume needs to improve

to only a few months vs. several quarters.• This issue if not addressed will continue to get worst as we continue to stretch

current technology to its limits– Product development methodology, process, material and production

equipment selection need to include high process yield requirement – As new substrate technologies and design rules are implemented, in

addition to process and manufacturing improvements there is a need to develop better final substrate inspection and testing capabilities.

• Automatic Visual Inspection (AVI) and Open and Short (O/S) Test capabilities need to be developed

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Organic Substrate Technology Gaps and Roadmap Requirements

Thermo MechanicalProperties

ChemicalProperties

ElectricalProperties

High Yields andManufacturability

Optim

ization

Innovations – Breakthroughs – Cost CompetitiveFuture Substrate Technology

New

Materials

New

ProcessesWhat are the limits of current technology?

Where can current technology stretch to?

Higher Levels of IntegrationHigher wiring densityHigh freq,/performance

More MiniaturizationThinner and smaller packages Higher thermal dissipation

Cost Competitive$$$

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I applaud all companies that are here today for supporting this initiative to work together to address an industry level priority in a cooperative pre-competitive R&D model. This is a new model and potentially the beginning of a new era in our industry.

Thank You