3D-IC Standardization Activity in Japan - INEMIthor.inemi.org/webdownload/2014/Substrate_Pkg_WS_Apr/15_AIST.pdf · 3D-IC Standardization Activity in Japan April 22, 2014 ... ・Mashiro

SEMI Standards Japan Packaging Committee, 2014

3D-IC Standardization Activity

in Japan

April 22, 2014

Haruo Shimamoto

SEMI Japan 3DIC Co-Leader

1


SEMI 3DS-IC Standards Committee

• To explore, evaluate, discuss, and create consensus-based specifications, guidelines, and practices that, through voluntary compliance, will;– promote mutual understanding and improved

communication between users and suppliers of 3DS-IC materials, carriers, automation systems and devices, and

– enhance the manufacturing efficiency and capability and shorten time-to-market so as to reduce manufacturing cost in the 3DS-IC industry.

Charter

2


3DS-IC Organization

North America

Formed Fall 2010

Taiwan

formed Jul.2011

3


4

SEMI Japan/ 3D-IC Study Group

• Understand and track the progress of the taskforce activities at SEMI

N.A. and Taiwan 3DS-IC committees.

• Form the taskforce teams in Japan to meet the members’ needs and

expectation for SEMI Japan members.

Scope

• Determine the area for standard creation to be formed the taskforce team.

– Include the significant reason for the taskforce team formation

– Clarify the benefit of taskforce team in Japan to the members

• Help the preparatory taskforce team meeting to smoothly launch the

discussion.

• Share SEMI standard activities to the Japan members via conferences or

workshop

• Bring more participants from the 3D-IC companies and related equipment/

test makers

Charter


3D-IC Organization in Japan

Approved for

#5691 Standard

Thin Die Handling TF

Start from Apr.2014

SEMI Japan

Packaging Committee

3D-IC Study Group Thin Die Bending Strength

Measurement TF

・Mashiro Tsuriya (iNEMI)

・Haruo Shimamoto (AIST)

Formed Oct.2012

Mar.2013~Apr.2014

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1. Purpose: To measure easily for ultra-thin die especially

less than 50um

2. Proposal: Use the cantilever bending method for

die bending test

3. Reason: 3 point bending method (SEMI G86-0303) is not

convenient because of narrow span(L≦2mm).

And when L becomes wider, die curves larger.

Thin Die Bending Strength measurement method TF

10μm

Die

Non-Broken

6


b Die Width

h

Die

Thickness

PB

Applied

Force at

Break(N)

L Span (=X )σ (MPa) =

3PBL

2bh2

Cantilever Beam

3 Point Bending

Calculation

Cantilever Bending Method

σ (MPa) =

6PBL

bh2

σ : Flexural Stress-2

0

2

4

6

8

10

12

14

16

18

0 100 200 300 400

Applie

dForc

e(g

)

Bending Length (um)

10umｔ Die Measurement Data

Broken Force：15.46g

Bending

Region

Broken Point

Initial

Position

7


Dage 4000PlusDie

Tool

Stage

Measurement Outline

Tool

Stage

Die

Die Thickness

Measurement

Height：XX+

0.2mm

Cantilever Bending

TOOL Speed：5mm/min

Radius of Tool Edge:0.1mmΦ

8


（Measured @ Tohoku Univ. by Nano-

Indent Method under ASET “NEDO

Dream Chip-PJ” ）

Base Back-Ground of Cantilever Bending Method

Young Modulus is reduced under 50μm thickness.

⇒ Si Behavior is changed in this region

【Reference】K. Lee, S. Tanikawa, M. Murugesan, H. Naganuma, H. Shimamoto, T. Fukushima,

T. Tanaka, and M. Koyanagi, “Degradation of Memory Retention Characteristics in DRAM Chip by Si

Thinning for 3-D Integration,” IEEE Electron Device Letters, Vol.34, pp.1038-1040, No.8, Aug.2013

3 Points Bending Region

Cantilever Bending Region

9


X-Ray View of Test Die with TSV

（Photo by Dage XD7600NT Diamond）

SiN

BumpA

B

Si=50um

240MPa

150MPa

Die Broken Part

Wide IO TEG from Renesas

Before Test After Test

10

Depend on the TSV Layout and Bending Direction


Via First Via Middle Via Last

MEOL: TSV Thinning, RDL, Bumping, Wafer Test

2.5D/3D Supply Chain11

・Many Interface are existent

・Who control the supply chain？

+ Business

Owner


12

① Information of manufacturing process, device design rule

and quality control points should be correctly transmitted

between supply chains.

⇒ Process matching between manufacturer interface

・Alignment Mark from FE ~ BE process, Package & Test

⇒ Incoming/Outgoing Inspection Items & Metrology

・Defect Inspection method, tool, equipment

⇒ Handling method between manufacturer interface

・Shipping Carrier, Tray, Container

② Characteristic models (electricity, heat, stress) of TSV is

important for 3D-IC design.

⇒ Measurement method of Device L,C,R parameter

⇒ Matching of signal transmission Interface level

⇒ Circuit Modeling including LSI-Package-Board

What to be Standardized ?


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■Basic approach

・Establish and standardize of TSV ElectricalCharacteristic Measurement method toextract PDK for LSI Designing

■2014Submit to IEC

■Validation of 2.5D/３D Electrical Performance

Logic

Memory 1

Memory 2

Performance

3D Model

・Standardize of Chip-Chip Interface・Validation by Simulation・Validation by Experiment of actual device

■2015~Submit to IEC

Logic Memory 1 Memory 2

Performance

2.5D Model for TSV

Interposer

JEITA 3DIC Activity

Logic Chip IF＜Physical Image＞

Substrate


When TSV interval is very

near,

coupling model

Is recommended

Cox Cdep

RvCfr

Ch

Cl

Vch Vcl

TSV Electrical Characteristic Model

TSV Model Neighbor TSV

Fringe

Capacitance

Cox+Cdep

◆Circuit model ◆Capacitance definition

Vcc

Low Freq.

High Freq.

JEITA 3D Semiconductor Sub-Committee Proposal


Electrode

PWELL

P+

T

S

V

P sub

Tap

(GND)

Bump

AL

Si-IP

1st

2nd

◆Resistance measurement ◆Capacitance measurement

Terminal 1A Terminal 1B Terminal 2A Terminal 2B

2

12 RRRv

R2

R1

Terminal 1A Terminal 1B Terminal 2A Terminal 2B

Electrode

C1 C2

C2：Parasitic Capacitance

CCCv 1 2

TSV Electrical Characteristic Measurement


TSV Keep Out Zone （KOZ) Definition


C2C Process & Handling

●Wafer Process

●Foups Contain

●Top Bumping

●WSS Bond

●Back Side Grinding

●TSV Fabrication

●Bottom Bumping

●WSS Laser Scanning

●Dicing Tape Mount

●WSS Debond

●Dicing

●Pick Up/ Tray Contain

●C2C

●Tray Contain

●Underfill

●Tray Contain

●Underfill Hardening

●Tray Contain

●Electrical Test

●Tray Contain

●Vacuum Packing

●Packing/Outgoing

●Un-Packing

●Board Assembly

Tray ContainC2C

Top Bump

Si Wafer

TSVBottom Bump

Dicing Ring

Dicing Tape

Support Glass

Red Letter ： Wafer Handling

Red Letter ： Die Handling

Die Structure ： Single / Multi Stacked

17


Thin Chip Handling TF（<80umｔ）

Pocket Type Sticky Type A Sticky Type B

Conventional Chip Tray New Proposal Sticky Thin Chip Tray

①Outline Dimension ②Area of Adhesive Zone

③Conductive Resistance for ESD

④Die Adhesive Strength ⑤Surface Roughness etc.

18

Standardize Items


高さ40cmの場合

80cm Height Drop Test Data by Shin-Etsu Polymer

Sticky Type A Sticky Type B

with 80μmt

Insertion FilmConventional Tray

Thin Chip Drop Test Result （50μmt)19


20

・Many strong material & equipment Vendors

・Many SiP know-hows in semiconductor Manufacturer

3D-IC needs Virtual IDM Functions

In Japan

【Strong Points】

・Few strong semiconductor Manufacturer

【Weak Points】

New Frameworks

Standardization Situation in Japan

“ collaboration with National PJ”


21

mold resin

SoC

Wide-I/O memory

TSVsubstrate

[1] TSV formation:

- Via filling

- Front bump, Rear bump

[2] FC attach:

- Thin chip pickup&bonding

- UF formation (NCF/NCP)

[3] Test:

- Test methodology

- Microbump probing

[4] Thin wafer/chip handling:

- Temporary support attach

- Back Grinding

- Debond

- Gettering Effect

[5] Substrate/Assembly:

- Layer configuration

- Warpage control

- Molding for overhang

Total thickness

< 1.0mm

Issues of 3DIC and referred Organization

Testing TFMiddle End Process TF Wafer Bonded Stacks TF

Thin Wafer Handling TF（common）Inspection & Metrology TF

N

A

T

WN

A

N

A

T

W

Japan is planning to focus on Integration

Items through the 3DIC process


22

Automotive Obstruction

Sensing Device

Probe Data

Processing Device

Automatic Driving Assistance

Application Processor

・Achieve Energy Saving

・Establish Smart & Safety Society

Smart Device Project

Japan National Project from 2013 to 2017

High Band Width Data Transmission （2.5D/3D）


Content of Project23

Main Object Main Player

Automotive

Obstruction

Sensing

Device

①Enviroment：Under all weather including night time.

②Sensing Targets：Many kinds of obstructions

（Cars, Pedstrians, Bicycle etc.).

③Function：Real time Measurement about the position and

distance （≧20m） of several obstructions simultaneosly.

Denso

Lapis

AIST

Automatic

Driving

Assistance

Application

Processor

①Function：Recognize the vehicles and pedistrians,

and previously forecast their behavior.

②Action：Juge a rsik of a collosion in various traffic

enviroments to prevent the accident.

Renesas

Probe Data

Processing

Device

①Function：High speed and high volume data processing

which information is collected by neighboring vehicles.

Also makes communication with ADAS Highend Server System

in low power dissipation.

Fujitsu


New Frameworks for 3D-IC Standardization

ＮＥＤＯ

DENSO LAPIS AIST

Smart Device

Gr. STD.Gｒ

・Utilize the Smart Device PJ TEG for evaluation・Share the information and knowledge・Same Scheme is considered with JEITA for Electrical IF

Smart Device PJ

SEMI

GINTI

3D-IC TF

3D-IC SG

Support

Co-operation

Tohoku Univ.

24

（JEITA)

(3D SC)


25

Summary

1. SEMI 3D-IC SG & JEITA started Standardization TF.

2. To utilize Japan strong points, new frameworks is

going to be installed.

3. Smart Device PJ is one of moving force.

4. Keep more intimate relationship with other

International committee/ laboratory to expand 3DIC.

Documents

3D-IC Standardization Activity in Japan - INEMIthor.inemi.org/webdownload/2014/Substrate_Pkg_WS_Apr/15_AIST.pdf · 3D-IC Standardization Activity in Japan April 22, 2014 ... ・Mashiro