3D Package Technologies Review with Gap Analysis for Mobile Application Requirements

Apr 22, 2014STATS ChipPAC JapanT.Nishio

Confidential

Contents

• Package trends and roadmap update

• Advanced technology update

Fine pitch & low cost flip chip (fcCuBE®)

Wafer level package (eWLB)

Silicon level integration (TSV)

• Summary

Confidential

Contents

• Package trends and roadmap update

• Advanced technology update

Fine pitch & low cost flip chip (fcCuBE®)

Wafer level package (eWLB)

Silicon level integration (TSV)

• Summary

Confidential

Applications Driving Growth Through 2017

Gartner Webinar Semiconductor Forecast: Jun’13 Update

Mobile PC

2013-2016 Semi TAM Growth Differences

$0.3

$1.5

$2.6

$6.9

$4.8

$7.4

$10.3

$15.0

$0.0 $5.0 $10.0 $15.0 $20.0

Mili/Aero

Consumer

Wired

Auto

Storage

Industrial

Compute

Wireless

Source: Gartner, June’13

Confidential

Package Roadmap Update to Fill the Gaps

2012 2013 2014 2015 2016

eWLBGAP; Ball counts vs Size

FCBGA - LF Solder 2.5D/3D TSV Hybrid Memory Cube

fcFBGA PoP fcCuBE – PoPGAP; Flip Chip Cost

chip

WLCSPeWLB-3D

3D TSV

Application processor, Base band

RF, PM, WiFI, BT, GPS, etc

Network, PC, Game, DTV

Delayed one generation of Wide IOGAP; Power consumption vs Performance

GAP; Low profile to reserve more space

GAP; Dependency ofWide IO infrastructure

eWLB-3D F-t-F

GAP; Low profile

IPD/ Passive in eWLB

GAP Space/Performance

Cu-ColumnBump on Lead MUF /MR -> CUF / MR -> NPI / TCBGAP; Cost vs Density

fcCuBE

GAP; Cost reduction/ EM performance

eWLB‐PoP (1.5S)

Confidential

Contents

• Package trends and roadmap update

• Advanced technology update

Fine pitch & low cost flip chip (fcCuBE®)

Wafer level package (eWLB)

Silicon level integration (TSV)

• Summary

Confidential

Reduced Substrate Complexity• Majority of devices routable in 2-lyr laminate

using no-SOP/ BOL/open SRO design• Relaxed substrate des rules (SRO registration and

L/S) by virtue of Open SR design

Cu column bump & BOL Interconnection- A

• Dense routing w/ relaxed substrate design rules

• Dramatic reduction of ELK stress & elimination of ELK damage in Si

Enhanced Assembly• Hi throughput jet underfill

for fcBGA & Mold Underfill (MUF) for fcFBGA

• Wide boat format for fcBGA & 1-up high density matrix strip for fcFBGA

fcFBGA

Key Elements fcCuBE® Technology

®

Gap; Substrate cost, Under fill cost

Confidential

Further Enhancements of Cu pillar - Oblong Bump

80

16

30

1640

17um

25

25x50um Oblong Bump

33 20

80

14

40

40

13um

3340um Bump Diameter

Larger bump to trace spacing at a given pitch Larger Process window w/ respect to bump bridge

Benefits • Larger bump-to-trace spacing • More relaxed line width/spacing• Applicable to Mass Reflow (MR) & TC Bonding (TCB)• Larger solder cap volume Enhanced CA yield (non-wets) • Possibly improved EM performance • Possibly better ILD crack protection w/ increased UBM area

Gap; Bump pitch

Confidential

Coreless Embedded Trace Substrate (ETS)

• Cost reduction compared to normal pattern substrate – Mainly by elimination of PCF needed for SAP – Lower cost for conventional SAP design rules ( < 25/25um L/S)

• Flatter surface provides a better path for CUF or EMC flow under the die

• Thinner substrate

• Higher process margin with respect to bump-to-trace short– Leads to wider process window for fcCuBE & enables tighter bump pitch

• Currently in HVM – fcFBGA MUF

4L 1/2/1 Coreless 3L ETS

2L Conventional Coreless 2L ETS

BOL in ETSNormal BOL

Gap; Bump pitch, Chip Height4

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Stress Simulation – Bump Type & Design

• The thermal loading is from solder melting temp to room temp, then checked the maximum principle stress of the silicon

• Higher stress in Cu Column, but it can be reduced by BOL pad structure

4.0

4.5

5.0

5.5

6.0

6.5

7.0

7.5

8.0

8.5

9.0

Cu + Solder cap on BOC Cu + Solder cap on BOL Solder Bump on BOC Solder Bump on BOL

Max

Pri

ncip

le S

tres

s(10

^2 M

pa)

Die thickness: 150umLow CTE Core

S/M

Volume cross-section

Core

BOL

Bump

Cu column

Cu column

UBM

PassivationAL Pad

ELK

Die

fcCuBE: Preventing ELK Damage Gap; Ultra Low K damage

Confidential

Contents

• Package trends and Road map update

• Advanced Technology update

Fine pitch & Low cost flip chip (fcCuBE®)

Wafer level package (eWLB)

Silicon level integration (TSV)

• Summary

Confidential

What is eWLB ?

• Wafer Level Packaging technology that utilizes a well developed wafer bumping infrastructure with an innovative wafer reconstitution process to package Known Good Dice

• Uses mold compound to support the fan-out I/Os

• Fan-In Interconnects only - Number and pitch of Interconnects must be adapted to the chip size

• Only Single chip packaging solution

• Fan-out Interconnects - #, Pitch of Interconnect is INDEPENDENT of chip size

• Single/Multi/3D chip packaging solution

• Improved Yield with KGD

Fan-In WLP eWLB/Fan-Out WLPPKG size = Chip size PKG size > Chip size

eWLB expands the application spacefor Wafer Level Packaging!

chip chip

Gap; Die Size vs Bump Counts

Confidential

eWLB Positioning

chip

Over flip chip BGA (*1):• Slightly smaller footprint (clearance distances to the edges are smaller)• Thinner package• Substrate-less package (shorter interconnections meaning higher

electrical performance and cheaper in the long run)• Future potential for SiP and 3D integration• Lower thermal resistance• Simplified supply chain infrastructure• Lower cost until 12 mm size

Over fan-in WLCSP (*1):• Higher board-level reliability• Fan-out area to counter the pad limitation

issue, adaptable to customer needs• Only confirmed good dice are packaged• Built-in back-side protection• No restriction in bump pitch

Over FBGA (*1):• Slightly smaller footprint (clearance distances to the edges are smaller)• Better signal integrity and power integrity • Thinner package• Lower thermal resistance• Simplified supply chain infrastructure• Lower cost until 5 mm size

*1; Yole presented advantages of FO-WLP @ SEMI Networking Day:Packaging - Key for System Integration, Jun’13

Signal Integrity comparison for 10x9 mm eWLB vs 11x11 mm fcCSP

PkgCost

FBGA

FCCSP

eWLB

Pkg Size

Gap; Cost Performance

Confidential

Bottom View

Top View

eWLB PoP (eWLB + eWLB) Total PKG height ~ 1.3mm

Double-sided eWLB for 3D Packaging

Courtesy of 3D eWLB JDA

Gap; vs Embedded Substrate

Confidential

28nm ELK Device

Plated Cu RDL

Ultra fine pad pitch (<50um)

Advanced FO-WLP Technology

HVM from Q1 2012 for 40nmQualified 28nm devices

35m pad pitch

IPD, SMD/discrete embedding

EMC

IPD embedding0201 MLCC

Gap; vs Embedded Substrate

Confidential

eWLB : Themo-Moire, High Temperature Warpage Measurement

fcVFBGA,7x7mm, 191LD NSPPKG height 0.95 mm

Die 4.46 x 5.65 x 0.19 mm

eWLB 8x8mm, 182I/OPKG height 0.7 mmDie 5 x 5 x 0.45 mm

Gap; vs Flip Chip

Confidential

Presented in iMAPS Europe (MINAPAD) April 2012

eWLB-PoP Packages

0.8mm

Total PoPHeight

30% height reductionwith eWLB in 2012

40% height reductionin 2013

Gap; vs Flip Chip

12x12 mm eWLB-PoP14 x 14 mm eWLB-PoP

Confidential

Large Panel Carrier Manufacturing Technology

Panel

200 mm300 mm

1x 4 – 10 x2.2 x

Dramatic cost & throughput improvement with expanded carrier size

Starting(2009)

2010

Near Future

Gap; vs Embedded Substrate

Confidential

Contents

• Package trends and roadmap update

• Advanced technology update

Fine pitch & low cost flip chip (fcCuBE®)

Wafer level package (eWLB)

Silicon level integration (TSV)

• Summary

Confidential

TSV Ecosystem with Foundry & OSAT partnership

20

IDM& Foundry

Full-Turnkey

Open ecosystem collaborative approach drives proven and reliable 3D IC solutions for the semiconductor market by combining the foundry partner’s robust, leading-edge TSV FEOL with OSAT’s TSV MEOL & BEOL assembly technology.

VirtualTSV-ecosystem

TSV BEOLPackagingAssemblyTest

TSV MEOL

TSV Fab. Foundry

OSAT

Gap; Quality Owner

Confidential

DicingDicing

CtC BondingCtC Bonding

WideIO Memory WaferWideIO Memory Wafer

Underfill - NCPUnderfill - NCP

CtS BondingCtS Bonding

Grinding Grinding

DicingDicing

Underfill - NCPUnderfill - NCP

MoldingMolding

Ball MountBall Mount

Marking/SingulationMarking/Singulation

TestingTesting

MEOL TSV waferMEOL TSV wafer

Substrate

3D TSV IC

3D TSV IC

Wide IO MemoryChip-to-Substrate bonding

Chip-to-Chip bonding

TSV Assembly Process Flow – Example (3D IC TSV)

Thermocompression Bonding

Thermocompression Bonding

Gap; TCB cost

Confidential

40/50um bump pitch Chip-to-Chip Bonding

Wide IO memory (40/50um pitch) bonding on TSV 3D IC

Wide IO Memory

3D TSV IC Device

Gap; TCB cost

Confidential

3D IC TSV Stacked Packaging

Chip-to-Substrate & Chip-to-Chip Thermo-compression Bonding (TCB) for 3D TSV IC packaging

40m

Gap; TCB cost

Confidential

Contents

• Package trends and roadmap update

• Advanced technology update

Fine pitch & Low cost flip chip (fcCuBE®)

Wafer level package (eWLB)

Silicon level integration (TSV)

• Summary

Confidential

Summary• 2D, 2.5D and 3D structures with Flip Chip, Fan-out Wafer level and TSV structures fill the gaps

from requirements for high performance and compact form factor mobile applications such as Smartphones and Tablets

• Flip Chip with fcCuBE®

– Cu colum bump with BOL, OSR Mold underfill flip chip is a lower cost, finer pitch flip chip solution

– Oblong bump and ETS achieve narrower bump pitch, applicable to Mass Reflow and TCB– TCB for narrower bump pitch and thiner die thickness still has a process time gap with a cost

impact– eWLB-PoP realizes lower package height and less warpage than flip chip

• eWLB technology is evolving toward embedded component substrates with 2D, 2.5D and 3D level heterogeneous integration

– eWLB technology is used in a variety of 2D, 2.5D and 3D structures– Provides better electrical performance and less thermal warpage– Embedded passive function with IDC and passive components – 3D eWLB-PoP provides higher I/O in an ultra thin profile– As panel size increases, the cost of manufacturing drops significantly with increased throughput

• TSV Wide I/O memory offers improved mobile computing performance with minimized power consumption

– Delay of Wide I/O applications caused slow down of the development activities and manufacturing tool investments for TSV Mid-end and Back-end processes

– TSV ecosystem with Foundry & OSAT partnership offers proven 3D IC solution