PLL Design

A. Matsuzawa, Titech 1

PLL/DLL design

A. Matsuzawa

Titech


PFD Filter(LPF) VCO

FrequencyDivider

Output signal

Input signal

Basic construction of a PLL system

Vc oipPD KV

io

cvco V

Feedback signal

ＰＬＬ System

PLL (Phase Locked Loop) is a negative feedback to adjust phases.As a result, frequencies becomes equal completely.


Charge pump PLL

Charge pump PLL is a current major PLL scheme.


VcontVmin VmaxVcenter

ωmax

ωmin

ωfr

VCOVcntr

cntrVCOfrout VK Vcntr is high

Vcntr is low

Freq

uenc

y

VCO

Design pointsProper tuning rangeLow jitter and phase noiseLow power supply noise and stabilityHigh linearity for V to f characteristics

VCO generates frequency proportional to the control voltageConstant Kvco is preferable to stabilize the system.


Phase and frequency

time

time

phase

2

34

time

time

Phase

2

34

tsinV)t(V 0a

0

tsinV)t(V 1a1

tsinV)t(V 2a2

V1

V2

V1V2

21 dtd

Angular frequency is a temporal differentiation of phase Higher frequency: rapid phase change


To change phase

12

12

)t(

)t(

)t(Vt

0dt

contVCO0out VK

0contVCO0a

0a

dt)t(VKtcosV

dtcosV)t(V

dt)t(VK contVCOex

Vcont Frequency Phase (Integration of ω)


tsinVKtcosA)t(V

tcosV)t(V:exampleFor

dtVKtcosA)t(V

VK

mmm

VCO0

mmcntr

cntVCO0

cntVCO0out

High frequency component in Vcntr can be suppressed

VCO as a LPF

Low frequency component in Vcntr can't be suppressed

Transfer function between control voltage and phase of VCO is similar to the LPF.


ＰＦＤ

REF_IN

VCO_IN

VCO_UP

VCO_DOWN

PFD can generate a pulse of which width is proportional to the phase difference.


Charge pump

UP

Vout

time

A

B

)rad/A(2I

K

KI

pPD

PDPD

2

UP

DOWN

A

BCp

Ip

Vout

Ip

s

1C2I

)s(Vp

pout

Charge pump with PFD generates charge proportional to the phase difference.


Charge pump PLL without zero

+sKv

)s(in1/N)s(out

s1

C2I

p

p

logω

logωPhase

+ sKv

)s(in

1/N

)(' sout

s1

C2I

p

p )(log20 sG

-90 °-135 °

-180°

-40db/dec

-20db/dec

Two poles at zero frequency

Needs zero

OscillationOpen loop：G(s)

2

2

22)()(

sNsK

CI

ssG nv

p

p

openin

out

Closed loop: H(s)

22

2

2

2

12)(1

)()(n

n

p

vpp

vp

sNC

KIsNC

KIsGsGsH

np

vpp j

NCKI

js

22,1

)(sout

A charge pump PLL without zero is unstable and needs zero to be stabilized.

n

NCKI

p

vpn

2


PLL with zeroOpen loop: G(s)

z

nv

pp

p

openin

out ssNs

KsC

RI

ssG

112

)()(2

NCKI

sNRKI

sNCsCRKI

sH

p

vppvpp

ppvp

22

12

1)(

2

Closed loop: H(s)

2nn

2z

2n

LPz

LP2

zLP

s2s

s1

KsKs

s1K)s(H

2221,

2

,2

,1,

ppp

z

n

p

pLPn

p

pLP

ppz

v

CIKRCIK

K

CI

CRNKK

Damping factor

KIR421

pp2n

z

n

Insert this resistor to form the zero

UP

DOWN

A

B

Cp

Ip

Vout

Ip

Rp


Open loop characteristics

VDB(4)

-60

-40

-20

0

20

40

VD

B(4

) (d

B)

VP(4)

-200

-190

-180

-170

-160

VP

(4)

(deg

)

107 108 109

FREQUENCY (Hz)

VDB(5)-20

0

20

40

60

80

VD

B(5

) (d

B)

VP(5)

-180

-160

-140

-120

-100

-80

VP

(5)

(deg

)

106 107 108 109

FREQUENCY (Hz)

fz fn fu

位相余裕

Without zero With zero4.1

7.0 nz

　　

Oscillation at fn

Phase margin


Response

ppz CR

1

7.0222

1

ppp

z

n CIKR

Settling time

Damping factor

Loop bandwidth

2

2 ppnu

IKR

ppnpp IKCC

R

42

p

p

ppn IKC

KIRtconstimeDecay

441tan ：

22

2

22

2

2 2

21

2

11)(

nn

nn

nn

zn

LPz

LP

zLP

ss

s

ss

s

KsKs

sKsH

,nwithdescribedbecanSystemp

pn C

IK

2

Natural angular frequency


Frequency characteristics

VV

VDV

-50

-40

-30

-20

-10

0

10

MA

GN

ITU

DE

(dB

)

VVP(4)@DAMVP(4)@DAMP=1

VP(4)@DAMP

-100

-80

-60

-40

-20

0

PH

AS

E (

deg)

106 107 108 109 1010

FREQUENCY (Hz)

ζ=0.4ζ=0.７ζ=1.0ζ=2.0

ζ=0.７

ζ=0.4

ζ=0.７

ζ=1.0

ζ=2.0

MHzn 1002


Step and error responses

V(6)@

-1.00

-0.75

-0.50

-0.25

0

0.25

0.50

V (

V)

0 10n 20n 30n

TIME (s)1m

ζ=0.4

ζ=1.0

ζ=2.0

ζ=0.７

V(6)@

-1.00

-0.75

-0.50

-0.25

0

0.25

0.50

V (

V)

0 10n 20n 30n

TIME (s)1m

ζ=0.4

ζ=1.0

ζ=2.0

ζ=0.７

V(V(4)@DAMPV(4)@DAMP=1.00V(4)@DAMP=2.00

0

0.3

0.6

0.9

1.2

1.5

TRA

NS

IEN

T R

ES

PO

NS

ES

(V

)

0 10n 20n 30n 40n 50n

TIME (s)

ζ=0.4

ζ=1.0

ζ=2.0

ζ=0.７

V(V(4)@DAMPV(4)@DAMP=1.00V(4)@DAMP=2.00

0

0.3

0.6

0.9

1.2

1.5

TRA

NS

IEN

T R

ES

PO

NS

ES

(V

)

0 10n 20n 30n 40n 50n

TIME (s)

ζ=0.4

ζ=1.0

ζ=2.0

ζ=0.７

Step response Error response

Damping factor of 0.7 is proper. MHzn 1002


Phase error response to the frequency change

2nn

2

2

2nn

2z

nn

2

e s2ss

s2s

s2s)s(H1)s(H

)(t

)(te

t

t

Sudden frequency change

If phase error caused by sudden frequency change is not larger than linear phase comparison range, PLL can stay in lock condition.

)(t

t

Ramped frequencychange

)(te

tLPe K)t(

If the frequency change rate is constant,The phase error is constant and the magnitudeIs inversely proportional to Kωlp.

0)s(slim)t(s)s(H)s(

e0se

2ee

2n

e0se

3ee

1)s(slim)t(

s)s(H)s(

Go to zeroConstant error


Improvement of PLL

UP

DOWN

A

B

Cp

Ip

Vout

Ip

Rp

C2

Insert this capacitor

10C

5C

C pp2 ～

Rp for making zero increases high frequency noise.Thus small capacitor should be inserted to suppress it.


PLL design by symmetric pole zero location.

C１

R１

C2

Ip

Vout

Ip

VCO_UP

VCO_DOWN

Phas

eG

ain

(dB

)

0

Phase margin

au

z

up a 3

-180°

nu a

upu

znu aa

a 3,,

111

'22 C

IN

KCI

NK

CI

KK pVCOpVCOpLPn

2' VCOVCO

KK

21'

n

pVCO IN

KC

231

2 1aC

C

p

z

21

2 aCC aaCR

nuz

11

1

nu Ca

CaR

111

A=2～4 conventionally

Symmetric pole zero location to ωu


Exam： basic PLL design

kHzu 7002

K’vco=580MHz/VIc=22uAfr=33MHzDivision number：12a=4

C１

R１

C2

Ip

Vout

Ip

VCO_UP

VCO_DOWN

andfffDerive p

pz

zn

n ,2

,2

,2

33

Determine C1, C2, and R1


Noise transfer

+ F(s)s

Kv

1/N

LPF VCO

Different noise transfers to different noise sources.

+in_n

cont_nv vco_n１）Jitter and phase noise to the input noise

inout )s(H)s(

２） Jitter and phase noise to the VCO noise

VCO_ne

VCO_nout

)s(H)s(H1)s(

３） Jitter and phase noise to the VCO control voltage noise

s)s(H)s( VCO_n

eout

1)

2)3)


Frequency characteristics to the different noises

周波数

LPF

BPF

HPF

１） to the input noise ２） to the VCO noise

３） to the VCO control voltage noise


Optimization of PLL loop filter

Narrow bandwidth Wide bandwidth

Total noise can be minimized by adjusting filter bandwidth


Jitter and phase noise

Cycle to Cycle Jitter

N cycle jitter (n=5）

0

2nTj2n d)e1()(SP

Pn: Phase noise

Ｓ（ω）: Phase noise spectrum of VCO

0

0

)(2 fdfSTPLL

Transfer function


Accumulation of JitterWider bandwidth can suppress jitter.

Accumulation Jitter

# of clocks

Nor

mal

ized

Jitt

er

BW/fclk

Documents

PLL Design