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Comparators and Buses

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What is it?

A comparator is circuitry that compares two inputs A and B, determining whether the following conditions are true or false – A = B– A > B– A < B– A B– A B– A B

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Two will do

Actually the first two will suffice, since the others are easily related to these– A < B (NOT(A > B)) AND (NOT(A = B))– A B (A > B) OR (A = B)– A B NOT(A > B)– A B NOT(A = B)

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One-bit comparator

Input Output

A B = >

0 0 1 0

0 1 0 0

1 0 0 1

1 1 1 0

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Gate version

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Comparing word equality

To compare if two words are equal, you pair up the bits holding the same position in each word, and each individual pair must be equal for the words to be equal.– 1100 and 1110 {(1,1), (1,1), (0,1), (0,0)} are not

equal – 1100 and 1100 {(1,1), (1,1), (0,0), (0,0)} are

equal

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Comparing word inequality

Assume unsigned integers, then – If the most significant bit of word A is greater than

the most significant bit of word B, then word A is greater than word B.

– If the most significant bit of word A is less than the most significant bit of word B, then word A is less than word B.

– If the most significant bit of word A is equal to the most significant bit of word B, then we must compare the next most significant bits.

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And so on

If the most significant bits are equal, one compares the next-most significant bits.

Then if the next most significant bits are equal, one compares the next-next-most significant bits, and so on.

It seems that one must know the outcome of testing the more significant bits before one proceeds to the less significant bits.

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Timing issues

In terms of circuitry, this would seem to require many layers, the output of one layer being fed into the next layer.

There would seem to be as many layers as there are bits in the word.

Each layer of circuitry requires time to settle into the desired state.

More layers means more time.

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Scaling

If the comparing is to be done in one clock cycle, this clock’s period restricts the size of the word that can be compared.

It is said that such circuitry “does not scale,” that is, changing the word size produces (timing) problems not seen in the smaller word size.

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Combinatorial scaling

Recall that combinatorial logic is expressible in terms of a truth table.

Recall our procedure to realize a truth table as a circuit: we focus on the true (1) outputs, etc.

Thus logical circuits really require only three layers: inverting the inputs, ANDing inputs or inverted inputs, ORing the output of the AND gates

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Complexity

Sometimes the price one pays to have a circuit that scales is loss of simplicity.– There are fewer layers, but more going on in a given

layer. There are other possible problems,

– The scaling circuit may have a given input attached to many gates.

– A given gate may have many inputs.– Potential power problems.

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4-bit comparator

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Buses

Warning: some of the terminology is used inconsistently within the field

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What is a bus?

A bus is a basically just wires through which data travels from one part of a computer to another.

– Usually it’s implied the path is shared by a number of parts There is more than one bus and more than one kind of

bus– Data, address, control– System, expansion, local, external– USB, AGP, ISA, EISA, MCA, PCI, VESA– (Parallel, serial)

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What does it carry?

In simple architectures, data and addresses travel on the same bus, while control information traveled along individual wires (not shared)– Saves on pins

In more complicated architectures, data and address buses are separate

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Data, address and control buses

The data bus carries data and instructions. The address bus carries information about

where the data should go. The control bus carries information from the

CPU to other parts of the computer, telling what they should be doing.– Some use control bus as a synonym for system bus.

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Bus characteristics

The highway analogy: moving data along the buses is like moving cars on the highway.

Bus width (number of lanes)– How many bits are moving around in parallel

Bus speed (speed limit) – How fast those bits are moving

Throughput is the numbers of bits being handled per unit time, it combines bus width and bus speed into one measure.

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Memory size

The width of the system’s address bus puts an upper limit on the amount of memory locations.

For example, if the address bus width is 32, then there are 232 (4,294,967,296) addresses.

Note that instead of addressing individual words, computers usually address individual bytes, so that would mean 4 GB.

Of course, most computers have less than 4 GB of memory, it’s just an upper limit.

– To exceed this limit, say in a server, one needs a wider bus or one needs to break the addresses into parts.

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Bus speeds

Measured in MHz (millions of cycles per second).

It doesn’t make much sense to have a very fast processor speed and a slow bus speed; they should be compatible.– The bus speed is slower than the processor speed

and often limits the speed of the computer.

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Multiple buses

A bus should not be too long; its speed is determined in part by its length.

Also slower devices do not need faster (and more expensive) buses.

The computer should not be held back by the slowest device.

Solution: More than one bus

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System bus

The system bus connects the CPU, memory and other motherboard parts.

This bus should be well coordinated with the processor and memory access speeds.

Other buses must interface with the system bus if they want to interact with the processor.

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Frontside and backside buses

The frontside bus is the bus within a processor that connects the CPU with main memory. It's used to communicate between the motherboard and other components in a computer system.

In contrast, a backside bus connects the CPU to a Level 2 cache. – L2 cache usually sits on top of the processor chip.

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Expansion bus

The expansion bus connects the system bus to the expansion slots (where cards are inserted to expand the computer’s capabilities)

– This bus usually works at slower speeds Early PCs used an expansion bus called the ISA bus. Most PCs today have a much faster PCI bus but may

have an ISA bus for backward compatibility.

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Local bus

If a device or devices require a great deal of speed (e.g. video), then one solution is for the device to have its own high-speed, direct (or nearly direct) connection to the processor.

Such a connection is called a local bus. Can only support a few devices.

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ISA

Industry Standard Architecture (ISA) is the bus used in early IBM PC and their clones.

The AT (advanced technology) version of the bus is called the “AT” bus and became an industry standard.

Worked at 8.33 MHz

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Plug and Play

In 1993, Intel and Microsoft introduced a version of the ISA called Plug and Play ISA.

Plug and Play ISA enables the operating system to do the configuring, instead of the user setting switches and jumpers.

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PCI

Peripheral Component Interconnect, a standard introduced by Intel.

PCI is a 64-bit bus, though it is usually implemented as a 32-bit bus.

It can run at clock speeds of 33 or 66 MHz. At 32 bits and 33 MHz, it yields a throughput

rate of 133 MBps (Mega bits per second).

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EISA and MCA

Between ISA and PCI were some short-lived bus architectures

Extended Industry Standard Architecture (EISA)

Micro Channel Architecture (MCA) The principal difference between EISA and

MCA is that EISA is backward compatible with the ISA bus, while MCA is not.

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VLB

Short for VESA Local-Bus, a local bus created by the Video Electronics Standard Association (VESA).

33 MHz Although it was used a lot in PCs made in 1993

and 1994, PCI has become more popular

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external bus

A bus that connects a computer to peripheral devices.

Two examples are the Universal Serial Bus (USB) and IEEE 1394.

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USB

Universal Serial Bus, a new external bus standard that supports data transfer rates of 12 Mbps (12 million bits per second).

A single USB port can be used to connect up to 127 peripheral devices, such as mice, modems, and keyboards.

USB also supports Plug-and-Play installation and hot plugging.

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Bus mastering

Refers to a feature supported by some bus architectures that enables a controller connected to the bus to communicate directly with other devices on the bus without going through the CPU. Most modern bus architectures, including PCI, support bus mastering because it improves performance.

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DMA

Direct Memory Access Gives a peripheral device access to the

memory without going through the CPU. Speeds up data transfer.

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Three State Logic

A E Output

0 0 Z (High impedance)

0 1 0

1 0 Z (High impedance)

1 1 1

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Tri-state buffer

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In the high impedance state

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In the high impedance state

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In the “enabled” state

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In the “enabled” state