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Scheduling algorithms forinput-queued IP routers
Andrea Bianco Paolo Giaccone
Gruppo Reti di TelecomunicazioniDipartimento di Elettronica
Politecnico di Torinohttp://www.tlc-networks.polito.it
Switching Architectures 2011/12
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Outline
IP routers
OQ routers IQ routers Scheduling
Optimal algorithms
Heuristic algorithms
Packet-mode algorithms
Networks of routers QoS support
CIOQ routers
Multicast traffic
Conclusions
Switching Architectures 2011/12
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Note
The slides marked RWP are reproduced withpermission of Prof.Nick McKeown from theElectrical Engineering and Computer ScienceDept. of Stanford University (CA,USA)
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Outline
IP routers
OQ routers
IQ routers Scheduling
Optimal algorithms
Heuristic algorithms
Packet-mode algorithms
Networks of routers
QoS support
CIOQ routers
Multicast traffic
Conclusions
Switching Architectures 2011/12
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The Internet is a mesh of routers
corerouter
accessrouter
enterpriserouter
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Access router:
high number of ports at low speed (kbps/Mbps)
several access protocols (modem, ADSL, cable)
Enterprise router:
medium number of ports at high speed (Mbps)
several services (IP classification, filtering)
Core router:
low number of ports at very high speed (Mbps/Gbps)
very high throughput
few services
The Internet is a mesh of routers
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Basic architecture
Control Plane
Datapathper-packetprocessing
SwitchingForwarding
Table
Routingtable
Routingprotocols
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Basic functions
Routing
computation of the output port ofan incoming packet (forwarding)
uses the routing tables computed bythe routing protocols
can be a complex procedure: very large routing tables
dynamic variation of routes in the Internet
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Basic functions
Switching transfer of packets from input ports
to output ports
solution of the contentions for output ports
queueing methods where to store
scheduling methods what to transfer
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Faster and faster
Need for high performance routers to accommodate the bandwidth demands
for new users and new services
to support QoS (over-provisioning)
to reduce costs with respect to a cloud of smaller sizerouters (maybe)
a smaller number of fibers is needed
a smaller number of devices (but it is less costly?)
May be more energy hunghry
to ease of the management task
10Switching Architectures 2011/12
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Packet processing and link speed
0,1
1
10
100
1000
10000
1985 1990 1995 2000
Spec95In
tCPUr
esults
0,1
1
10
100
1000
10000
1985 1990 1995 2000FiberCapacity(Gbit/s)
TDM DWDM
Packet processing Power Link Speed
Moores law2x / 18 months
2x / 7 months
Source: SPEC95Int & David Miller, Stanford.
RWP
Increase of electronic packet processing power cannotaccommodate the increase in link speed
?
Switching Architectures 2011/12
120,001
0,01
0,1
1
10
100
1000
1980 1983 1986 1989 1992 1995 1998 2001
AccessTime
(ns)
Moores Law2x / 18 months
1.1x / 18 months
RWP
Memory access time
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Its hard to keep up with Moores law:
the bottleneck is memory speed
Moores law is too slow:
routers need to improve fasterthan Moores law
RWP
Moores law
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Router capacity exceeds Moores law
Growth in capacity of commercial routers: 1992 ~ 2 Gb/s
1995 ~ 10 Gb/s
1998 ~ 40 Gb/s
2001 ~ 160 Gb/s
2003 ~ 640 Gb/s
Average growth rate: 2.2x / 18 months
RWPSwitching Architectures 2011/12
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Single packet processing
The time to process one packetis becoming shorter and shorter
worst case: 40-Byte packets (ACKs)travelling over the Internet
3.2 s at 100 Mbps
320 ns at 1 Gps
32 ns at 10 Gps
3.2 ns at 100 Gbps
320 ps at 1Tbps
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S F
LC
LC
LC
LC
CP
S F
IP
IP
IP
IP
CP
OP
OP
OP
OP
Hardware architecture
physical structure logical structure
Switching Architectures 2011/12
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Hardware architecture
Main elements
line cards support input/output transmissions
adapt packets to the internal format of the switching fabric
support data link protocols
In most architectures
store packets
classify packets schedule packets
support security
switching fabric transfers packets from input ports to output ports
Switching Architectures 2011/12
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control processor/network processor runs routing protocols
computes and stores routing tables
manages the overall system
sometimes
store packets
classify packets
schedule packets
support security
forwarding engines inspect packet headers
compute the packet destination (lookup)
Searching routing or forwarding (chaching) tables
rewrite packet headers
Hardware architecture
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switching fabric
line card line card
control processor &
forwarding engine
1 N
Interconnections among mainelements - I
Switching Architectures 2011/12
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switching fabric
line card line card
control
processor
forwarding
engine
forwarding
engine
1 N
Interconnections among mainelements - II
Switching Architectures 2011/12
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Interconnections among main
elements - II
switching fabric
line card &forwarding engine
control
processor
1
line card &forwarding engine
N
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Cell-based routers
ISM: Input-Segmentation Module
ORM: Output-Reassembly Module
packet: variable-sizedata unit
cell: fixed-size dataunit
22
Cell switch (fabric) ORM1
ORMN
1
ISM
N
ISM
packets cells cells packets
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Switching fabric
Our assumptions:
bufferless
to reduce internal hardware complexity
non-blocking
given a non-conflicting set of inputs/outputs,
it is always possible to connect inputs withoutputs
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Switching fabric
Examples:
bus
shared memory
crossbar
Multi-stage
rearrangeable Clos network
Benes network
Batcher-Banyan network (self-routing)
Switching constraints
at most one cell for each input and for each outputcan be transferred
1234
1 2 3 4
outputs
inputs
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Switching fabric
We do not discuss switching fabrics withinternal buffers
e.g.: crossbars with buffer at each crosspoint
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Generic switching architecture
Output 1
switching fabric
Input 1
Input NOutput N
Sin
Sin
Sout
Sout
input queues output queues
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Speedup
The speedup limits the switch performance
Sin = reading speed from input queues
Sout = writing speed to output queues
The main performance limit can be due tothe maximum speedup factor:
S = max(Sin,Sout)
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Performance comparison
The performance of different switchingsystems can be studied
with analytical models
introducing simplifying assumptions, butobtaining general results
with simulation models
obtaining more detailed results
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Traffic description
Aij(n) = 1 if a packet arrives at time n at input i,with destination reachable through output j
ij = E[Aij(n)]
An arrival process is admissibleif:
i ij < 1
j ij < 1
that is, no input and no output are overloadedon average
note that OQ switches exhibit finite delays only
for admissible traffic
traffic matrix: = [ij ]Switching Architectures 2011/12
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Traffic scenarios
Uniform traffic Bernoulli i.i.d. arrivals
usual testbed in the literature
easy to schedule
Diagonal traffic Bernoulli i.i.d arrivals
critical to schedule, since
only two matchings are good
=
2001
1200
0120
0012
3
=
1111
1111
1111
1111
N
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Traffic scenarios
LogDiagonal traffic
Bernoulli i.i.d. arrivals
more critical than uniform,less than diagonal traffic
=
8124
4812
2481
1248
12N
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Outline
IP routers
OQ routers IQ routers Scheduling
Optimal algorithms
Heuristic algorithms
Packet-mode algorithms
Networks of routers QoS support
CIOQ routers
Multicast traffic
Conclusions
Switching Architectures 2011/12
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Output Queued (OQ) switches
Sin = 1 Sout = N
used for low bandwidth routers
no coordination among ports
work-conserving
best average delays
complete control of delays
support of QoS scheduling
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Output Queued (OQ) switch
speedup N
Output N
Output 1
switching fabric
Input 1
Input N
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0% 20% 40% 60% 80% 100%
Normalized load
Delay
OQ performance
OQ
Note: OQ is optimal from the pointof view of average delay and
throughput
Uniform traffic
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Stability, throughput and delays
Hp: stationary system, infinite queue
for a particular in stable finite occupancy finite delays
in= out
100% throughput stable under any inadmissible
in out
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Stability, throughput and delays
outmax
stable(in) in= out inmax
hence, max is maximum throughput achievable
maximum offered load for stability
unstable (in) in> max
queue grows with rate in- max
in
out
max
in
delay
max
max
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Outline
IP routers
OQ routers IQ routers Scheduling
Optimal algorithms
Heuristic algorithms
Packet-mode algorithms
Networks of routers QoS support
CIOQ routers
Multicast traffic
Conclusions
Switching Architectures 2011/12
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Simple Input Queued (IQ) switches
Sin = 1 Sout = 1
1 FIFO queue for each input port
throughput limitations
due to head of the line (HOL) blocking
scheduling
to solve contentions
for the same output
Output N
Input 1 Output 1
switching fabric
Input 1
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Head of the Line (HOL) Blocking
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0% 20% 40% 60% 80% 100
Normalized load
Delay
Simple IQ switch performance
OQSimpleIQ
Uniform traffic
%5822
Switching Architectures 2011/12
Single IQ switch
Using a simple Markov chain model
2x2 throughput 0.75
states: (2,0), (1,1)
3x3 throughput ?
states: (3,0,0), (2,1,0), (1,1,1)
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Bufferless switch
Throughput= uniform i.i.d. Bernoulli arrivals
input load p
Switching Architectures 2011/12 43
63.0111 1 eNp
N
44
Improving IQ switches performance
Window/bypass schedulers
the first w cells of each queue contendfor outputs
HOL blocking is reduced, not eliminated
w = 1 means FIFO at each input
higher complexity
the scheduler deals with wN cells
non-FIFO queues
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Improving IQ switches performance
Maximum throughput in an NxN switch withvariable window size w
N W=1 W=2 w=3 w=4 W=5 W=6 W=7 W=8
2 0.75 0.84 0.89 0.92 0.93 0.94 0.95 0.96
4 0.66 0.76 0.81 0.85 0.87 0.89 0.91 0.92
8 0.62 0.72 0.78 0.82 0.85 0.87 0.88 0.89
16 0.60 0.71 0.77 0.81 0.84 0.86 0.87 0.88
32 0.59 0.7 0.76 0.8 0.83 0.85 0.87 0.88
64 0.59 0.7 0.76 0.8 0.83 0.85 0.86 0.88
128 0.59 0.7 0.76 0.8 0.83 0.85 0.86 0.88
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Improving IQ switches performance
Virtual output queueing (VOQ) one queue for each input/output pair
N queues at each input
N2 queues in the whole switch
eliminates HOL blocking
used in high-bandwidth routers
scheduling implemented in hardwareat very high speed
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IQ switches with VOQ
Output N
Input 11
N
Output 1
Input N1
N
scheduler
switching fabric
Note: from now on, we always assume VOQ
at the switch inputs
input
constraints
output
constraints
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Outline
IP routers
OQ routers IQ routers Scheduling
Optimal algorithms
Heuristic algorithms
Packet-mode algorithms
Networks of routers
QoS support
CIOQ routers
Multicast traffic
Conclusions
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Scheduling in IQ switches
Scheduling can be modeled as a matchingproblem in a bipartite graph the edge from node ito nodejrefers to packets
at input iand directed to outputj
the weight of the edge can be
binary (not empty/empty queue)
queue length
HOL cell waiting time, or cell age
some other metric indicating the priorityof the HOL cell to be served
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Scheduling in IQ switches
51
2
3
4
4
2
5
4
8
2
5
4
4
8
1
2
3
4
1
2
3
4
1
2
3
4
Graph Matching
inputs outputs
schedulerSwitching Architectures 2011/12
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Implementing schedulers
Scheduling is a complex task
a scheduling algorithm can be implementedin hardware if:
it shows good performance for a wide rangeof traffic patterns
it can be efficiently parallelized
it can be efficiently pipelined
it requires few iterations (or clock cycles)
it requires limited control information
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Scheduling uniform traffic
A number of algorithms give 100%throughput when traffic is uniform
For example:
TDM and a few variants
iSLIP (see later)
RWP
Example of TDM for a 4x4 switch
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Scheduling non-uniform traffic
If the traffic is known and admissible, 100%throughput can be achieved by a TDMusing: for a fraction of time a1 matching M1 for a fraction of time a2 matching M2
for a fraction of time ak matching Mk subject toi ai = 1
thanks to the Birkhoff - von Neumanntheorem
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Outline
IP routers
OQ routers IQ routers Scheduling
Optimal algorithms
Heuristic algorithms
Packet-mode algorithms
Networks of routers
QoS support
CIOQ routers
Multicast traffic
Conclusions
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Maximum Weight Matching
Maximum Weight Matching (MWM) among all the possible N! matchings, selects the one
with the highest weight (sum of the edge metrics)
MWM is generally not unique
MWM is too complex to be implemented in hardwareat high speed
the best MWM algorithm requires O(N3) iterations,
and cannot be implemented efficiently, sinceit is based on a flow augmentation path algorithm
cannot be parallelized and pipelined efficiently
MWM has never been implemented in a commercial
chipsetSwitching Architectures 2011/12
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Maximum Weight Matching
MWM is the optimal solution of the schedulingproblem when the traffic is unknown, when theweight is either the queue length or the cell age
achieves 100% throughput under any traffic
also under non-Bernoulli arrival processes,
satisfying the law of large numbers
achieves low average delays, very close to thoseof OQ switches
possible starvation for lightly loaded packet flows
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MWM with pipeline and latency
Let T and P be fixed
Dt denotes the matching used at time t
The following variations of MWM also achieve100% throughput:
Dt = MWM(t-P) MWM with pipeline degree P
Dt = MWM(ceil(t/T)T) MWM with latency T
combinations of both
thus, it seems easy to achieve 100% throughput!
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MWM with pipeline and latency
But: What about throughput?
100% throughput
but needs the computation of a MWM
What about delays?
delays can be really bad!
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General consideration
When scheduling in IQ switches, it isvery difficultto achieve simultaneously
high throughput
low delay
limited implementation complexity
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Maximum Size Matching
Maximum Size Matching (MSM)
among all the possible matchings, selects the one
with the highest number of edges (like MWM with
binary edge weights)
MSM is generally not unique
the best MSM algorithm requires O(N2.5) iterations,
and cannot be implemented efficiently, since it isbased on a flow augmentation path algorithm
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Maximum Size Matching
MSM maximizes the instantaneousthroughput
MSM may not yield 100% throughput
short term decisions can be inefficientin the long term
non-binary edge weights allow MWMto maximize the long-term throughput
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Instability of MSM
Assume:
P(arrival at Q12) =
P(arrival at Q11) = P(arrival at Q22) = 1--
Q12 = B 0 Q11 = Q22 = 0 in case of parity serve Q11 and/or Q22 instead of Q12
Observe:
Q12 is served only when A11 = 0 and A22 = 0, i.e. with probab ility:
P(serve Q12) = P(no arrivals at both Q11 and Q22 ) = [1-(1--)]2 = (+)2
P(serve Q12) < P(arrival at Q12) if is small enough
Example: = 0.5; = 0.1;P(serve Q12) = 0.36 In1
In2
Out1
Out2
1--
1--
Note: this proof is due to
I.Keslassy and R.Zhang,Stanford Univ.
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Uniform traffic
MWM and MSM behave almost identically
1
10
100
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Meandelay
Normalized Load
Uniform Traffic
MWMMSM
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LogDiagonal traffic
MSM is somewhat inferior to MWM
1
10
100
1000
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Meandelay
Normalized Load
LogDiagonal Traffic
MWMMSM
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Diagonal traffic
MSM yields much longer delays than MWM at medium/high loads
1
10
100
1000
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Meandelay
Normalized Load
Diagonal Traffic
MWMMSM
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Outline
IP routers
OQ routers IQ routers Scheduling
Optimal algorithms
Heuristic algorithms
Packet-mode algorithms
Networks of routers
QoS support
CIOQ routers
Multicast traffic
Conclusions
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Approximations of MSM and MWM
Motivation strong interest in scheduling algorithms with
very low complexity
high performance
Usually implementable schedulers (low complexity)
low throughput, long delays
theoretical schedulers (high complexity)
high throughput, short delays
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Some implementable algorithms
Approximate MSM WFA, iSLIP, 2DRR, RC, FIRM and many
others
Approximate MWM with wij = Xij (queue length) iLQF, RPA, learning algorithms
Approximate MWM with wij = cell age iOCF
Approximate MWM with wij = i Xij+ j Xij iLPF, MUCS
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APPROXIMATIONS OFMAXIMUM SIZE
MATCHING
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Wave Front Arbiter
Requests Match
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
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Wave Front Arbiter
Requests Match
RWP
2N-1 steps
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Wrapped Wave Front Arbiter
Requests Match
N steps instead of
2N-1
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iSLIP
iSLIP means iterative SLIP iterates among the following 3 phases Request
Grant
Accept
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iSLIP
iSLIP demo
from: http://tiny-tera.stanford.edu/tiny-tera/demos/index.html
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iSLIP
3 phases: Request (from inputs to outputs)
each unmatched input sends a requestto every output for which it has a cell
Grant (from outputs to inputs)
if an unmatched output receives requests,it sends a grant to one of the inputs contentions solved by a round-robin mechanism
Accept (from inputs to outputs)
if an unmatched input receives grants, it selectsa single output and it becomes matched to it contentions solved by a round-robin mechanism
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iSLIP
The round robin mechanism in iSLIP isdesigned so that, under uniform traffic,iSLIP emulates a dynamic TDM schedulersynchronized on the arrival pattern
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iSLIP
iSLIP is maximal
often, with log N iterations
always, with N iterations
iSLIP was implemented on a single chipin the Cisco 12000 router http://www.cisco.com/warp/public/cc/pd/rt/12000/tech/fasts_wp.pdf
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APPROXIMATIONS OFMAXIMUM WEIGHT
MATCHING
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iLQF
iLQF means iterative Longest Queue First iterates among the following 3 phases Request
Grant
Accept
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iLQF
iLQF demo
from: http://tiny-tera.stanford.edu/tiny-tera/demos/index.html
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iLQF
3 phases: Request (from inputs to outputs)
each unmatched input sends all its queue lengthsas requests to corresponding outputs
Grant (from outputs to inputs)
if an unmatched output receives requests, it sendsa grant to the input corresponding to the longest queue
contentions solved by random choice
Accept (from inputs to outputs)
if an unmatched input receives grants, it selects
the output with the longest queue contentions solved by random choice
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iLQF
iLQF is maximal often, with log N iterations
always, with N iterations
iLQF is robust to non-uniform traffic
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RPA
RPA means Reservation with Preemptionand Acknowledgment
Two phases Reservation (possibly preemptive)
Acknowledgement
Sequential accesses to a reservation vector Urgj (if set) is the urgency of the transfer from
input Inj to output j
Urg1,In1 Urg2,In2 Urg3,In3 UrgN,InN
Out 1 Out 2 Out 3 Out N
VectorRes
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RPA
Vector Res is sequentiallyaccessed by all inputs
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Res
Input 1 Input 2
Input 4 Input 3
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RPA
Initially, at each round: Urgj = 0 for all j
Reservation phase
when input i accesses Res it computes Wj= Xij Urgj for all j
finds j* such that Wj* = max{ Wj }
if Wj* > 0,
reserve output j* and set Urgj*=Xij*, possiblyoverwriting the previous reservation
otherwise,
leave the current reservation
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RPA
Acknowledgement phase
if input i still finds its reservation at output j,
books output j
otherwise,
chooses an unreserved output j and books
output j
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Uniform traffic
comparison between MWM, iSLIP, iLQF, and RPA
1
10
100
1000
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Meandelay
Normalized Load
Uniform Traffic
MWM
iSLIP
iLQF
RPA
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LogDiagonal traffic
iSLIP saturates close to 84% throughput
1
10
100
1000
10000
100000
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Meandelay
Normalized Load
LogDiagonal Traffic
MWMiSLIPiLQFRPA
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Diagonal traffic
RPA achieves 98% throughput, iLQF 87%, iSLIP 83%
1
10
100
1000
10000
100000
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Meandelay
Normalized Load
Diagonal Traffic
MWMiSLIPiLQFRPA
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LEARNING ALGORITMS
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Learning algorithms
Goal:
find a good compromise among
throughput, delayand complexity
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Learning algorithms
Key observation the matchings generated by MWM show limited
changes from one time slot to another
remembering the matching from the pastsimplifies the computation of the new matching
the search implemented by MWM can beenhanced
with a randomized approach
by observing arrivals
by searching in parallel
based on an extension of randomizedscheduling algorithms
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Simple Randomized Schemes
Choose a matching at random and use itas the schedule doesnt yield 100% throughput
Choose 2 matchings at random and usethe heavier one as the schedule
Choose N matchings at random and usethe heaviest one as the schedule
None of these can give 100% throughput !
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0.001
0.01
0.1
1
10
100
1000
10000
0.0 0.2 0.4 0.6 0.8 1.0
MeanIQLen
Normalized Load
Diagonal Traffic
MWMR32R1
Simple randomized algorithms
32x32
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Bounds on Maximum Throughput
by Devavrat Shah, StanfordUniversity
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Tassiulas scheme
Consider the following policy Rt = matching picked at random (uniformly) among
all the possible N! matchings
Dt = arg max { W(Dt-1), W(Rt) }
Complexity is very low O(1) iterations
easy to pipeline
Yields 100% throughput ! note the boost in throughput is due to memory
of the past matching Dt-1
However, delays are very large
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0.01
0.1
1
10
100
1000
10000
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
MeanIQLen
Normalized Load
Diagonal Traffic
MWMTassiulas
Tassiulas' scheme
32x32
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Learning approach
Properties of COMP1
W(Dt) W(Dt-1)
W(Dt) W(Mt)
Examples:
COMP1 is the MAX amongDt-1 and Mt
COMP1 is the MERGEamong Dt-1 and Mt
Dt-1
Dt
COMP1
Mt
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The learning approach
Dt-1
Dt
COMP1
Mt
Properties of Mt informally, Mt should be a good sample
in the space of all possible matchings
Examples:
Mt is a matching picked uniformly at
random
Mt is derived from the arrival vector At
Mt is a good neighbor of D t-1
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Theoretical properties
Dt-1
Dt
COMP1
Mt
Stability 100% throughput under any
admissible Bernoulli trafficpattern
Delay the better is the weight of Mt ,
the smaller are the queuelengths, and hence the smallerare the delays
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Dt-1
Mt
Dt
MAX
MAX
N1 NK
At
K-th neighborof Dt-1
Example of practical implementation
Exploiting parallel search:
This scheme is calledAPSARA
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What is a neighbor of a matching?
Each neighbor differs from Dt-1 in ONLY TWO edges can be generated very easily in hardware
3 neighbors
Example: 3 x 3 switchDt-1
N1 N2 N3
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Max-APSARA
APSARA, as described before, is notmaximal
Max-APSARA is a modified version ofAPSARA where a maximal size matchingalgorithm runs on the remaining unmatchedinputs/outputs e.g., if k inputs/outputs are unmatched,
run iSLIP with k iterations
select k random edges among theunmatched inputs/outputs
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APSARA performance
0.01
0.1
1
10
100
1000
10000
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Me
anIQL
ength
Normalized Load
Diagonal Traffic
MWMMaxAPSARAAPSARAiSLIPiLQF
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Outline
IP routers
OQ routers IQ routers Scheduling
Optimal algorithms
Heuristic algorithms
Packet-mode algorithms
Networks of routers
QoS support
CIOQ routers
Multicast traffic
Conclusions
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Routers and switches
IP routers deal with variable-size packets
Hardware switching fabrics often dealwith fixed-size cells
Question:
how to integrate an hardware switching fabricwithin an IP router?
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Router based on an IQ cell switch:cell-mode
switching fabric
IQ cell switch1 ISM
N ISM
ORM1
ORMN
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Cell-modescheduling
Scheduling algorithms work at cell level
pros:
100% throughput achievable
cons:
interleaving of packets at the outputsof the switching fabric
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Router based on an IQ cell switch:packet-mode
switching fabric
IQ cell switch1 ISM
N ISM
ORM1
ORMN
NO packetinterleaving
ifpacket-mode
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Router based on an IQ cell switch:packet-mode
switching fabric
IQ cell switch1 ISM
N ISM
ORM1
ORMN
NO packetinterleaving
ifpacket-mode
ORMs can be
removed
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Packet-modescheduling
Rule: packets transferred as trains of cells when an input starts transferring the first cell
of a packet comprising k cells, it continuesto transfer in the following k-1 time slots
Pros: no interleaving of packets at the outputs
easy extension of traditional schedulers
Cons: starvation due to long packets
inherent in packet systems without preemption
negligible for high speed rates
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Packet-modescheduling
Questions
can packet mode provide highthroughput?
what about delays?
YES!
It depends
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Packet-modeproperties
Main theoretical results
MWM in packet-modeyields 100% throughput
Packet modecan provide shorter delaysthan cell mode, depending on thepacket length distribution
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Simulation scenario
Router with ISMs and ORMs
Uniform packet traffic uniform packet load
uniform (1,192) packet sizedistribution
Spotted packet traffic non uniform packet load
bimodal (3,100) packet sizedistribution
1 1 1 0 1 0 1 0
0 1 0 1 1 1 0 1
1 0 1 0 1 1 1 0
1 1 0 1 0 1 0 1
1 0 1 0 1 0 1 1
0 1 0 1 0 1 1 1
1 0 1 1 1 0 1 0
0 1 1 1 0 1 0 1
P=
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Packet mode features
Packet mode scheduling is a feasible modification of schedulers
improves throughput
but it can generate some unfairness betweenlong and short packets
inherent to all variable-packet networks withoutpreemption
maygive better packet delays than cell mode
depends on the packet size distribution
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Outline
IP routers
OQ routers IQ routers Scheduling
Optimal algorithms
Heuristic algorithms
Packet-mode algorithms
Networks of routers QoS support
CIOQ routers
Multicast traffic
Conclusions
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Network of IQ routers
Question:
given a network of IQ switches running MWMand an admissible input traffic, is the networkalways stable?
NO!
this is quitecounterintuitivebut true
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Networks of IQ routers
Consider the acyclic network of IQ routersin the following slide
derived from well established resultsfrom adversarial queueing theory
a very specific scenario, but comprisesonly few switches
this situation may not be common,but cannot be excluded in real networks
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Pathological network of IQ switches
Network with
8 switchesand 4 flows
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Instability of MWM
If MWM is adopted at each IQ router, andthe traffic is admissible, the system can beunstable under Bernoulli i.i.d. arrivals
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Instability of MWM
MWM is too greedy, in the sense that itcan create traffic bursts that are amplifiedby each scheduler
A server can be idling when large bursts(directed to it) are blocked becauseof the contentions upstream
the problem arises when a packet flow issubject to priority changes along its paththrough the network
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Stability in networks of routers
Global policies
Oldest in the network and many others
problem: requires global information aboutthe network, and synchronized clocks at theingress of the network
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Stability in networks of routers
Semi-local policies MWM with local information about the router
neighbors can achieves 100% throughputunder i.i.d. Bernoulli arrivals
Virtual network queue
the weights used by MWM are: wij = max{0,Xij-Xdown-queue(ij))}
where down-queue(ij) is the first downstreamqueue which is receiving packets from Xij
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Outline
IP routers
OQ routers
IQ routers Scheduling
Optimal algorithms
Heuristic algorithms
Packet-mode algorithms
Networks of routers
QoS support
CIOQ routers
Multicast traffic
Conclusions
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IQ and QoS
Problem:
support rate guarantees, with admissible ratematrix
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Birkhoff von Neumann
decomposition
goal: find a sequence of matchings Mk andtheir fraction of time k such that the servicegiven to all the queues satisfies R
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IQ and frame scheduling
Example:
M1
1=1/4, 2=1/2, 3=1/4
M2 M2 M3 M1 M2 M2 M3
frame i frame i+1
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How to decompose R?
R double substochastic
R double stochastic such that RR
R decomposition
augmentation
algorithm
BvN algorithm
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Augmentation algorithm
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BvN algorithm
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BvN algorithm
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Outline
IP routers
OQ routers IQ routers Scheduling
Optimal algorithms
Heuristic algorithms
Packet-mode algorithms
Networks of routers
QoS support
CIOQ routers
Multicast traffic
Conclusions
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CIOQ routers
Output 1
switching fabric
Output N
S
S
o1
oN
Input 1S
Input NS
VOQ
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CIOQ routers
Question:
if a low speedup S is allowed (and queuesare available at both inputs and outputs),is it possible to design simple schedulingalgorithms, capable of achieving high
throughput and low delay?
YES!
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OQ emulation
a CIOQ switch achieves perfect OQemulationif the departure order of all thepackets from each output is the same asthe emulated OQ it is impossible to distinguish, by observing
arrivals and departures, if the switchingarchitecture is CIOQ or OQ
delays are perfectly controlled
easy to implement scheduling algorithmsborn for OQ (eg: WFQ)
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Work conservation
a CIOQ switch is work-conserving when eachoutput is busy at the same time as thecorresponding OQ switch i.e., each output of the switch for which there are cells
(either at the inputs or at the outputs) at the beginningof cell slot T is active at the end of the cell slot T
output never idling whenever a packet is presentdestined to it
good delay performance: same average delays as OQ
note that OQ emulation implies work conservationbut not viceversa
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Speedup and performance
speedup 4
exact OQ emulation
speedup 2
exact OQ emulation
work conservation
same average delay than OQ
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CIOQ routers with S=2
If S = 2
easy to obtain 100% throughput
any maximal matching obtains 100%throughput
less easy to obtain work conservation
LOOFA algorithm
it is difficult to obtain perfect OQ emulation
stable marriage algorithm with specialpreference list
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LOOFA
Occupancy oj : number of cells currentlyresiding at the j-th output queue
at each time slot, oj is decremented by onebecause of departures
Basic idea of LOOFA
Higher priority is given to outputs with loweroccupancy, thereby attempting to maintainwork-conservation for all outputs
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LOOFA
If S = 2, during eachof the two phases
each unmatched input selects a non-emptyVOQ directed to the unmatched output withthe lowest occupancy, and sends a requestto that output
each unmatched output grants one request the selection can be round robin, random, ...
repeat until the matching is maximal
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LOOFA with S=2
TEO:
LOOFA achieves work conservation if S = 2
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OQ emulation with S=4
urgency of a cell=departure time in OQ-current time
MUCF (Most urgent cell first)
During each phase:
1. outputs request their most urgent cells from inputs
2. input grants output with the most urgent cell
3. loser output tries to obtain their next urgent cell
4. when no more matchings are possible, cells aretransferred and the next phase starts
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OQ emulation with S=4
Note: picture reproduced from Balaji Prabhakar and Nick McKeown, "On the Speedup Required f orCombined Input and Output Queued Swi tching.", Computer Systems Technical Report, November 1997
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OQ emulation and speedup 4
TEO:
MUCF with speedup 4 obtains OQ emulation
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CIOQ routers
CIOQ are very promising architectures many degrees of freedom in design
how to balance input/output buffers
how the buffers interact
e.g., by backpressure mechanisms
Several currently designed architectures aresupposed to be CIOQ
Speedup S is becoming closer and closer to 1 inpractical implementations of new switchingarchitectures (CIOQ IQ)
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Outline
IP routers
OQ routers IQ routers Scheduling
Optimal algorithms
Heuristic algorithms
Packet-mode algorithms
Networks of routers QoS support
CIOQ routers
Multicast traffic
Conclusions
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Multicast traffic
Misleading idea:
observe
1. OQ can achieve 100% throughput underany admissible unicast and multicast traffic
2. OQ can be perfectly emulated by CIOQwith S = 2
then, with S = 2 it is possible to achieve100% throughput for multicast traffic
WRONG!
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Multicast traffic
Question: what is the minimum speedup required
to achieve 100% throughput?
unknown!
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Multicast traffic
Possible implementations
copy network before the switching fabric
a multicast cell with f destinations is treated as f cells
possible bandwidth inefficiency
dedicated queue
multicast packets are treated in some specific way1
UC
MC
N
N N
UC+MC
N N
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Multicast traffic: optimal queueing
MC-VOQ queueing
best throughput performance
avoids HOL blocking
2N-1 queues for each input, one for each fanout set
re-enqueuing process out-of-sequence problem
no re-enqueuing some throughput degradation
MC+UC
1
2N-1
N NSwitching Architectures 2011/12
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Multicast traffic: optimal scheduling
The optimal scheduling for multicast trafficcan be defined similarly to unicast traffic
it is a sort of max flow algorithm on all N(2N-1)queues
Many heuristics can be envisagedto approximate it
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Summary
3 main ingredients for IQ schedulingalgorithms: Weight computation
Matching computation
Contention resolution
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Summary
Weight computation obtains the priority of each input queue
the metric can be related to queue length,waiting time of the cell at the HOL,
Contention resolution
whenever the selection is among situationswith equal weights
can be round robin, or random
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Summary
Matching computation computes the matching, trying to maximize
its total weight
can be based on
an iterative search, like in iSLIP, iOCF,iLQF
a matrix greedy approach, like in MUCS,WFA
a reservation vector, like in RPA
a learning approach, like in APSARA
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Summary
Good IQ scheduling algorithms exist: 100% throughput
short delay
limited complexity
Performance differences are significant
only close to saturation
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Summary
Open questions concerning IQschedulers: QoS guarantees
stability of networks of switches
multicast traffic
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ReferencesRouter functions and architectures
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Scheduling in IQ switches
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LaMaire R.O., Serpanos D.N., `Two dimensional round-robin schedulers for packet switches with multipleinput queues'', IEEE/ACM Transaction on Networking, vol.2, n.5, Oct.1994, p.471-482
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Partridge C., et al., `A 50-Gb/s IP router'', IEEE Transactions on Networking, vol.6, n.3, June 1998, pp.237-248
Ajmone Marsan M., Bianco A., Leonard i E., Milia L., ``RPA: a flexible sched uling algorithm for input buffere dswitches'', IEEE Transactions on Communications, vol.47, n.12, Dec.1999, pp.1921-1933
Ajmone Marsan M., Bianco A., Filippi E., Giaccone P.,Leonardi E., Neri F.,``On the behavior of input queueing
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vol.1, pp.112-116, 2001
Serpanos D.N., Antoniadis P.I., ``FIRM: a class of distributed scheduling algorithms for high-speed ATMswitches with multiple input queues'', IEEE INFOCOM 2000, vol.2, pp.548-555, 2000
Ying Jiang, Hamdi, M., A 2-stage matching scheduler for a VOQ packet switch architecture, IEEE ICC 2002,vol.4, pp.2105-2110, 2002
Tassiulas L., ``Linear complexity algorithms for maximum throughput in radio networks and input queuedswitches'', IEEE INFOCOM'98, vol.2, New York, NY, 1998, pp.533-539
Giaccone P., Prabhakar B., Shah D., `Towards simple, high-performance schedulers for high-aggregatebandwidth switches '', IEEE INFOCOM'02, New York, Jun.2002Switching Architectures 2011/12
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Ajmone Marsan M., Bianco A., Giaccone P., Leonardi E., Neri F., ``Pack et scheduling in input-q ueued cell-based switches'', IEEE INFOCOM'01, Anchorage, Alaska, Apr.2001(extended version to appear in IEEETrans. on Networking, about Oct.2002)
Moon S.H., Sung D.K., `High-performance variable-length packet scheduling algorithm for IP traffic'', IEEEGLOBECOM'01, Dec.2001
Scheduling multicast traffic in IQ switches
Hayes J.F., Breault R., Mehmet-Ali M.K., ``Performance analysis of a multicast switch'', IEEE Transactions onCommunications, vol.39, n.4, Apr.1991, pp.581-587
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McKeown N., Prabhakar B., ``Scheduling multicast cells in an input-queued switch'', INFOCOM'96, vol.1, SanFrancisco, CA, Mar.1996, pp.261-278
Prabhakar B., McKeown N., Ahuja R., ``Multicast scheduling for input-queued switches'', IEEE Journal onSelected Areas in Communications, vol.15, n.5, Jun.1997, pp.855-866
Chen W., Chang Y., Hwang W., ``A high performance cell scheduling algorithm in broadband multicastswitching systems'', IEEE GLOBECOM'97, vol.1, New York, NY, 1997, pp.170-174
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Liu Z., Righter R., `Scheduling multicast input-queued switches'', Journal of Scheduling, John W iley & Sons,May 1999
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ReferencesScheduling multicast traffic in IQ switches
Nong G., Hamdi M., ``On the provision of integrated QoS guarantees of unicast and multicast traffic in input-queued switches'', IEEE GLOBECOM'99, vol.3, 1999
Ajmone Marsan M., Bianco A., Giaccone P., Leonardi E., Neri F., ``On the throughput of input-queued cell-based switches with multicast traffic'', IEEE INFOCOM'01, Anchorage Alaska, Apr.2001
Ge Nong, Hamdi M., Providing QoS guarantees for unicast/multicast traffic with fixed/variable-length packetsin multiple input-queued switches, IEEE Symposium on Computers and Communications, pp.166 171, 2001
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QoS support in IQ switches
Tabatabaee V., Georgiadis L., Tassiulas L., ``QoS provisionin g and tracking fluid policies in input queueingswitches'', IEEE INFOCOM'00, New York, Mar.2000
Chang C.S., Lee D.S., Jou Y.S., `Load balanced Birkhoff-von Neumann switches'', 2001 IEEE Workshop onHigh Performance Switching and Routing, 2001, pp.276-280.
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Advanced architectures derived from pure IQ
Iyer S., McKeown N., ``Making parallel packet switches practical'', IEEE INFOCOM'01, Alaska, Mar.2001
Chang C.S., Lee D.S., Jou Y.S., `Load balanced Birkhoff-von Neumann switches'', 2001 IEEE Workshop onHigh Performance Switching and Routing, 2001, pp.276-280
Sivaram R., Stunkel C.B., Panda D.K., HIPIQS: a high-performance switch architecture using input queuing,IEEE Transactions on Parallel and Distributed Systems, vol.13, n.3, pp.275-289, Mar.2002
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M.Andrews, L.Zhang,``Achieving Stability in Networks of Input-Queued Switches'',IEEE INFOCOM 2001,Anchorage, Alaska, Apr.2001, pp.1673-1679
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M. Ajmone Marsan, P. Giaccone, E. Leonardi, F. Neri,``On the Stability of Local Scheduling Policies inNetworks of Packet Switches with Input Queues'', IEEE JSAC, to appear, 2003
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