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OpenDFM for DRC and DFM

Jake Buurma Si2 , Vice President jakeb@si2.org

June 3, 2013

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Overview of Today’s Presentation

• The well known explosion of DRC rules and operations

• The well known paradigm shift in logic design and verification

• Can we apply some cross domain learning from Logic Verification to Pattern Verification?

• How can we abstract pattern complexity when the patterns are increasingly complex?

• Early results from early adopters

6/10/2013

Exploding Size and Complexity of DRC Design Rule Manuals use specialized rules to overcome manufacturing limitations

20% Compound Growth Rate is not sustainable

Complexity Costs: Efficiency, Quality and Time

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Yield Detractor Pattern

Source: Luigi Capodieci, Ph.D DRC+ Global Foundries, DAC 2010

DRM development cycle: Find a yield detractor pattern Transform the pattern into words Transform the words into DRC code Run the DRC code on the patterns Find any missed patterns and repeat

Design Rule Manuals (DRM) cannot be checked algorithmically and human interpretation varies greatly

A word description of a DFM adjustment is open to multiple interpretations

Copying a Paradigm Shift • Years ago, logic designers had the same explosion of

complexity but they survived it, and now thrive on it But it required a paradigm shift

• Maybe it’s time to look at the Pattern Verification problem

differently? Just turn your head to see a rabbit

Can Verification Engineers verify patterns without DRC Rules?

Logic designers no longer slave over gate level net lists

Clearly, separating intent from

implementation has many benefits

OpenDFM: The “RTL” of Physical Verification

Intermediate Representation

OpenDFM Description

Native Rule Deck

Cailbre Lib

Translation

API Socket

RTL Description

Mapping and

Optimization

Gate Level Netlist

High Performance

Low Power

Low Voltage

Intermediate Representation

PVS Lib

ICV Lib

Translation

API Socket

Mapping and

Optimization

High Level Intent

Low Level Implementation

Multiple Technology

Libraries Mentor

Cadence

Synopsys

Separate the pattern verification intent from its implementation

Multiple Technology

Libraries

Pattern Verification without DRC Rules

set NW_S_1 300 drawn_layer -rule_name drawn_1:1 -layer_name NWELL -layer_numbers {1} -data_types {1} -database_type rectilinear check_space -rule_name NW.S.1 -in_layer NWELL -width1_range { 40 60 } -width2_range { 60 80 } -space_less_than $NW_S_1 -length_greater_than 100 -check_corner_region radial -cmnt "NWELL minimum space is $NW_S_1 nm”

Variable Defined

Layer Defined

Pattern Check

A space pattern verification check can include two widths, a length and a corner

extension

Patterns are described by discriminants which define the pattern properties A pattern check is just a list of constants, variables, ranges and options

No DRC rules written

Ranges

Variable Used

Retargeting Functions Find and Fix Yield Detractors • After locating a problematic pattern, the function automatically optimizes the pattern depending on slack area • The most sensitive yield detractors are fixed first making the layout more robust to manufacturing variances • Typical yield increases are 3% - 5% but it can be much higher when early manufacturing has high variability

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adjust_gate_endcap -rule_name poly.3 -out_layer polyAdjusted -in_layer1 active -in_layer2 poly -eol_width _range { 50 60 } -eol_length_greater_equal 65 -endcap_less_than 60 -poly_space_greater_equal 80 -poly_eol_extent_equals 20 -clears_space_greater_equal 70 -clears_eol_extent_equals 15 -set_endcap 75 -cmnt “ Set the gate endcap to 75nm

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No DRC rules written

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The Impact of OpenDFM

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• A higher level of abstraction focused on intent (not implementation) provides a more compact, technology independent description

• Conversion from a high level to a low level is fast and predictable

• A single, high-level description can be mapped and optimized via specialized libraries into a technology dependent implementation

• OpenDFM descriptions can be re-translated targeting different DRC engines reducing the need for expert resources, time and money

• Productivity is improved because the developer focuses on patterns. The translator handles all of the details and finds errors earlier

• In some cases, better verification results occur because the libraries used for mapping and optimization are built by DRC engine experts

Zero loss of verification accuracy and very little loss in performance

What Early Adopters say about OpenDFM

Compact Layer Equations In logic synthesis, Booleans are used in compact logic equations

and (a, b, c …) f = ( a ∙ b ∙ c … ) nand (a, b, c …) f = ( a ∙ b ∙ c … ) ‘ or (a, b, c …) f = ( a + b + c … )

Layer Equations

OpenDFM provides a similar concept: Compact layer equations for derived layers and/or LVS regions

Transcoding a DRM in XML into OpenDFM • An entire DRM for an 45nm process node was developed in XML • Each section of the DRM included an Executable Specification • OpenDFM pattern descriptors were added to the typical words & figures • OpenDFM automatically generated DRC runsets for Calibre, ICV and PVS • The rule decks were run on thousands of patterns with 100% correlation

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DRM in XML Automatic Generation: Calibre ICV PVS Runsets

Coding Verification Intent as Expected Results # Create a Positive bias of device edges

dfmc::adjust_gate_edges -rule_name ade.1 -in_layer1 PC -in_layer2 RX \ -out_layer device_bias_1 -add_bias 10 -marker_layer NW

# Create a Negative bias of device edges dfmc::adjust_gate_edges -rule_name ade.2 -in_layer1 PC -in_layer2 RX \ -out_layer device_bias_2 -add_bias -10 -marker_layer NW

# Write the modified output to a gds file dfmc::write_oasis_layers -rule_name writeGDSoasis \ -file_name adjust_gate_edges.test \ -write_layers { {RX 1} {PC 2} {NW 3} {device_bias_1 10} {device_bias_2 11}}

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A typical test case for OpenDFM is shown on the right. The input patterns are transistors. The expected result is a bias of selected transistors with either a positive or a negative bias.

Expected Result Coded as Test Data

Both over-corrections and under-corrections are caught by comparing to Expected Result

Pattern Generators Test Translation Mapping • Development of the DFM runset requires pattern generated data sets

– Simultaneous variation of the OpenDFM function input parameters – Varying each input parameter over a wide range of values

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Red dots mark the adjustment locations XML description of pattern parameters

Silicon Substrate

Silicon Substrate

STI Oxide

Gate

Source Fin Drain Fin

Field Oxide

Field Oxide Gate

STI Oxide

Gate Oxide

Gate Length

Source

Fin Length

Gate

Field Oxide

Source Source Source Source Source

Oxide

3D Process Parameters Defined in OPEX

20nm FinFET Patterns use three dimensional parameters

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Summary • OpenDFM provides a compact, high level description that

can be translated into the native languages of several, different DRC engines

• Translation of verification intent in OpenDFM to verification implementation in native DRC rules is fast and efficient with no loss of accuracy and very little loss of performance

• Design Rule Manual written in XML can specify the pattern parameters for OpenDFM and automatically generate DRC rules decks for Calibre, ICV and PVS with 100% correlation

It’s time to join the revolution and think in patterns, not code

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THANK YOU!

6/10/2013