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The integration of Open Library Architecture (OLA) libraries within nano-technology design environments can positively impact SoC design cycle times. Consistent calculation of desired information across a standard application programming interface (API) ensures analysis convergence among tools, eliminates data exchange processing and storage requirements, and significantly reduces iterations through design processes steps.
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2002 OLA Developers Conference
Benefits of OLA Integration into Nano-Technology SoC Design
Environments
Benefits of OLA Integration into Benefits of OLA Integration into
NanoNano--Technology SoC Design Technology SoC Design
EnvironmentsEnvironments
Timothy J. Ehrler
Senior Principal Methodology Engineer
SoC Methodology Development
Design Technology Group
Philips Semiconductors
Timothy J. EhrlerTimothy J. Ehrler
Senior Principal Methodology EngineerSenior Principal Methodology Engineer
SoC Methodology DevelopmentSoC Methodology Development
Design Technology GroupDesign Technology Group
Philips SemiconductorsPhilips Semiconductors
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OutlineOutlineOutline
� Introduction
� Technology Advancement
� Design Complexity Trends
� Traditional & Timing Closure Design Flow
� Open Library Architecture (OLA)
� OLA Based Design Flow
� Extended Integration Benefits
� Conclusion
�� IntroductionIntroduction
�� Technology AdvancementTechnology Advancement
�� Design Complexity TrendsDesign Complexity Trends
�� Traditional & Timing Closure Design FlowTraditional & Timing Closure Design Flow
�� Open Library Architecture (OLA)Open Library Architecture (OLA)
�� OLA Based Design FlowOLA Based Design Flow
�� Extended Integration BenefitsExtended Integration Benefits
�� ConclusionConclusion
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IntroductionIntroductionIntroduction
� Technology is reaching to sub-100nm range
� increased density allows greater die functionality
� SoC evolving from multiple ASIC implementations
� increased demand on tools and methodologies
� Timing closure heavily impacts design cycle
� inconsistent/divergent timing algorithms
� tool specific, non-standard/proprietary views
� expanding overhead of information exchange
� OLA positively impacts SoC design cycle
� consistent library-embedded algorithms, timing
� elimination/reduction of information exchange
�� Technology is reaching to subTechnology is reaching to sub--100nm range100nm range
�� increased density allows greater die functionalityincreased density allows greater die functionality
�� SoC evolving from multiple ASIC implementationsSoC evolving from multiple ASIC implementations
�� increased demand on tools and methodologiesincreased demand on tools and methodologies
�� Timing closure heavily impacts design cycleTiming closure heavily impacts design cycle
�� inconsistent/divergent timing algorithmsinconsistent/divergent timing algorithms
�� tool specific, nontool specific, non--standard/proprietary viewsstandard/proprietary views
�� expanding overhead of information exchangeexpanding overhead of information exchange
�� OLA positively impacts SoC design cycleOLA positively impacts SoC design cycle
�� consistent libraryconsistent library--embedded algorithms, timingembedded algorithms, timing
�� elimination/reduction of information exchangeelimination/reduction of information exchange
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Technology AdvancementTechnology Advancement
� Increased gate density >= >= >= >= Moore’s Law�� Increased gate densityIncreased gate density >= >= >= >= >= >= >= >= Moore’s LawMoore’s Law
700
500
350
250
180
130
100
70
50
1993 1995 1997 1999 2001 2003 2005 2007
Fe
atu
re S
ize
(n
m)
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d
q
ck
dff
� Coupling capacitance
�� Coupling Coupling
capacitancecapacitance
Impact on TimingImpact on TimingImpact on Timing
� Decreased cell delay�� Decreased cell delayDecreased cell delay
� Increased IR drop susceptibility�� Increased IR drop susceptibilityIncreased IR drop susceptibility
� Increased input slew, output load dependency�� Increased input slew, output load dependencyIncreased input slew, output load dependency
� Increased interconnect concerns�� Increased interconnect concernsIncreased interconnect concerns
� Signal noise�� Signal noiseSignal noise
� Slew propagation�� Slew propagationSlew propagation
� RLC, not just RC�� RLC, not just RCRLC, not just RC
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2001
2M+ gates average65% > 1M gates40% > 2M gates20% > 3M gates
20012001
2M+ gates average2M+ gates average65% > 1M gates65% > 1M gates40% > 2M gates40% > 2M gates20% > 3M gates20% > 3M gates
2000
1.6M gates average52% > 1M gates30% > 2M gates
20002000
1.6M gates average1.6M gates average52% > 1M gates52% > 1M gates30% > 2M gates30% > 2M gates
1999
1.1M gates average53% < 1M gates18% > 2M gates
19991999
1.1M gates average1.1M gates average53% < 1M gates53% < 1M gates18% > 2M gates18% > 2M gates
Design Complexity TrendsDesign Complexity TrendsDesign Complexity Trends
0
10
20
30
< 2
00
k
20
0-5
00
k
50
0k
-1M
1M
-2M
2M
-3M >3
1999
2000
2001
1999
2000
2001
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IP Reuse TrendIP Reuse Trend
� System solution, not functional design
� Extensive IP, design re-use
�� System solution, not functional designSystem solution, not functional design
�� Extensive IP, design reExtensive IP, design re--useuse
0
50
100
150
200
250
1999 2000 2001
IP Portfolio size
IP Deliveries
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SoC ImplementationSoC ImplementationSoC Implementation
Over 10M gates
Less than 700ps clock slew
Sea of Gates
Cores (DSP, MicroP)
Memories
Analog
Over 10M gatesOver 10M gates
Less than 700ps clock slewLess than 700ps clock slew
Sea of GatesSea of Gates
Cores (DSP, Cores (DSP, MicroPMicroP))
MemoriesMemories
AnalogAnalog
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Design Flow ComplexityDesign Flow Complexity
� Hierarchical design
� IP, complex cores, “glue”
�� Hierarchical designHierarchical design
�� IP, complex cores, “glue”IP, complex cores, “glue”
LOGIC LOGIC
DSP
IP IP Program
Memory
Program
Memory
Program
Memory
Program
Memory
� Increased interconnect
to cell delay ratio
� Complex parasitics
� Xtalk, noise, inductance
�� Increased interconnect Increased interconnect
to cell delay ratioto cell delay ratio
�� Complex parasiticsComplex parasitics
�� XtalkXtalk, noise, inductance, noise, inductance
� Extensive interconnect�� Extensive interconnectExtensive interconnect
� inter-cell, intra-block�� interinter--cell, intracell, intra--blockblock
� inter-block�� interinter--blockblock
� over-the-block�� overover--thethe--blockblock
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Technology & Design InformationTechnology & Design InformationTechnology & Design Information
� Multiple sub-flows
� multiple tools
� multiple algorithms
�� Multiple subMultiple sub--flowsflows
�� multiple toolsmultiple tools
�� multiple algorithmsmultiple algorithms
RTL Development/AnalysisRTL Development/Analysis
Sub-FlowSub-Flow
Sub-FlowSub-Flow
Sub-FlowSub-Flow
Sub FlowSub Flow
Sub-FlowSub-Flow
Sub-FlowSub-Flow
Sub-FlowSub-Flow
Sub-FlowSub-Flow
Sub-FlowSub-Flow
Sub-FlowSub-Flow
Sub-FlowSub-Flow
Sub-FlowSub-Flow
Sub-FlowSub-Flow
Des
ign
Met
hod
olo
gie
sD
esig
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eth
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olo
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s
Tec
hn
olo
gy
Pa
cka
ges
+ L
ibra
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+ I
PT
ech
no
logy
Pa
cka
ges
+ L
ibra
ries
+ I
P
Design SynthesisDesign Synthesis
Logic/Timing VerificationLogic/Timing Verification
Partitioning & Floor PlanningPartitioning & Floor Planning
Layout & Chip FinishingLayout & Chip Finishing
� Multiple libraries
� tool-specific
� representations
�� Multiple librariesMultiple libraries
�� tooltool--specificspecific
�� representationsrepresentations
� Information exchange
� inter-tool
� representations
� interpretation
�� Information exchangeInformation exchange
�� interinter--tooltool
�� representationsrepresentations
�� interpretationinterpretation
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Traditional Design FlowTraditional Design FlowTraditional Design Flow
Contents:Delay CalculationStatic Timing AnalysisGate-level SimulationPower EstimationScreenerVerification of specification
Contents:Contents:
Delay CalculationDelay Calculation
Static Timing AnalysisStatic Timing Analysis
GateGate--level Simulationlevel Simulation
Power EstimationPower Estimation
ScreenerScreener
Verification of specificationVerification of specification
Contents:RTL SimulationArchitectural AnalysisBus interfacesSoftware code developmentRSP platformFeasibility: Performance, Area, Power, Clocking, Test management
Contents:Contents:
RTL SimulationRTL Simulation
Architectural AnalysisArchitectural Analysis
Bus interfacesBus interfaces
Software code developmentSoftware code development
RSP platformRSP platform
Feasibility: Performance, Area, Feasibility: Performance, Area,
Power, Clocking, Test managementPower, Clocking, Test management
Contents:Block level synthesisCreate top level design (CPU, DSP, analog, memory, HDLi templates, I/O, schematics)DFT (scan insertion, MBIST, JTAG, padring)Floorplanning
Contents:Contents:
Block level synthesisBlock level synthesis
Create top level design (CPU, DSP, Create top level design (CPU, DSP,
analog, memory, HDLi templates, analog, memory, HDLi templates,
I/O, schematics)I/O, schematics)
DFT (scan insertion, MBIST, DFT (scan insertion, MBIST,
JTAG, padring)JTAG, padring)
FloorplanningFloorplanning
SPECSPEC
IPIP
Library Models
Library Models
Behavioral RTLDesign
Verilog or VHDL
Behavioral RTLDesign
Verilog or VHDL
Verilog or VHDLRTL description
Verilog or VHDLRTL description
Functional DesignVerilog or VHDL
Functional DesignVerilog or VHDL
LayoutLayoutLayout
Verilog or VHDLStructural Netlist
Verilog or VHDLStructural Netlist
Logic & TimingVerification
Verilog or VHDL
Logic & TimingVerification
Verilog or VHDL
Library Models
Library Models
Test ProgramGeneration
Test ProgramTest Program
GenerationGeneration
SDBSDB
Ref LibsRef Libs
LDBLDB
Ref LibsRef Libs
Ref LibsRef Libs
Contents:Hierarchy planningAutomatic flatten for P&Rpre-route P/G, clock netsArea estimation
Contents:Contents:
Hierarchy planningHierarchy planning
Automatic flatten for P&RAutomatic flatten for P&R
prepre--route P/G, clock netsroute P/G, clock nets
Area estimationArea estimation
Contents:Cell and Block P&RTiming driven extensions
Contents:Contents:
Cell and Block P&RCell and Block P&R
Timing driven extensionsTiming driven extensions
Partitioning &Floorplanning
Partitioning &Floorplanning
Layout:Cell & Block
Layout:Cell & Block
LDBLDB
Layout:Chip Assembly
Design Finishing
Layout:Chip Assembly
Design Finishing
LDBLDB GDS-IIGDS-IILib Rules,
Timing,Package
Lib Rules,Timing,Package
Contents:Insert core & pad fillersSymbolic verificationBond diagram
Contents:Contents:
Insert core & pad fillersInsert core & pad fillers
Symbolic verificationSymbolic verification
Bond diagramBond diagram
VerificationVerification
Contents: DRC, LVS, Plots, Extraction, Circuit Simulation, Back-annotation & Timing Analysis
Contents:Contents: DRC, LVS, DRC, LVS,
Plots, Extraction, Circuit Plots, Extraction, Circuit
Simulation, BackSimulation, Back--annotation annotation
& Timing Analysis& Timing Analysis
To Factory Finishand Mask Making
To Factory FinishTo Factory Finish
and Mask Makingand Mask Making
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Timing Closure FlowTiming Closure FlowTiming Closure Flow
De
sig
n D
ata
ba
se
SDF
StaticTiming
Analysis
SlewReport
DelayCalculation(Parasitics)
LIB
LIB
Netlist
SPEFParasiticsExtraction
Place & RouteClock TreePad Ring
SDF
StaticTiming
Analysis
SlewReport
DelayCalculation
(Custom WL)LIB
LIB
Netlist
CustomWireloads
WireloadExtraction
FormalVerification LIB
FloorPlanning
NetlistSDF
StaticTiming
Analysis
SlewReport
DelayCalculation(Tech. WL)
LIB
LIB
SynthesisOptimization
Scan Insertion
LIB RTL
FormalVerification
LIB
FunctionalSimulation
LIB
ImportLibrary
� Static Timing Analysis (STA) based�� Static Timing Analysis (STA) basedStatic Timing Analysis (STA) based
� Multiple closures�� Multiple closuresMultiple closures
� Closure impediments�� Closure impedimentsClosure impediments� calculation algorithms
� interconnect analysis
�� calculation algorithmscalculation algorithms
�� interconnect analysisinterconnect analysis
� timing view consistency�� timing view consistencytiming view consistency
� timing information
exchange, interpretation
�� timing information timing information
exchange, interpretationexchange, interpretation
� delay calculation
� SDF exchange
�� delay calculationdelay calculation
�� SDF exchangeSDF exchange
� pre-route wireload�� prepre--route wireloadroute wireload
� FP custom wireload�� FP custom wireloadFP custom wireload
� post-rout extraction�� postpost--rout extractionrout extraction
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OLA ConceptOLA ConceptOLA Concept
� Provides single consistent, accurate method for library
information access, calculation
� embedded algorithms for timing, power for all tools
� single “view” so no interpretation, annotation issues
�� Provides single consistent, accurate method for library Provides single consistent, accurate method for library
information access, calculationinformation access, calculation
�� embedded algorithms for timing, power for all toolsembedded algorithms for timing, power for all tools
�� single “view” so no interpretation, annotation issuessingle “view” so no interpretation, annotation issues
OLA(API)
OLA(API)
OLACompliant
Library
Synthesis
Static Timing
Design for Test
Floorplanning
Place & Route
Semiconductor Sign-Off
� Replaces traditional parsing, interpretation of library formats
� compiled library API access instead of textual data
� protect IP from user access and “hacking”
�� Replaces traditional parsing, interpretation of library formatsReplaces traditional parsing, interpretation of library formats
�� compiled library API access instead of textual datacompiled library API access instead of textual data
�� protect IP from user access and “hacking”protect IP from user access and “hacking”
includesTiming
andPower
CalculationRoutines
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OLA Based Design FlowOLA Based Design FlowOLA Based Design Flow� STA sub-flows replaced
� STA tool interfaces with OLA
� tool-specific calculation algorithms
replaced by library embedded ones
� delay calculation tool removed
�� STA subSTA sub--flows replacedflows replaced
�� STA tool interfaces with OLASTA tool interfaces with OLA
�� tooltool--specific calculation algorithms specific calculation algorithms
replaced by library embedded onesreplaced by library embedded ones
�� delay calculation tool removeddelay calculation tool removed
De
sig
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ata
ba
se
StaticTiming
AnalysisNetlist
SPEFParasiticsExtraction
Place & RouteClock TreePad Ring
StaticTiming
Analysis
OLA LIB
Netlist
CustomWireloads
WireloadExtraction
FormalVerification
FloorPlanning
Netlist
StaticTiming
Analysis
SynthesisOptimization
Scan Insertion
RTL
FormalVerification
FunctionalSimulation
De
lay &
Po
we
r Ca
lcu
latio
n S
ys
tem
(OL
A)
� SDF file eliminated
� tools use OLA directly
� timing consistent for all tools
� exchange medium unnecessary
� resource overhead eliminated
� Libraries, views reduced
� consistent information from OLA
� annotation interpretation issues
eliminated
�� SDF file eliminatedSDF file eliminated
�� tools use OLA directlytools use OLA directly
�� timing consistent for all toolstiming consistent for all tools
�� exchange medium unnecessaryexchange medium unnecessary
�� resource overhead eliminatedresource overhead eliminated
�� Libraries, views reducedLibraries, views reduced
�� consistent information from OLAconsistent information from OLA
�� annotation interpretation issues annotation interpretation issues
eliminatedeliminated
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Extended Integration BenefitsExtended Integration BenefitsExtended Integration Benefits
� Power analysis, closure tool support
� more flexible, consistent, accurate power
� in conjunction with timing closure
� Function graph based tool support
� synthesis, optimization
� functional simulation
� formal verification
� Physical, back-end flow support
� floor planning
� placement
�� Power analysis, closure tool supportPower analysis, closure tool support
�� more flexible, consistent, accurate powermore flexible, consistent, accurate power
�� in conjunction with timing closurein conjunction with timing closure
�� Function graph based tool supportFunction graph based tool support
�� synthesis, optimizationsynthesis, optimization
�� functional simulationfunctional simulation
�� formal verificationformal verification
�� Physical, backPhysical, back--end flow supportend flow support
�� floor planningfloor planning
�� placementplacement
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Library, IP Provider BenefitLibrary, IP Provider BenefitLibrary, IP Provider Benefit
� Major Reduction in Supported File Formats
� corresponding reduction of generation/verification requirements
� eliminate generation/translation tool requirements
� reduce generation & verification resources (h/w, personnel, time)
�� Major Reduction in Supported File FormatsMajor Reduction in Supported File Formats
�� corresponding reduction of generation/verification requirementscorresponding reduction of generation/verification requirements
�� eliminate generation/translation tool requirementseliminate generation/translation tool requirements
�� reduce generation & verification resources (h/w, personnel, timereduce generation & verification resources (h/w, personnel, time))
Design Process Tools Standard /Proprietary
Formats
TotalFormats
OLAReplaceable/
Deleteable
TotalFormats
FormatReduction
RTL Development/Analysis 5 3/0 3 2/0 2 33%Design Synthesis 7 4/6 10 4/1 6 40%
Logic/Timing Verification 17 5/11 16 6/5 6 63%Partitioning & Floor Planning 11 3/9 12 5/0 8 33%
Layout & Chip Finishing 21 4/15 19 6/2 12 37%
� Even Greater Savings for Multiple Libraries
� relative to OLA Replaceable/Deleteable numbers
� 16 libraries per technology ~= 16-fold reduction
� dependent on tool set choices and interfaces
�� Even Greater Savings for Multiple LibrariesEven Greater Savings for Multiple Libraries
�� relative to OLA Replaceable/relative to OLA Replaceable/DeleteableDeleteable numbersnumbers
�� 16 libraries per technology ~= 1616 libraries per technology ~= 16--fold reductionfold reduction
�� dependent on tool set choices and interfacesdependent on tool set choices and interfaces
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ConclusionConclusionConclusion
� OLA significantly improves timing closure
� consistent, accurate timing calculation
� timing closure through all design phases
� reduction, elimination of timing iteration cycles
� OLA improves interconnect analysis
� consistent coupling, signal integrity handling
� OLA provides instance specific timing
� PVT per instance for IR drop, thermal issues
� incremental timing “on-demand”
� SDF timing exchange eliminated
� generation, parsing, interpretation, annotation issues gone
�� OLA significantly improves timing closureOLA significantly improves timing closure
�� consistent, accurate timing calculationconsistent, accurate timing calculation
�� timing closure through all design phasestiming closure through all design phases
�� reduction, elimination of timing iteration cyclesreduction, elimination of timing iteration cycles
�� OLA improves interconnect analysisOLA improves interconnect analysis
�� consistent coupling, signal integrity handlingconsistent coupling, signal integrity handling
�� OLA provides instance specific timingOLA provides instance specific timing
�� PVT per instance for IR drop, thermal issuesPVT per instance for IR drop, thermal issues
�� incremental timing “onincremental timing “on--demand”demand”
�� SDF timing exchange eliminatedSDF timing exchange eliminated
�� generation, parsing, interpretation, annotation issues gone generation, parsing, interpretation, annotation issues gone
�Consistent, Accurate Timing Closure Achieved !!!��Consistent, Accurate Timing Closure Achieved !!!Consistent, Accurate Timing Closure Achieved !!!
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Questions & AnswersQuestions & AnswersQuestions & Answers
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BiographyBiographyBiography� Timothy received his BS in Computer and Information Science from The Ohio State
University, College of Engineering, in 1977, taking a position as Test Systems Analyst with
Industrial Nucleonics Corporation, followed shortly thereafter by 14 years with Honeywell Information Systems, now Groupe Bull, in developing and managing their proprietary HDL-
based Design Language System for large mainframe computer system design.
� Timothy joined VLSI Technology, Inc., in 1993 as a staff software engineer, heavily involved in the development of the integrated ASIC design environment, from library view
generation to tool development, during which time he received a patent for timing model
analysis and optimization, with a related patent pending. He subsequently managed the ASIC tools development group for 4 years and, shortly after the acquisition of VLSI by
Philips Semiconductors, became the manager of ASIC Technical Programs, and now holds his present position as Senior Principal Methodology Engineer.
� Timothy has been a contributing member of both the Advanced Library Format (ALF) and
Open Library Architecture (OLA) working groups since their inception. He led the migration effort within VLSI/Philips from a proprietary-based ASIC design environment to that based
on ALF, and is currently leading the effort within Philips Semiconductors in establishing the development and support of OLA libraries and EDA tools.
�� Timothy received his BS in Computer and Information Science fromTimothy received his BS in Computer and Information Science from The Ohio State The Ohio State
University, College of Engineering, in 1977, taking a position University, College of Engineering, in 1977, taking a position as Test Systems Analyst with as Test Systems Analyst with
Industrial Nucleonics Corporation, followed shortly thereafter bIndustrial Nucleonics Corporation, followed shortly thereafter by 14 years with Honeywell y 14 years with Honeywell
Information Systems, now Groupe Bull, in developing and managingInformation Systems, now Groupe Bull, in developing and managing their proprietary HDLtheir proprietary HDL--
based Design Language System for large mainframe computer systembased Design Language System for large mainframe computer system design.design.
�� Timothy joined VLSI Technology, Inc., in 1993 as a staff softwarTimothy joined VLSI Technology, Inc., in 1993 as a staff software engineer, heavily involved e engineer, heavily involved
in the development of the integrated ASIC design environment, frin the development of the integrated ASIC design environment, from library view om library view
generation to tool development, during which time he received a generation to tool development, during which time he received a patent for timing model patent for timing model
analysis and optimization, with a related patent pending. He subanalysis and optimization, with a related patent pending. He subsequently managed the sequently managed the
ASIC tools development group for 4 years and, shortly after the ASIC tools development group for 4 years and, shortly after the acquisition of VLSI by acquisition of VLSI by
Philips Semiconductors, became the manager of ASIC Technical ProPhilips Semiconductors, became the manager of ASIC Technical Programs, and now holds grams, and now holds
his present position as Senior Principal Methodology Engineer.his present position as Senior Principal Methodology Engineer.
�� Timothy has been a contributing member of both the Advanced LibrTimothy has been a contributing member of both the Advanced Library Format (ALF) and ary Format (ALF) and
Open Library Architecture (OLA) working groups since their incepOpen Library Architecture (OLA) working groups since their inception. He led the migration tion. He led the migration
effort within VLSI/Philips from a proprietaryeffort within VLSI/Philips from a proprietary--based ASIC design environment to that based based ASIC design environment to that based
on ALF, and is currently leading the effort within Philips Semicon ALF, and is currently leading the effort within Philips Semiconductors in establishing onductors in establishing
the development and support of OLA libraries and EDA tools.the development and support of OLA libraries and EDA tools.
