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Off Detector Electronics Upgrade. Outline. Present schemes and features New schemes of nSYNC Technology. Present ODE implementation. SYNC. L0 front-end electronics stage 192 LVDS input signals 24 SYNC chips (on 3 types of piggy board) TFC system interface and clock management - PowerPoint PPT Presentation
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Off Detector Electronics Upgrade
S. Cadeddu - INFN Cagliari 2
Outline
• Present schemes and features
• New schemes of nSYNC
• Technology
19/03/2014
S. Cadeddu - INFN Cagliari 3
Present ODE implementation
L0 front-end electronics stage• 192 LVDS input signals • 24 SYNC chips (on 3 types of piggy board)
TFC system interface and clock management• 1 optical receiver + 1 TTCrx chip• 1 QPLL chip• Tree network based on MC100LVEP family
L0 trigger interface• 12 GOL chips + 1 parallel optical transmitter• Valid data transmission @40MHz
L1 DAQ interface• 1 GOL chip + 1 VCSel diode• Valid data transmission @1 MHz
FPGA board controller• Flash RAM based Actel FPGA (ProAsicPlus)• 3 buses (32 bit) for SYNC and GOL interfaces
ECS interface• 1 ELMB board
– CANbus link on the backplane– 2 I2C internal buses
6U Compact PCI card• 10 layers motherboard with controlled impedance• Mixed 5/3.3/2.5 V devices
19/03/2014
SYNC
DAQ inter.
TRG inter.
TFC inter.
GOL
ECS inter.
Controller
S. Cadeddu - INFN Cagliari 4
Present SYNC implementation
19/03/2014
TDC & Synchronizer: • 4 bit TDC (1.5 ns resolution @ 40 MHz) –
DLL based. Custom Macro-cell.L0 Trigger Interface: • Sends 8 synchronized hits along with the
2 LSB of the BX Id @ 40 MHz.• Prog. buffer depthL0 buffer & Derandomizer: • Based on the 128x27 SRAM blocks (CERN
development – K. Kouklinas)• Circular buffer of 256x54 SRAM.• Initial R/W address programmable.• FIFO of 128x54 SRAM• The depth is programmable to 16, 32, 64
or 128.EDAC: • Single Error detection and correction,
Double Error detection. 7 bits code.Histogram Builder: • 16 bins of 224 entries each. I2C Interface• Used to R/W internal configuration.• Configuration Registers are triple voted
and auto-corrected for best SEU immunity.
• All other registers are triple voted
Trigger link testL1 link test
S. Cadeddu - INFN Cagliari 5
SYNC 1.0: The present …
19/03/2014
L0 Buffers L0 Buffers
L0 BuffersL0 Buffers
Derand Derand
TDC’s
VD
D
VDD
VDD
VDD
VDD
VD
D
VD
D
VD
D
GN
D
GN
D
GN
D
GND
GND
GND
GND
8 LVDS Input
Output to L1 electronics
GO
L ou
tput
GND
I2C I2C
I 2CC
TR
LS
SYNC 1.0
97 pins
4x4 mm2
QFP 14x14 100 pins
IBM 0.25 mm RadHard
S. Cadeddu - INFN Cagliari 6
ODE upgrade specs
• Design new boards (nODE), almost “plug & play” with current ODEs– No need to touch cables from chamber to crates– Same transition boards (no crate re-cabling)– Single type of board for all stations/regions
• Use new GBT and versatile link components to implement trigger, DAQ, TFC and ECS interfaces– Optimized number of links to the L0 Muon trigger
• Maintain the trigger unit information on the same link• Possible implementation in the TELL40
– Read TDC data @ 40 MHz rate– No more need to maintain present TFC and ECS systems
• Use a new custom ASIC (nSYNC) to integrate all the required functionalities– Clock synchronization and Bx alignment – Time measurements and histogram capability– Zero suppression algorithm and buffering– Test facilities and diagnostic– Trigger, DAQ, TFC and ECS interfaces via GBTx
• Guarantee enough flexibility to increase granularity and reduce channel occupancy– Possible IB boards replacement in the high occupancy zone – Possible chambers replacement in low granularity zone
19/03/2014
S. Cadeddu - INFN Cagliari 7
nODE Architecture
19/03/2014
nODE
DATA Path
Sync
nSYNC
Bu
nch
cro
ss s
ynch
r.
TDC
Hit format
Hist.
GBT interf.
Zero Supp.
GBT interf.
ECS/TFC
LVD
S R
ecei
vers
Tr
ansl
ato
rs
GBTx Hit data
serializer
VTTx Optical
transmitter
GBT-SCAControlMonitor
VTRx Optical
transceiver
GBTxData
Ser/Des
VTTx Optical
transmitter
GBTx Hit data
serializer
Sync
nSYNC
Bu
nch
cro
ss s
ynch
r.
TDC
Hit format
Hist.
GBT interf.
Zero Supp.
GBT interf.
Sync
nSYNC
Bu
nch
cro
ss s
ynch
r.
TDC
Hit format
Hist.
GBT interf.
Zero Supp.
GBT interf.
Sync
nSYNC
Bu
nch
cro
ss s
ynch
r.
TDC
Hit format
Hist.
GBT interf.
Zero Supp.
GBT interf.
LVD
S R
ecei
vers
Tr
ansl
ato
rsLV
DS
Rec
eive
rs
Tran
slat
ors
LVD
S R
ecei
vers
Tr
ansl
ato
rsLV
DS
Rec
eive
rs
Tran
slat
ors
LVD
S R
ecei
vers
Tr
ansl
ato
rs
Sync
nSYNC
Bu
nch
cro
ss s
ynch
r.
TDC
Hit format
Hist.
GBT interf.
Zero Supp.
GBT interf.
192 Input channels
Power section
Voltage regulators
DC/DC converter
Power up sequencer
Clock management
Clock driver
Phase adjust
Sync
nSYNC
Bu
nch
cro
ss s
ynch
r.
TDC
Hit format
Hist.
GBT interf.
Zero Supp.
GBT interf.
GBTx TDC data serializer
GBTx HIT data serializer
To TELL40 Links
simplex
To Trigger links
simplex
To/from TFC1 linkduplex
S. Cadeddu - INFN Cagliari 8
nSYNC Architecture
19/03/2014
TDC + Histogram builder: • 4 bit TDC (1.5 ns resolution @ 40 MHz)• 16 bins of 224 entries each. The counts stop
when any of the bins saturates. Dead time free in hit capture.
Muon Trigger TELL40 Interface: • Sends synchronized hits every machine cycle
(40 MHz).• Prog. buffer depth to guarantee the
synchronization between different nSYNC sending data through the same GBT
TDC ZS: • Zero Suppression of TDC’s data not related to
hit events.
TDC TELL40 Interface: • Sends synchronized ZS TDC data every
machine cycle (40 MHz).• Prog. buffer depth to guarantee the
synchronization between different nSYNC sending data through the same GBT
I2C Interface: • Configure through the ECS.• Triple-voted configuration
S. Cadeddu - INFN Cagliari 9
SYNC 1.0 vs nSYNC
19/03/2014
8 ch vs 32 ch
Histo for each TDC
No more needs forRAM’s + EDAC
TDC data ZS
97 pins vs 220 pins
S. Cadeddu - INFN Cagliari 10
Why an asic
• Modularity: we are thinking at three possible modularity (32, 48, 96 channels), to best fit the requirements for:– Power consumptions (less then 20mA per channel)– Best ZS for TDC data
• An eye on LS3 stage: If we go to design a new detector with higher granularity for at least M2R1 and M2R2 (and maybe for the same regions of M3 too), we have also to design a new front-end electronics and a new front-end board where we can integrate the nSYNC direct on the detector.
19/03/2014
S. Cadeddu - INFN Cagliari 11
Technologies
IMEC DARE (Design Against Radiation Effects) technology:
• Radiation-hardened-by-design libraries in standard commercial technology– DARE180 well supported (UMC .18)– DARE90 small core & IO library available(UMC 90nm)
• Manufacturing, Packaging, Testing, Characterization (lot) Qualification & Radiation test up to FM is supported by imec’s ASIC Services– Through subcontractors (Microtest, Maser, MAPRAD)
• Flexible solution– DARE allows for mixed signal design
• Can add specific analog blocks; designed by customer, design house or imec• Encrypted models of library cells can be used in analog design ervironment.
– Cells can be added to the library– IO pads can be customized ...
• Imec has expertise on the full DSM design flow • They tested DARE digital blocks up to 1 MRad without failures or
leakage current increases. • SEU performance is in the order of a LET cross-section of 48/60
Mev. 19/03/2014
S. Cadeddu - INFN Cagliari 12
Technologies
DARE UMC 180 Family
19/03/2014
IO a
t 3.3
and
2.5
V
Logic MMRF CIS
combinatorial 50 50 50normal' FF's 20 20 20HIT FF's 20 20 20HIT FF with M1 progr. Reset no no 4Clock Gating cells 3 3 3TIEx 2 2 2Digital IO 40 40 40Analog IO 5 5 6LVDS (extended Com. Mode Range) 3 3 3PLL 1 1 1
SRAM Compiler (6Tor cell) a a noDPRAM Compiler (6Tor cell) a a no
IO
IO
Core 1.8V
pads:- 70x70- 110x110- custom
All FF’s have scan equivalents
+ Fillers & Corners
+ Customer Requests+ Additional Analog IP developed by an external design house (DAC, ADC, ...)
S. Cadeddu - INFN Cagliari 13
nSYNC: work in progress
I2C interface:• Designed and tested in another chip for
a INFN gruppo 5 experiments.
PLL and Delay lines:• These are the main crucial parts for the
TDC implementation as well as the GBT interfaces that needs a different frequencies from the master clock.They are under study and develpment in another INFN gruppo 5 experiment (alldigitall)
19/03/2014
S. Cadeddu - INFN Cagliari 14
All Digital PLL
• An ADPLL include a DCO instead of a VCO
• In most architecture the DCO=DAC+VCO
• In other case the DCO is based on effects of analog components
• The aim of ALLDIGITALL experiment is to realize a true DCO, portable on differenttechnologies (FPGA, ASIC), integrable in a flow fully digital
19/03/2014
S. Cadeddu - INFN Cagliari 15
DCO in 130nm technology
Frequency Range (1.3 – 25.5) ns(770 – 39) MHz
LSB 95 psDNL (+/- 13) ps
19/03/2014
S. Cadeddu - INFN Cagliari 16
DCO in 130nm technology
Frequency Range (0.75 – 39) ns(1250 – 26) MHz
LSB 150 psDNL (+/- 10) ps
19/03/2014