15

CHAPTER 2

LITERATURE REVIEW

2.1 MODELING AND SIMULATION OF MESFET

PHOTODETECTOR

2.1.1 MESFET a general overview

Metal semiconductor field effect transistor (MESFET) has very good

photosensitivity, and hence it is utilized in various optoelectronic applications

such as optical-to-microwave conversion, high-speed optical detection, optical

injection locking and optically controlled amplification and oscillations. In

MESFET, the channel conductivity can be controlled by Schottky barrier gate

which enabled it to be built in monolithic microwave integrated circuits

(MMICs) and optoelectronic integrated circuits (OEICs). A Schottky barrier,

named after Walter H. Schottky, is a potential energy barrier for electrons

formed at a metal semiconductor junction. Schottky barriers have rectifying

characteristics, suitable for use as a diode. A MESFET or metal semiconductor

field effect transistor (FET) uses a reverse biased Schottky barrier to provide a

depletion region that pinches off a conducting channel buried inside the

semiconductor.

MESFET was developed by Mead in 1966. Later, Drangeid et al

(1968) proposed silicon MESFET with a maximum oscillation frequency of 10

GHz. The Schottky contact consists of evaporated Cr and Ni layers. The channel

is a thin epitaxial n-layer on a high-resistive Si substrate. In 1970, Middlehoek

16

realized the silicon-based MESFETs with 1

oscillation frequency of up to 12 GHz for microwave applications. In 1971,

Turner et al (1971) made GaAs-based MESFETs with maximum oscillation

frequency of up to 50 GHz. Such a high performance is attributed to GaAs which

offers superior electrical properties compared to silicon. Beside high frequency

(HF) of oscillation, GaAs MESFETs also provide high output power with low

noise figure.

2.1.2 GaAs MESFET as a photodetector

The Gallium Arsenide MESFET as a photodetector has created an

environment whereby it is now possible to interface optical fibers and high-speed

GaAs analogue-digital circuitry in optical communication links. Low operating

voltage, high switching speed and opto-isolation characteristics of GaAs

MESFETs have resulted in considerable research into uncovering some of the

principles that govern the optical characteristics of the GaAs MESFET as a

photodetector.

Baack et al (1977) reported a low-power, high-speed photodetector

based on GaAs MESFET. The results showed that switching speed of GaAs

MESFET photodetector is double the time faster than avalanche photodiode.

Later, Gammel & Ballantyne (1978) named the optically controlled MESFET as

optical field-effect transistor (OPFET). Mizuno (1983) experimentally proved

that the GaAs MESFETs are very useful in applications such as optically

switched amplification and optical/microwave transformation. Adibi &

Eshraghian (1989) proposed a more complete GaAs MESFET photodetector

model for various modes of operation.

The impact of illumination on the characteristics of MESFET was

consequently researched by a number of researchers to understand the various

17

mechanisms involved and also to look at the possible applications of the device.

Herewith various works carried out with this device are discussed below.

2.1.3 Impact of illumination on the characteristics of GaAs MESFET

photodetector

The DC and dynamic properties of GaAs MESFET are greatly

changed by illumination. Graffeuil et al (1979) analyzed the changes in

transconductance and drain current due to illumination of the Schottky-junction

gate with a light source and noticed a 10% variance in the transconductance and

25% variance in the drain current for a light intensity variation as low as

0.2 mW.

Sugeta & Mizushima (1980) demonstrated the high-speed

photoresponse of a GaAs-MESFET and confirmed the theory that the measured

current pulse heights through the gate and the drain as a function of the gate bias

voltage are caused by the sweep-out effect of photo-generated carriers in the

depletion layer extending from the gate to the drain.

De Salles & Forrest (1981) and De Salles (1983) presented the

performance of GaAs MESFET under illumination considering both the

photovoltaic and photoconductive effects in the active channel and the substrate.

It was concluded that when the incident optical radiation has energy greater than

the band-gap energy of the semiconductor, there will be considerable change in

the DC characteristics. Due to this effect, the intrinsic parameters of the device

change. On the basis of this observation, many possible applications of the

device such as optically controlled amplification and oscillation, injection phase

locking, optical detection and so on were predicted. Later, Seeds & De Salles

(1990) reviewed the use of optical signal to control the operation of microwave

amplifiers, oscillators, switches and mixers.

18

An optical illumination effect on the GaAs MESFET was studied by

Chaturvedi et al (1983). The light-generated voltage was theoretically evaluated

due to the optical radiation (0.87

It was shown that the maximum optical gain can be obtained by illuminating a

normally-off MESFET (i.e. kept in pinch-off condition). Gautier et al (1985)

studied the changes in the static and dynamic characteristics of GaAs MESFET

under illumination considering the photoconductive and photovoltaic

phenomena. In their work, they described how the S-parameters of a GaAs

MESFET are affected by illumination. Using a one-dimensional (1D) model,

they analyzed the photoconductive and photovoltaic DC phenomena in the

channel and in the depletion layer, and showed the light effect on DC

transconductance. Tzu Hung & Michael (1985) presented the first capacitance

model for GaAs MESFET considering the Gunn domain formation which exists

at microwave frequency.

Simons & Bashin (1986) and Simons (1987) experimentally measured

DC and also the microwave characteristics of optically illuminated

AlGaAs/GaAs HEMT with that of GaAs MESFET. Studies were made on an

ion-implanted Si MESFET to observe the optically controlled characteristics by

Singh et al (1986), and it was shown that increase in radiation flux density with

lower wavelength enhances drain-source current and the threshold voltage was

found to be increased under normally ON condition but reduced under normally

OFF conditions. At larger flux densities and lower wavelengths, the effect of

radiation became predominant over the impurity concentration.

Darling & Uyemura (1987) revealed how the thickness of metal gate

determines the amount of absorption of optical radiation in the case of GaAs

MESFET. It was shown that no optical transmission occurs for metal gate with

thickness of about 500 A0. It was also shown that extreme thinning of the gate

metal to achieve good optical radiation absorption must be balanced against the

19

increased series resistance of the gate, which will lower the gain bandwidth

product and increase the noise figure of the device.

Chen (1989) suggested a 2D model to describe the influence of electric

field and mobility profile on GaAs MESFET characteristics. The model included

the calculation of electric field along the channel using 2D numerical

simulations. Chang et al (1990) have developed an analytic model for simulating

the GaAs MESFET drain-induced barrier lowering (DIBL) and its effects on the

device performance. It was found that this model gives an excellent

approximation for the field and potential distributions. The barrier height

between the source and drain in or near the subthreshold region can be accurately

estimated.

Mishra et al (1990) studied the characteristics of an ion-implanted

GaAs MESFET analytically in the below pinch-off region. The effects of optical

radiation and surface recombination were considered for analysis and

photovoltaic effect was not considered. It was observed that the drain-source

current is enhanced by optical radiation significantly if only the electron hole

pair generation is considered. However, the surface recombination, which in turn

results in a gate leakage current, reduces the drain-source current depending on

the density of trap centers. The effect was reversed due to surface recombination,

that is, threshold voltage decreased under the normally ON condition and

increased under the normally OFF condition, with the increase in the trap center

density at a particular ion dose compared to those cases where the effect of

recombination was not considered.

A theoretical model for the I V characteristics of these MESFETs was

presented by Mohamed et al (1990) considering the non-uniform Gaussian

doping for ion-implanted channels. Photo-generated carriers as well as the

doping-generated residual carriers were considered. It was noted that the density

of photo-generated carriers in the channel due to diffusion is much less than that

20

due to drift. Treatment of both under gradual channel approximation and

saturation velocity approximation was presented. The gradual channel and the

velocity saturation approximations were applied to study the I V characteristics

of long-channel and short-channel MESFETs, respectively. Results for both

long-channel and short-channel MESFETs indicated that drain saturation current

and transconductance can be improved by properly fixing the optical flux and the

absorption coefficient of the material.

The effects of deep levels in the substrate of the GaAs MESFET have

been investigated with the aid of 2D numerical simulation by Barton & Snowden

(1990). It was described that the frequency dependence of the output

conductance is explained in terms of a reduction in the magnitude of the

substrate current at low frequencies, as the trap filling varies in response to the

impressed terminal voltages. Comparisons of fast transient and steady state

behavior have shown that deep levels result in an increase in the output

conductance of the device at high frequencies compared to that found with DC

and for low frequencies.

Anholt & Swirhun (1991) have carried out an experiment from

S-parameter measurements and subsequent equivalent-circuit parameter

extraction for a series of 0.25 µm, ion-implanted GaAs MESFETs with different

widths and different gate-source and drain-source spacings and parasitic FET pad

capacitances. The interelectrode capacitances have been separated from

active-FET capacitances. They compared the active-FET fringe capacitances

extracted at pinch-off with results from 2D Poisson simulations.

The models based on the semi-numerical approach were later

developed for optically controlled ion-

Chakrabarti et al (1992) to show how the photovoltaic effect also plays an

important role in the characterization of the device in the illuminated condition.

21

by simple numerical techniques. The characteristics of the devices were obtained

in dark and various illuminated conditions. An attempt had been made here to

improve the existing model of the device by considering the effects of the

photovoltage generated across the metal-semiconductor junction and optical

modulation of depletion edge depths in the illuminated condition. It was

concluded that optical radiation controls the saturation drain current by changing

channel conductance rather than conductivity.

An analytical model for an ion-implanted GaAs OPFET was proposed

by Pal & Chattopadhyay (1992). In this model, the photovoltaic effect and the

voltage dependence of depletion-layer widths in the active region were

considered. It was shown that the threshold voltage decreases in the enhancement

device and increases in the depletion device at a particular dose, flux density and

trap center density. At a higher flux density and trap density, the threshold

voltage showed nonlinear effect at lower value of implanted dose which was

mainly due to the recombination term.

Lo & Lee (1992) studied the photo effects on the I-V characteristics of

GaAs MESFETs by a 2D numerical method. It was theoretically verified that the

photovoltaic effect occurring at the channel/substrate interface is responsible for

the substantial increase of the drain current. The reverse gate current due to

illumination was caused by sweep-out by the high electrical field in the gate

depletion region, where a large gradient in the depth profile of the hole Fermi

energy was found. It was shown that for devices with a lightly doped n-type

buffer layer, the increase of the drain current was less than for devices without a

buffer layer.

An analytical model for the illuminated MESFET was proposed by

Madjar et al (1992) incorporating all of the major contributions to optical

response such as the bias conditions, the wavelength and intensity of the optical

22

input and the particulars of the device structure, and the model was verified with

experimental results.

Rizk et al (1992) proposed an analytical, physically-based, GaAs

MESFET model to generate the parameters of the AC small-signal equivalent

circuit. In the saturated operation, the conducting channel was represented by a

two-resistive part model, namely, the full depletion and graded depletion layer

parts. For a 1-µm gate- length FET, I-V Characteristics were obtained and the

AC equivalent circuit parameters were evaluated as a function of drain source

and gate source bias voltages.

Chang & Lee (1993) have performed 2D simulations on the

side-gating effect in GaAs MESFETs with a realistic configuration, where both

the FET and the side-gate were placed on the surface of the substrate. It was

concluded that substrates which are electron-trap-rich were found to have very

small side-gating effect compared with substrates that are hole-trap-rich. Hole

traps were found to be crucial in spreading out the negative voltages from the

side-gate. However, in electron-trap-rich substrates, Schottky contacts on the

semi-insulating substrate can induce side-gating effect and were found to be

un-doped substrates, Schottky contacts on the semi-insulating substrate were the

major cause for the side-gating effect. The threshold behavior of the side-gating

effect was found to be related to the leakage current of the Schottky-i-n

(side-gate) structure under the influence from the biases of the FET. Both the

injection of holes and the presence of hole traps are essential to the side-gating

effect.

Time-dependent numerical simulations have been performed by

Li et al (1993) to investigate avalanche breakdown and surface deep-level

trapping effects in GaAs MESFETs. Their model was based on a combination of

bipolar drift-diffusion transport, impact ionization, and a dynamic surface

charging mechanism. It was found that at low gate bias, impact ionization at the

23

drain edge results in the breakdown voltage increasing with the magnitude of the

gate voltage as the channel current decreases. On the other hand, at high gate

bias, ionization at the gate edge dominated and caused the breakdown voltage to

decrease with Vgs. The changes in occupation of surface traps under different

bias conditions were also shown to have a significant effect on the magnitude of

the breakdown voltage.

A new empirical-based expression for simulating the bias dependency

of the GaAs MESFET junction capacitance was presented by Rodriguez et al

(1993). It was found that it provides increased accuracy over a wide range of

silicon and GaAs devices for microwave circuit design applications and up to

72% savings in CPU execution speed over existing techniques.

A new I V model was proposed by Chin & Wu (1993) for short gate

length MESFETs operating in the turn on region. By using the conventional 1D

approximation and s potential distribution

supplied by the depletion layer charges was calculated. This was done for gate

and non-gate region. It was shown that the channel potential increased in two

cases, one with the decrease in channel length for fixed drain-source voltage and

another with increasing source-gate voltage for fixed gate length.

Short-channel effects (SCEs) in GaAs MESFETs were investigated by

Adams et al (1993). MESFETs were fabricated with gate lengths in the range of

40 300 nm with GaAs and AlGaAs buffer layers. The use of an AlGaAs buffer

had been shown to reduce the influence of SCEs associated with buffer layer

conduction. They concluded that for shorter gate lengths more severe SCEs

became apparent in the DC transconductance and output conductance which

lessened the advantage of the AlGaAs buffer. They also concluded that the

longer gate length MESFETs also benefitted from an AlGaAs buffer, with

reduced non-barrier-controlled subthreshold buffer currents.

24

The 2D transient simulations of GaAs MESFETs with deep donors in

the semi-insulating substrate have been made by Kazushige & Yasuji (1994). It

-

where the deep donors do not respond to the voltage change and the drain

currents become constant temporarily. The drain currents began to decrease or

increase gradually when the deep donors began to capture or emit electrons,

reaching real steady state values. I V curves were quite different between the

- -

insulating substrate could be the cause for drain-current drifts and hysteresis in

I V curves. Effects of introducing a p-buffer layer were also studied.

GaAs MESFET side-gating effects were studied by Yi et al (1994) by

experiments and analysis of carrier-trapping process in semi-insulating GaAs

substrates using a trapping model. Two mechanisms responsible for side-gating

were revealed. One was the formation of a stationary Gunn domain at the

channel substrate interface. The other was the substrate conduction between a

parasitic Schottky contact and the side-gate due to carrier injection.

A new method of modeling output conductance dispersion in

MESFETs was presented by Jeff et al (1994). HF model parameters were

extracted and used to simulate HF characteristics over a wide range of gate and

drain bias values. The HF models were used to analyze the effect of output

conductance dispersion on logic gate performance.

A numerical method for calculating the I V characteristics of a GaAs

MESFET with ion-implanted layer was presented by Tung (1994). This method

was based on the finding of the channel conductance as a function of the voltage

drop across the metal semiconductor junction, which was related to the

25

The switching characteristics of an optically controlled GaAs

MESFET were modeled by Chakrabarti et al (1994). The limitations of the

existing model were overcome in the present model. Calculations were being

carried out to examine the effect of illumination on the current voltage

characteristics, drain-to-source capacitance, internal gate-to-source capacitance,

drain-to-source resistance, transconductance, the input RC time constant and the

cutoff frequency of a GaAs-MESFET. The variations of these parameters with

gate length and the doping concentration were also studied in dark and

illuminated conditions. An overall decrease in the input RC time constant of the

device in the illuminated condition was shown arising from the internal

gate-to-source capacitance and the transconductance. Madjar et al (1994) also

studied the switching characteristics through theoretical model predicting that the

optical switching performance is a function of the optical signal parameters, the

bias level and the device physics and geometry.

An in-depth, comprehensive, theoretical model of the MESFET s

photoresponse to modulated illumination was presented by Paolella et al (1994).

As predicted by the authors, a marked dependence of the frequency response on

the optical power due to the internal photovoltaic effect was shown. This

in-depth model took into account all photodetection mechanisms in the device,

with expressions provided for the frequency responses of the three fundamental

photodetection processes: photoconductive, external and internal photovoltaic

effects. This model could be used to optimize the response of a given device

through the proper choice of bias and optical signal parameters. Also, it was

possible to optimize the device structure to get maximum response. The

experimental results and the theory showed a relatively poor frequency response

of commercially available microwave MESFETs with the best 3 dB bandwidth

around 100 MHz.

26

Chakrabarti et al (1996) presented an analytical model for determining

the DC characteristics of GaAs-OPFET. The model took into account the effect

of photo-generation in the semi-insulating substrate region and all the major

effects that determine the device characteristics in the illuminated condition. The

semi-insulating nature of substrate was modeled accurately for the first time.

The frequency dispersion of the small-signal transconductance for

GaAs MESFET was analyzed by Lo & Lee (1996) using 2D numerical

simulation. It was confirmed that the bulk traps beneath the n channel were not

responsible for the dispersion. The surface traps at the ungated surface were the

cause of this phenomenon. It was also found that the dominating surface traps are

hole traps. The calculated results showed that the higher transconductances occur

at lower frequencies and a dip in the phase angle at the transition frequency. This

result could be explained by the frequency-dependent modulation of the

gate-to-source and the gate-to-drain resistances caused by the slow behavior of

the charge exchange via the surface states at the un-gated surface region near the

gate edge.

Zebda & Abu Helweh (1997) developed a model of OPFET in which

the carrier lifetime was considered as a function of carrier concentration in the

channel. It was studied that the carrier concentration in the active channel is

altered due to the absorption of the incident light, which affects the carrier

lifetime. The influences of this effect on the device parameters and

characteristics were studied and analyzed. Based on this model the

current voltage characteristics, the gate-source capacitance and the threshold

voltage of the OPFET had been evaluated for different incident light power

intensities.

The nonlinear performance of most widely used GaAs MESFET

model was investigated by Markovic et al (1998). DC, AC and inter-modulation

measurements were done on 300 µm devices and equivalent circuit parameters

27

were extracted. To predict the intrinsic equivalent circuit parameters of the

device from DC data, the measured DC characteristics were first simulated by

employing a nonlinear DC model. The effects of biasing on the device AC

parameters were evaluated. An improvement greater than 10% in predicting the

AC response of the device was observed.

Shubha et al (1998) proposed an analytical modeling for an

ion-implanted GaAs MESFET with a nontransparent Schottky gate, where the

incident radiation was absorbed in the device through the spacings of source,

gate and drain in contradiction to other models where gate was transparent or

semitransparent. Excess carrier generation in the neutral active region, the

extended gate depletion region and the depletion region of active and substrate

junction was modeled by solving the continuity equation. It was shown that the

two controlling parameters are the photovoltage across the channel and the

p-layer junction and that across the Schottky junction due to generation in the arc

region of the gate depletion layer. A significant increase in device current,

channel conductance and transconductance was shown when compared with the

previous models proposed by Pal & Chattopadhyay (1992) and Lo & Lee (1992).

A numerical model of an ion-implanted GaAs OPFET was presented

by Chakrabarti et al (1998). The exact potential profile in the channel and

variation of gate and substrate depletion widths in the channel as a function of

position between source and drain were computed for the first time for a

non-uniformly doped channel.

An OEIC using a single optically gated Indium Gallium Arsenide

MESFET to perform the function of a PD and preamplifier and also a noise

model for this receiver were presented by Chakrabarti & Rajamani (1999). It was

shown that the proposed OEIC receiver has a higher sensitivity, wider bandwidth

and wider dynamic range at a speed of 20 Gb/s compared to OEIC receiver based

on conventional PDs. Bobbo et al (1999) evaluated the performance of GaAs

28

MESFETs through a physical I V model by varying the gate lengths.

Chang-Fetterman electron mobility relationship was used in the analytical

solution of the 2D Poisson equation and current-continuity equation.

A frequency-dependent analytical model of OPFET with improved

absorption under back illumination was presented by Roy & Pal (2000). Instead

of the conventional front illumination through the source, gate and drain, the

device was illuminated through the substrate. Two cases were considered: one in

which the fiber was inserted partially into the substrate, and the other in which

the fiber was inserted up to the active layer substrate interface. The latter case

represents improved absorption in the active layer of the device. The

current voltage characteristics and the transconductance of the device for

different signal-modulated frequencies were obtained. The frequency

dependence of internal and external photovoltages and the photocurrent were

also calculated and discussed. The results indicated significant improvement over

published data using front illumination.

A new analytical model was presented by Bose et al (2000) to show

the photoeffects on the threshold voltage of optically controlled non-self-aligned

short-channel GaAs MESFET by solving 2D

function technique. It was found that when light radiation is allowed to fall on

the gate metal, the threshold voltage of the device shifts increasingly toward the

negative values.

Kuwayama & Kawasaki (2001) reported the significance of the

finite-difference-time-domain method analysis for modeling of an illuminated

GaAs MESFET. It was concluded that the physical model should include various

physical phenomena to simulate accurately. By this method, both active and

passive circuits were analyzed at the same time. As this method was used with

change in time domain, the wide frequency range was analyzed. This method

could be used to simulate the active integrated antenna in the package.

29

Verma & Pal (2001) studied the I V characteristics for a buried-gate GaAs

MESFET under dark and front illumination and their results indicated very good

performance of the device compared to other devices.

Ali et al (2003) have described a high-resolution optical measurement

system, and the system is used to study the drain and gate currents of MESFET

under optical illumination. The high resolution enables external and internal

photovoltaic effects and also the photoconductive effects. The significant

dependence of the optical effect on the bias conditions of the device has also

been highlighted.

An efficient small signal parameters estimation technique for

submicron GaAs MESFETs was studied by Iqbal et al (2004). A software tool

was used which computes the AC behavior of mm wavelength GaAs MESFETs

by using observed DC characteristics. The DC characteristics of a MESFET were

first simulated by using the fabrication parameters of the device which were then

compared with the observed response using S-parameters. Once a good match

was attained by minimizing RMS error values, the device AC parameters were

then evaluated by employing the observed DC data. The developed technique

was highly time efficient because it uses DC measurements for the estimation of

AC parameters of a GaAs MESFET.

Morikuni et al (2005) presented a new analytical model to study the

microwave characteristics of GaAs OPFET in terms of S-parameters under dark

and illuminated conditions. This model was developed to calculate the induced

photovoltage due to the incident illumination on the gate-area of the device. To

make effective and accurate characterization, the Gunn domain capacitance,

domain resistance, transit time effect, low-frequency anomalies and parasitic

elements in the equivalent circuit of MESFET were included.

30

The influence of illumination on characteristics of a non-uniformly

doped GaAs MESFET PD was studied by Mishra et al (2010) by solving the

Monte Carlo Finite Difference method. A 2D channel

potential was modeled for fully depleted (FD) optically biased GaAs MESFET

device with a Gaussian-like doping profile in the vertical direction by Tripathi &

Jit (2011).

equation using the separation of variable technique. Optical radiation dependent

threshold voltage expression was also derived and compared with dark condition.

It was found out that the observed threshold voltage degradation due to SCEs can

be minimized by reducing channel thickness of GaAs MESFET. The proposed

model results were found to be well-matched with the ATLAS simulation data.

The photo effects on the capacitance of optically controlled short gate

length GaAs MESFET were modeled analytically along with the electrical bias

dependencies in the linear as well as saturation region by Patil & Mishra (2012).

The review presented in this section reveals that the GaAs MESFET is

a potential candidate for the application as high-speed photodetector. Though

many theoretical models have been reported by a large number of researchers

over a decade, the more realistic models are yet to be developed for the complete

characterization of the device.

2.2 MODELING AND SIMULATION OF MISFET

PHOTODETECTOR

To attain much higher performances of both FETs and circuits, it is of

great importance to scale down device sizes, especially gate length-without

undesirable SCEs. Among the CMOS family of FETs, MISFET, is chosen due to

its flat impedance over a large frequency range, simplifying impedance matching

for wide band amplifiers, high current drivability, large noise margin, high

breakdown voltage, high channel aspect ratio, low gate leakage and high

31

breakdown voltage for higher power density and compatible accumulation and

depletion mode devices.

With the advent of the technology of III V semiconductors, it has

become possible to develop MISFET structures based on compound

semiconductors by Sze (1981). Quite a large number of MISFET structures

based on III V semiconductors have been proposed, fabricated and tested for

various applications including photodetection. In recent years, the low-noise

MISFET PDs have drawn considerable attention for use in optical receivers due

to its integrated circuit compatibility.

Yamaguchi & Kobayashi (1975) demonstrated the operation of an

enhancement mode MISFET as a new high-gain photodetector. The light was

focused on the semitransparent metal gate to increase the photosensitivity. It was

shown that the photocurrent gain in the order of 103 can be obtained under

application of gate bias. It was explained that the amplification is due to the

increase in the surface channel conductivity via the development of an electron

quasi-Fermi level shift toward the conductive-band edge under illumination.

The multi-finger type Indium Phospide MISFET was fabricated and its

characteristics for HF and high-power application were studied by Nagahama et

al (1984). Its characteristics were compared with GaAs MESFET. It was shown

that double gate (DG) finger type InP MISFETs with 360 µm wide gates have

excellent output characteristics of 310 mW at 8 GHz with 33% power-added

efficiency. The 24 gate-finger type MISFETs with 4800 µm wide gates give

1.5 W output at 10 GHz with 4 dB gain.

Ohata (1990) explained that InP is a promising semiconductor for the

fabrication of FETs for microwave high-power applications because of its

reduced trapping and thus its lower noise over other materials. A charge-sheet

model of a novel InGaAs hetero-gate MISFET was developed by Chakrabarti et

32

al (1991) theoretically to examine its potential as a detector of intensity-

modulated optical signal. It was shown that at a constant gate voltage, the

saturation drain current of the device can be controlled by the incident optical

power and the surface potential at the drain end also decreases with increase of

the incident optical power. The drain conductance was found to increase with the

incident optical power at a constant drain voltage.

A semi-numerical model of an InGaAs/InP: Fe hetero-gate MISFET

was developed by Chakabarti et al (1995) to determine the optically controlled

characteristics of the device. The model involved an analytical solution of the 1D

Poisson equation and computation of surface potential using numerical

techniques in the illuminated condition. Finally, the global characteristics of the

device in the illuminated condition were obtained by numerical integration of the

charge in the inversion region. It was studied that the saturation drain current,

drain conductance and transconductance of the device can be controlled by the

incident optical power at a constant gate voltage. The RC time constant and the

optical responsivity of the device were also calculated.

The design and characterization of a novel high-sensitivity nanoscale

photo MISFET-based OEIC receiver for use in 1.55 µm applications based on

3D numerical modeling has been carried out by Balasubadra et al (2008) to

perform both the functions as PD and preamplifier. The bit error rate (BER) and

sensitivity of the photoreceiver have been computed. The proposed OEIC

receiver had a transimpedance gain of 71.35 dB and the sensitivity at 20 Gbps

for a BER of 10 9

Phade & Mishra (2013) have reported a mathematical model based on

solution of current continuity equation for the optical dependence characteristics

of MISFET with InGaAs as substrate material and InP as insulator. It has been

shown that drain current and transconductance increases significantly in the

33

presence of illumination due to change in carrier concentration of channel

resulting from photo-generated carriers.

2.3 MODELING AND SIMULATION OF SILICON-ON

INSULATOR MOSFET

2.3.1 Modeling of SOI MOSFET by threshold voltage model

SOI MOSFET has two gates simultaneously controlling the charge in

the thin silicon body layer, allowing for two channels of current flow. The

current voltage characteristics of the device with the front channel in strong

inversion and the back channel either in accumulation or in depletion has been

modeled analytically by many researchers. Since SOI films were thin, the

electrical properties of fabricated MOSFETs were inherently influenced by the

charge coupling between the front and back gates. The characteristics of SOI

MOSFET were studied by several researchers through threshold voltage models

which are given below.

Sasaki & Togei (1979) found that threshold voltages for both the

n- and p-channel silicon-on-saffire (SOS) MOSFETs shift toward the more

enhanced mode as epitaxial film thickness decreases. An analytical model was

derived by Worly (1980) for the threshold voltage of an SOS transistor in which

charge coupling between the front and the back gates occurs as in SOI MOSFET,

but only the back silicon surface is depleted. Sano et al (1980) analyzed

numerically the characteristics of MOSFETs fabricated on an epitaxial Si layer

on top of a buried SiO2 equation, the equations for minority-carrier-concentration, for majority-carrier-

concentration and for carrier multiplication due to impact ionization were

iteratively solved for obtaining a self-consistent solution. The threshold shift

with respect to the reduction in silicon film and buried SiO2 thickness was

shown.

34

Ratnakumar & Meindl (1982) proposed a short-channel threshold

voltage model by solving the 2D Poisson equation in the depletion region under

the gate of MOS transistor, and it was found out that the short-channel threshold

voltage depends exponentially on channel length and linearly on drain and

substrate biases. Lim & Fossum (1983) analyzed how the back gate bias along

with the front gate bias may be utilized to control the linear region channel

conductance and for the enhancement of the performance of SOI MOSFET by

deriving the closed form expressions for the threshold voltage under all possible

steady state conditions.

The effect of interface parameters on the threshold voltages of front

and back channels of both the n- and p-type SOI MOSFET structures was

analyzed by Balestra et al (1985). In their

numerically integrated throughout the structure to obtain the electron and hole

densities, potential profile and drain current as a function of front and back-gate

voltages. Lin & Wu (1987) solved the 2D

function technique and calculated the sub-threshold current and threshold

voltage.

Mckitterick & Cavigila (1989) have derived an approximation to

Poisson s equation valid for thin silicon films, assuming that the silicon film is

replaced by a sheet of charge and zero thickness. The results of this model

indicated the difference in properties of long-channel transistors fabricated in

thin SOI from transistors fabricated in thicker SOI films or in bulk films. In

particular, the threshold voltages of the transistors were independent of doping,

the threshold voltages were dependent only logarithmically on the thickness of

the film, and the front threshold voltage was linearly dependent on the back-gate

voltage over a wide range of back-gate voltages.

Matloubian et al (1990) studied an n-channel SOI MOSFET with

floating body that the negative shift in threshold voltage is due to the reduction

35

of threshold voltage by body effect of the forward biased body-to-source

junction. It was shown that by reducing the body-to-source junction diffusion

lifetime or the body doping concentration, an improvement can be achieved in

sub threshold slope at high drain biases.

The temperature dependence of the threshold voltage of the ultra-thin

SOI n-channel MOSFET was presented by Groeseneken et al (1990), and it was

shown that the threshold voltage variation with temperature in thick film SOI

MOSFET and bulk MOSFTs is significantly larger than FD thin film SOI

MOSFETs. Schubert et al (1991) developed a 1D analytical model for

DG controlled SOI MOSFETs and modeled a nonlinear dependence of

front-gate threshold voltage on back-gate voltage if threshold is defined by a

constant current instead of a constant silicon-surface potential. It was

demonstrated by comparison of subthreshold slopes that surface potentials are

not pinned to the onset of strong inversion or accumulation. The statistical

variation of the threshold voltage in bulk and SOI MOSFETs with respect to

device parameters such as channel length, oxide thickness, doping density and so

on was compared by Chen & Li (1992).

It was investigated by Chen et al (1992) that the threshold voltage of

DG FD SOI MOSFET is less sensitive to inherent fluctuations in impurity

distribution and discussed the design considerations for minimizing the statistical

variation of threshold voltage. Guo & Wu (1993) developed 2D analytical

threshold voltage model and derived the solution of the FD

Poisson equation to obtain the front and back surface potential using three zone

Greens function technique. Using the minimum surface potential, the DIBL

effect was analyzed.

Banna et al (1995) investigated the threshold voltage, Vth, of FD SOI

MOSFET with effective channel lengths down to the deep-submicron range

using a simple quasi-2D model to describe the Vth roll-off and drain voltage

36

dependence. It was shown that the shift in threshold voltage is similar to that in

the bulk. However, threshold voltage roll-off in FD SOI was less than that in the

b Vth is independent of

back gate bias in FD SOI MOSFET.

Aggarwal & Gupta (1999) presented thermal characterization of

threshold voltage and SCE of thin film SOI MOSFET. They provided an

absolute expression for temperature-dependent short-channel threshold voltage

reduction and temperature coefficient of threshold voltage of a thin film FD SOI

MOSFET. The model was applicable in the enhanced range of temperature

(25°C

37

induced shallow source/drain (S/D) junctions and investigated the SCEs. They

divided the SOI MOSFETs silicon thin film into three zones and obtained the

surface potential by solving the 2D

Kumar et al (2006) developed a simple and accurate analytical model

for the threshold voltage of nanoscale single-layer FD strained-SOI MOSFETs.

In their work, the 2D Poisson equation was solved considering several

parameters such as the effect of strain, SCE, strained-silicon thin film doping and

thickness and the gate work function and other device parameters. It was shown

that SCEs for channel lengths even less than 50 nm can be successfully

controlled by the application of induced S/D extensions to the SOI MOSFET.

The results were validated with 2D simulation results.

Zhang et al (2007) described the threshold voltage model using a

quasi-2D approximation for deep submicron DG FD SOI PMOS devices by

solving basic semiconductor physical equations. An accurate prediction of SCE

has been obtained by taking into consideration the distribution of minority

carriers in the silicon film, and also a further threshold voltage model including

DIBL effect and interface charge effect was obtained. Results were verified with

MEDICI simulated results.

Rathnamala et al (2009) developed a unified analytical threshold

voltage model for a FD SOI MOSFET. This model was able to handle

non-uniform doping profile in lateral or vertical direction. The 2D Poisson

equation was solved with appropriate boundary conditions using separation of

variable technique and the solution was used to find out the threshold voltage.

An analytical threshold voltage model was developed by Rathnamala et al (2010)

for a non-uniformly doped FD SOI MOSFET to study the random dopant

fluctuation (RDF) effects. The threshold voltage deviation and impact of this

deviation upon other device parameters were studied.

38

Kushwah & Akashe (2013) did the analytical modeling and simulation

of 2D DG nanoscale SOI MOSFET including the calculation of the electrical

field, surface potential, DIBL and threshold voltage, and they have discussed a

model for the drain conductance, drain current, and transconductance. It was

shown that the proposed DG structure provides increased transconductance,

drain current and reduced the electric field, drain conductance and SCEs when

compared with the SG SOI MOSFET. The simulations were done by using

Cadence Virtuoso Tool.

Simple analytical models for the front- and back-gate threshold

voltages and ideality factors with back gate control of lightly doped

short-channel FD SOI ultrathin body and buried oxide thickness MOSFETs was

developed by Fasarakis et al (2014) based on the minimum value of the front and

back surface potentials. Good agreement between the model, simulation and

experimental results were obtained by calibrating the minimum carrier charge

density adequate to achieve the turn-on condition.

2.3.2 Subthreshold behavior of SOI MOSFETs

It is very important to study the characteristics of MOSFET in

subthreshold region for low-voltage operation. The subthreshold behavior of a

MOSFET is characterized by the subthreshold swing (S-factor), which has to be

small enough to ensure low leakage current and sufficient overdrive necessary

for high speed. The dependence of the S-factor on current capability of the

MOSFET has been discussed for the gate length down to Sze 1981). It

was found out by Davis et al (1986) that the drain current versus gate-source

voltage characteristics of certain SOI n-channel MOSFETs have very steep

slopes in the sub threshold region in contradiction to the normal models.

Studying the subthreshold behavior of floating-body SOI MOSFET is

necessary for proper designing and circuit modeling of transistors. The 1D

39

analysis based S-factor of SOI MOSFET models were reported by Mckitterick

(1989), Wouters et al (1990), Balestra et al (1990) and Young (1989), and these

models cannot be applied to short-channel devices where the potential is two

dimensionally distributed. The 2D analysis of subthreshold behavior using

numerical analysis approach has been reported by Edwards (1988) for DG FD

SOI devices.

Fossum et al (1987) found out that the anomalous high slopes of the

current voltage characteristics of an n-channel SOI MOSFET is related with

off-state leakage current, channel length and impact ionization induced body

effect at the drain. Fossum et al (1995) showed that the subthreshold kinks in

current voltage characteristics of a FD SOI MOSFET can be controlled by back

gate bias.

Colinge (1988) presented that the two factors, that is, (1) less impact

ionization due to the reduction of the drain electric field and (2) prevention of

accumulation of holes in the substrate due to reduced substrate source potential

barrier, in the FD SOI n-channel MOSFET, reduces the kink effect in the output

characteristics.

The conduction characteristics of FD SOI MOSFET was studied

through theoretical analysis by Young (1989) and was found that an inverse

subthreshold slope of 59.6 mV/decade can be obtained if the interface-state

capacitances are smaller than gate-oxide capacitance. Woo et al (1989) solved

the 2D 2D

Lapalace equation and studied the reduction in the SCEs in thin film SOI

MOSFETs.

Wouters et al (1990) studied the subthreshold conduction regime in

thick film and thin film SOI MOSFETs. A 1D expression for the subthreshold

slope was derived using the depletion approximation. The model accounted for

40

the influence of the back interface properties on the S-factor in the thin film

regime. The coupling between front and back surface potential and the influence

of the backside conduction on the front interface characteristics were accounted

for.

Balestra et al (1990) proposed analytical models for thin and ultra-thin

film SOI MOSFETs operating in weak or strong inversion considering all the

device parameters. The cases of two and three interfaces with a silicon substrate

were considered in the modeling and compared with one another. These models

gave the main electrical MOSFET parameters in ohmic operation (S-factor and

threshold voltage) for these structures. The analytical models were verified with

the simulated results considering various behaviors depending on the Si film and

the buried insulator thickness, as well as the interface charges, Si film doping or

substrate regime.

The variation of subthreshold slopes with respect to temperature, drain

bias and substrate bias in submicron n-channel FD SOI MOSFETs were

measured by Tokunaga et al (1991). It was observed that the experimental results

can be explained with a simple capacitor model for low drain voltage. For large

negative substrate biases with large drain voltages, strange sharp subthreshold

characteristics were observed. The dependence of this anomalous effect on

substrate bias was explained by a model based on the charge state of the lower

SOI interface.

Joachim et al (1993) found out that S-factor degradation in short-

channel FD SOI MOSFET is governed by three mechanisms: (1) rise in source

and drain end capacitances due to 2D potential distribution; (2) flow of

subthreshold current at the back channel surface and (3) modulation of effective

current channel thickness by gate voltage. It was also reported that this S-factor

can be improved by increasing the channel doping concentration.

41

Hasio & Woo (1995) proposed an analytical current-voltage model in

subthreshold region for a FD SOI MOSFET with SOI channel lengths up to

0.2 µm to predict subthreshold current-voltage, threshold-voltage roll-off and

DIBL. For the analysis, the dependence of effective depletion charge on the drain

bias and the voltage drop in the substrate region underneath the buried oxide

were considered.

2.3.3 Short-channel effects in SOI MOSFETs

Young (1989) studied the short-channel effect in FD SOI MOSFETs

by a 2D analytical model and by computer simulation. It was found that the

vertical field through the depleted film strongly influences the lateral field across

the source and drain regions. It was shown that the short-channel effect can be

significantly reduced by decreasing the silicon film thickness. Sang-Hyun et al

(2000) studied that the SCE in cylindrical surrounding gate MOSFET structure is

less than that in FD DG-MOSFET due to more electrostatic potential

confinement in cylindrical structure. It was found that the channel length of

Cyl-MOSFETs can be scaled 35% more than DG-MOSFETs.

A 2D analytical model for the surface potential variation along the

channel in DM FD SOI MOSFET was developed by Kumar & Chaudhry (2004)

to investigate the SCEs considering all the parameters such as applied drain and

substrate biases, the thickness of the gate, buried oxide and the silicon thin film,

the lengths of the gate metals and their work functions and the S/D and body

doping concentrations. They demonstrated that the surface potential in the

channel region exhibits a step function that ensures the screening of the drain

potential variation by the gate near the drain resulting in suppressed SCEs like

the hot carrier effect (HCE) and DIBL.

Venkateshwar Reddy & Jagadesh Kumar (2004) demonstrated through

2D numerical simulation that the application of single halo in DG SOI MOSFET

42

structures yields better results such as reduced DIBL, threshold voltage roll-up,

high drain output resistance, output characteristics without kink effect and

increase in breakdown voltage. Widiez et al (2005) experimentally evaluated the

influence of gate architecture on the performance of SOI MOSFETs.

Performance of DG SOI MOSFET was compared to single gate and ground

plane SOI MOSFETs with gate lengths down to 40 nm. It was shown that the

DG SOI MOSFETs have the best SCE control than the other two structures.

Jagadesh Kumar & Venkateshwar Reddy (2005) showed that how the

short-channel behavior in sub-100 nm channel range can be improved in an

asymmetrical DG SOI MOSFET by inducing a step surface potential profile at

the back gate and having the front gate made up of two materials with different

work function. Adelmo et al (2005) offered a Lambert function-based analytic

solution of the surface potential of undoped-body symmetric DG devices. The

error produced by the proposed solution compared to exact results was

reasonably small for typical device dimensions and bias conditions.

Bangsaruntip et al (2010) demonstrated the universality of SCEs as a

function of LEFF LEFF

electrostatic scaling length through experimental data from undoped-body

gate-all-around (GAA) silicon nanowire (NW) MOSFETs with different sizes.

They showed that the universality of SCEs is valid for any undoped-body FD

SOI MOSFET. They indicated that LEFF of undoped GAA NW MOSFETs can be

scaled down by ~2.5 times compared with undoped single-gate ETSOI

MOSFETs while maintaining equivalent short-channel control.

Agarwal et al (2011) developed a compact model for PD SOI

DEMOSFETs using a sub-circuit approach. This model showed the special DC

behavior of a PD SOI DEMOSFET transistor. High-voltage effects such as

quasi-saturation and impact ionization in the drift region and floating-body effect

such as the kink effect in the output characteristics were considered. The channel

43

region was modeled using the BSIM4SOI model and the drift region was

modeled using a bias-dependent resistance model. The accuracy of the proposed

compact model was verified using 2D numerical simulations.

2.3.4 Quantum effects in SOI MOSFETs

Quantum effects gradually dominating electronic transport properties

impose severe challenges for device modeling. Numerical simulation considering

quantum effects is a fundamental approach today for exploring characteristics of

emerging nanoscale semiconductor structures and devices. Consequently, a

computationally efficient numerical scheme is of considerable interest because of

the increased numerical complexity.

Quantum-mechanical confinement of inversion-layer carriers

significantly affects the threshold voltage and gate capacitance of highly scaled

MOSFETs. In bulk-Si and partially depleted SOI n-MOSFETs, the confinement

is in the potential well defined by the gate oxide barrier (which is virtually

infinite) and the silicon conduction (or valence) band. In ultra-thin film FD SOI

and DG-MOSFETs, the well is defined by the front- and back-gate oxide

barriers, but the quantum effect can be significantly influenced by the electric

field in the Si film (Janik & Majkusiak 1998). Furthermore, as the film thickness

(tSi) is increased, this influence becomes predominant as in the bulk-Si and

PD/SOI devices.

A compact model for the DG-MOSFET which fully accounts for

quantum mechanical effects, including motion quantization normal to the

Si SiO2 interface, band splitting into sub-bands and non-static effects in the

transport model was presented by Baccarani & Reggiani (1999). The model was

suitable to both in subthreshold and strong inversion and guaranteed a smooth

transition between the two regions. A simplified energy-balance transport model

44

was worked out and the drain-current calculations were compared with Monte

Carlo data.

Lixin & Fossum (2000) presented a compact model for the quantum-

confinement effects for a DG SOI MOSFET with arbitrary silicon film thickness.

It was shown that the threshold-voltage increases due to the carrier-energy

quantization and the gate-capacitance reduction is due to the perturbed carrier

distribution. The model was verified by numerical simulation results obtained

with a self-consistent Schrodinger-Poisson solver, SCHRED.

Naveh & Likharev (2000) have performed numerical modeling of

nanoscale DG ballistic n-MOSFETs with ultra-thin undoped channel, taking into

account the effects of quantum tunneling along the channel and through the gate

oxide. It was shown that transistors with smaller channel length can exhibit

either a transconductance up to 4000 mS/mm or gate modulation of current by

more than 8 orders of magnitude, depending on the gate oxide thickness.

Knoch et al (2002) presented a quantum mechanical simulation of a

single-gated short-channel SOI MOSFET assuming ballistic transport to

investigate ideal device performance. They elaborated the electrical

characteristics and the dependence on the SOI body thickness variation and

doping of source and drain. The results showed that excellent performance can

be achieved for devices with channel lengths down to 15 nm for a single-gated

device layout. The influence of the SOI film roughness was investigated with an

SOI body thickness down to 2.5 nm and showed that high transconductances can

be expected if the doping level in source and drain is chosen appropriately.

Ramey & Ferry (2002) developed an effective potential model

considering the quantum confinement contributed by the rectangular barriers

formed by the gate oxide and the buried oxide in ultra-thin SOI MOSFET using

3D Monte Carlo calculations of the threshold voltage. They found that the

45

effective potential recovers the expected trend in threshold voltage shift with

shrinking silicon thickness, down to a thickness of approximately 3 nm.

Venugopal et al (2003) presented a modeling scheme for simulating

ballistic hole transport in thin-body FD SOI p-MOSFETs. The scheme included

all of the quantum effects associated with hole confinement and also accounts for

valence band non-parabolicity approximately. This simulator was used to

examine the effects of hole quantization on device performance by simulating a

thin (1.5-nm) and thick (5-nm) body DG p-MOSFET in the ballistic limit. The

2D electrostatic effects such as DIBL and off-equilibrium transport were

emphasized as part of this study. The effect of channel orientation on the device

performance was examined by simulating p-MOSFETs with channels directed

along and . Simulated device characteristics for identical

n-MOSFETs and p-MOSFETs were compared.

Jeyadeva & Dasgupta (2009) presented an analytical model for deep

submicron MOSFETs based on quantum charge-sheet approximation including

the drift-diffusion equation. The surface potential was obtained by analytically

considering quantum mechanical effects in the inversion region. The

field-dependent mobility variations, velocity saturation of carriers and secondary

effects such as DIBL and channel length modulation (CLM) were incorporated

in this model. The model calculated the drain current and the channel

conductance accurately for sub-100 nm devices with minimum number of model

parameters.

Bora & Baruah (2011) presented a semi-analytical model for the

current voltage and capacitance voltage characteristics of nanoscaled undoped

symmetric DG-MOSFETs using a parabolic potential approximation for the

body potential. The carrier confinement phenomenon was considered and the

surface electric field was calculated to determine the inversion charge sheet

density. Quantum effects like the threshold voltage shift and increase in the

46

effective oxide thickness were applied through some modifications to the core

model. The results were verified by ATLAS device software.

2.4 NOISE MODELING AND SIMULATION OF SOI MOSFET

The noise performance of FETs has been a subject of study for over a

quarter century. The published studies of noise properties of FETs may be

divided into two distinctive groups. The first group, as a starting point of

analysis, considers fundamental equations of transport in semiconductors. Most

papers in this category published over the years may be viewed as having

progressively more sophisticated treatments of the problem originally tackled by

Van der Ziel. The second group of published studies addresses the issue of what

needs to be known about the device in addition to its equivalent circuit to predict

the noise performance. Over the past decade, a considerable amount of effort has

been taken in analyzing the noise performance of FET-based photodetectors. HF

noise characteristics of modern MOSFETs are becoming increasingly important

for HF circuit design. The major works reported in this area have been reviewed

extensively and presented in this section.

Thermal noise for both n-channel and p-channel silicon MOSFETs

with either a thick oxide (6200 and 8400 A) or thin oxide (2000 A) due to effects

of bulk charge from the semiconductor substrate ionized impurities and gate

voltage-induced channel conductance fluctuations was obtained by Sah et al

(1966). Shoji (1966) analyzed the thermal noise characteristics at HF for

MOSFET in enhancement mode and compared with that of JFET. The mean-

squared gate and drain noises and their correlation were analyzed. It was found

that noise characteristics of JFET and MOSFET are similar, and correlation noise

coefficient is zero at zero drain voltage and 0.395 j at saturation.

The effects of thermal noise on performance and error rates of digital

integrated circuits were analyzed by Layman (1989) for a compact VLSI

47

MOSFET model and the limits to the DRAM design and construction were

highlighted. Low-frequency drain current noise power model for an n-channel

polysilicon-gated SOI MOSFET with SOI film thickness of 100 nm, buried

oxide thickness of 300 nm and gate oxide thickness of 11.5 nm was proposed by

Jian Chen (1990). It was obtained that drain current low noise overshoot has a

width of about 0.7 V and two orders of magnitude higher peak noise power.

Hung et al (1990) presented a physics-based flicker noise power model

applicable to long-channel and sub micron MOSFETs in the linear, saturation

and subthreshold operating regions considering both the oxide-trap induced

carrier number and correlated surface mobility fluctuation mechanisms. An

analytical thermal noise modeling suitable for submicron MOSFETs working in

the saturation region was presented by Triantis (1996) taking into account the

effects such as CLM -dependent

noise temperature and the back-gate effect.

Chen & Deen (1998) proposed a model for microwave frequency

noise sources to predict accurately four noise parameters: reactance of

MOSFETs, minimum noise figure (NFmin), optimized source resistance and

equivalent noise resistance and the intrinsic scattering using two de-embedding

techniques. The authors also proposed a small signal model to calculate the four

noise parameters.

A physically based noise model was proposed by Jin et al (1999) for a

floating body partially depleted SOI MOSFET device and, for the first time, the

shot noise associated with body-source diode current and impact ionization

current was found. It was observed that the floating-body effect is amplifying the

shot noise and it was seen as a Lorentzian-like spectrum.

An extensive experimental study of the HF noise properties of

MOSFET in SOI technology was presented by Dambrine et al (1999). Various

48

gate topologies were fabricated to study the influence of effective channel length,

gate finger width and gate sheet resistivity on the four noise parameters. It was

demonstrated that the main drawback of MOSFET technology in the realization

of ultra-low-noise circuits is its high sensitivity to the minimum noise matching

condition. The increase of the total gate width of transistors by multiplying the

number of fingers connected in parallel appeared to be a solution to improve

minimum noise matching conditions.

A physical-based thermal noise model for floating-body SOI

MOSFET operated in strong inversion regime considering carrier temperature

(significant for short-channel device in saturation region) and the lattice

temperature (unique to SOI due to the buried oxide) was presented by Wei Jin

(2000). Using a Langevin stochastic source term model and small-signal

equivalent circuit of the MOSFET, based on an active transmission line concept

induced gate noise and the drain noise were calculated by Goo et al (2000) to

study the HF noise performance of MOSFETs.

A compact model with simple analytic expressions to investigate the

shot noise associated with the generation and removal (via recombination or a

body contact), and the Lorentzian component dominating the low-frequency

spectra for SOI MOSFETs working under partially depleted FD

conditions, was proposed by Workman & Fossum (2000). It was found that the

FD.

The thermal channel noise of deep-submicron MOS transistors with

HCE was analyzed by Knoblinger et al (2001) through a simple analytical

model, and it was shown that for the correct simulation of the noise performance

of a low-noise amplifier in the GHz range, consideration of HCE is highly

essential. Chen & Deen (2002) presented a new channel noise model using the

CLM effect, the hot electron effect and the noise contributed from the velocity

49

saturation to calculate the channel noise of deep-submicron MOSFETs and was

compared to the channel noise directly extracted from RF noise measurements.

Lee (2003) analyzed the cause of excess noise in ultra-thin gate oxide

MOSFETs and found that it is generated by the trap-related processes, that is, the

slow traps in the oxide producing low-frequency dissipation in the conductance

of oxides and fast traps producing Lorentzian-modulated shot noise associated

with generation recombination process at higher frequencies. For this purpose,

based on an inelastic trap-assisted tunneling transport, a physics-based analytical

model of the gate leakage current noise was presented.

Ong et al (2012) investigated the thermal noise characteristics of

short-channel MOSFETs operating at high frequencies through four different

models such as (1) considering CLM effect only, (2) considering CLM and

velocity saturation effects (VSE), (3) considering CLM and HCE and (4)

considering CLM, VSE and HCE. It was found that the noise reduction due to

the VSE is found to be completely cancelled out by the noise increment due to

the HCE for all the operating conditions.

To accurately design MOSFET-based devices and circuits working at

HF and with low noise, their HF noise modeling is highly needed. There is a

controversy about the HF noises of the MOSFETs. At HF and the MOSFET

operating in strong inversion region, the drain current noise and induced gate

noise are generally accepted as dominated by the thermal noise. But, this is not

the case in subthreshold region. Teng et al (2003) proposed a unified HF drain

current noise and induced gate noise models valid in strong, moderate and weak

inversion regions by unifying the concepts of thermal noise, diffusion noise and

shot noise.

Han et al (2004) modeled the drain current thermal noise for the

n-channel and p-

50

technology taking into account the VSE and the carrier heating effect in gradual

channel region. It was found that the well known Qinv/L2 formula which was

derived previously for long-channel devices was valid even for short-channel

devices. Large excess noise reported previously by some other researchers was

not observed.

Dambrine et al (2003) analyzed the limiting parameters of

deep-submicron MOSFETs for HF applications. It was found that the

degradation of the maximum oscillation frequency is mainly related to the

increase of the parasitic feedback gate-to-drain capacitance and output

conductance with the physical channel length reduction. As a complementary to

the above work, Pailloncy et al (2004) analyzed to find out the parameters that

are limiting the improvement of HF noise characteristics for deep-submicron

MOSFETs through analytical modeling and experimental work with the

downscaling process of the channel gate length. It was demonstrated that the

intrinsic noise parameters are not strongly modified by the device scaling and the

noise performance is mainly due to the frequency performance (fmax) of the

device with the downscaling process as said earlier.

Asgaran et al (2004) developed and experimentally verified an

analytical model for MOSFET noise parameters considering the geometry and

biasing conditions. A HF thermal noise model considering the hot electron effect

and lattice temperature and CLM to analyze the spectral density of drain current

noise in the submicron SOI MOSFETs was presented by Kapoor et al (2005).

Lukyanchikova et al (2003) proposed a semi-empirical model to study

the impact of several electrical and technological parameters on excess

Lorentzian noise in deep-submicron SOI MOSFETs. It was found that this

particular noise originates from shot noise stimulated by the floating body

majority carriers which are injected by electron valence-band tunneling across

the ultra-thin (2.5 nm) gate oxide. Jomaah (2005) presented and illustrated

51

through experimental data the approaches such as the carrier number and the

Hooge mobility fluctuations used for the analysis of the low-frequency noise in

modern CMOS devices.

Fiegna (2003) analyzed the impact of gate leakage current-associated

gate shot noise in MOSFETs by means of analytical models and numerical

device simulation. The effects of shot noise and their dependence on oxide

thickness and on the level of tunneling leakage current (TLC) were analyzed and

it was shown that shot noise dominates over thermal noise at TLC levels above a

threshold value that is an increasing function of frequency.

Han et al (2005) presented a complete physics-based analytical

thermal noise model for the drain thermal noise, the induced gate noise and their

correlation considering the VSE and carrier heating effect for short-channel

MOSFETs. Experimental results have shown that the contribution of hot carriers

in the velocity saturation region to both the drain and gate terminal noises is

negligible and the VSE has more influence on the induced gate noise rather than

the drain thermal noise. With the complete four noise models, measured noise

parameters were excellently modeled for all gate lengths and biases.

Roy et al (2005 & 2006) demonstrated how the compact noise

modeling methodologies like the equivalent circuit-based approach, the classical

Langevin or Klaassen-Prins (2007) approach and the impedance field method

can be adapted to incorporate the mobility degradation due to electric field in

short-channel MOST, and demonstrated the equivalence of these methods in

yielding the same expressions for induced gate and drain noise current. A general

expression of induced gate noise which was valid for any mobility model was

presented for the first time. It was also pointed out that only half of the problem

is solved through this work in compact modeling of noise and the remaining half

is to find a suitable model for the local noise source, which is fully governed by

the noise-generation mechanisms.

52

Warabino et al (2006) developed a HF noise model based on

position-dependent surface potential for short-channel MOSFETs. The induced

gate noise and the cross-correlation noise between drain and gate was studied

without extra model parameters and the gate noise characteristics at GHz

frequencies were accurately calculated. This noise model was implemented in

the complete surface potential-based MOSFET model simulator HiSIM. The

model reproduces measured characteristics for any gate lengths and at any bias

conditions.

Deen et al (2006) developed a compact modeling of the most

important HF noise sources of the MOSFET. Ability of several channel thermal

noise models to predict the channel noise of extremely small devices was

discussed. Using analytical expressions, the impact of technology scaling on

noise performance of MOSFETs was also investigated. The impact of gate

tunneling current at lower frequencies on MOSFETs noise parameters was

studied. Limitations and methods to alleviate them in predicting the HF noise

parameters of modern MOSFETs were addressed.

Jindal (2007) presented analytical expressions for channel thermal

noise and induced gate noise of a long-channel MOSFET in the non-quasi-static

(NQS) regime extending the classical active transmission line analysis. The

analytical expressions exhibited a frequency-squared correction to channel

thermal noise, a fourth power in frequency correction to induced gate noise and a

new real part to the correlation coefficient between the two varying linearly with

frequency. The cross-correlation between the drain and gate noise currents

departed from a purely quadrature relationship because of the presence of a finite

real part which varies linearly with angular frequency. The expressions could be

extended to include the induced substrate current noise and incorporated in

compact models.

53

Yoshioki (2007) developed a shot noise model of a p-n junction in

conjunction with a 2D device simulator to calculate shot noise intensity under

various bias conditions and beyond GHz operational frequency in n-MOSFETs.

It was found that shot noise intensity is independent of frequency and dominated

by subthreshold current at DC or low-frequency region and shot noise intensity

depends on frequency at HF region above GHz frequency and also is much

larger than that of low-frequency region.

An analytical model for floating body SOI as well as bulk silicon

MOS transistors operating at GHz frequencies to analyze the HF noises was

presented by Adan (2008). The model considered the noise mechanisms such as

channel thermal noise, substrate back-gate-coupled thermal noise and shot noise

due to impact ionization. It was found that by reducing back-gate

transconductance, SOI MOSFETs attain lower noise figure than bulk silicon

devices. However, in SOI MOSFETs, due to the floating body, higher drain

electric field and parasitic bipolar action, more shot noise is produced due to

impact ionization. A correlation between the onset voltage and the DC electrical

characteristics was shown.

The HF signal and noise measurements on 40 nm, 80 nm and 110 nm

gate length MOS transistors were performed by Patalay et al (2009). On-wafer

measurements of S-parameters up to 18 GHz yielded an accurate small-signal RF

device model with gm in excess of 1000 mS/mm. Noise contributions due to gate

resistance, substrate resistance, source and drain resistances, substrate current

and induced gate noise were found to be small in comparison with total observed

noise. The noise parameter gamma was bias dependent and increased as channel

length decreased.

Vallur & Jindal (2009) developed analytical expressions for channel

thermal noise and induced gate noise considering mobility degradation and

carrier heating in the NQS regime. The following studies were made through this

54

work for a fixed frequency of operation. (1) Considering both carrier heating and

mobility degradation, drain current noise increased quadratically with electric

field in the NQS regime and is independent of electric field in the QS regime. (2)

In the presence of only HCE, drain current noise increased linearly with electric

field for both QS and NQS models. (3) When only mobility degradation was

present, the drain current noise was actually suppressed for both QS and NQS

cases. (4) Induced gate noise, on the other hand, increased quadratically with

electric field for both QS and NQS analyses in the presence of both mobility

degradation and carrier heating. (5) In the case of pure carrier heating or pure

mobility degradation, the increase in induced gate noise was linear, fairly

independent of transit-time effects. (6) The difference in the behavior of the two

noise currents was understood by the fact that induced gate noise current is a

direct signature of the magnitude of voltage fluctuations across the gate

capacitor, while the corresponding drain current fluctuations are subject to the

extra constraint of carrier mobility degradation in the channel.

Wang et al (2012) examined the HF noise characteristics for

deep-submicron bulk and SOI MOSFETs for various temperatures. They found

that the power spectral density of the channel noise (Sid) of the bulk MOSFET

was less sensitive to temperature with the downscaling of the channel length.

They also showed that floating body and self-heating effects of SOI results in

white-noise gamma factor. Also, they observed the significant decrease in

transconductance by increasing temperature and due to that the NFmin and

equivalent noise resistance are affected.

Dynamic characteristics and noise performance at HF of a

DG-MOSFET with 30 nm gate length using a Monte Carlo simulator was

presented by Yongbo Chen et al (2014). Dynamic response of the device was

analyzed by calculating admittance parameters. The noise behaviors were studied

by calculating the spectral densities of the instantaneous current fluctuations at

55

the drain and gate terminals, together with their cross-correlation. Using the

normalized noise parameters (P, R and C) and NFmin, noise performances of the

device was evaluated. To compare the noise performance, dynamic

characteristics and noise performance of a single-gate SOI MOSFET with the

same gate length was also studied. The results showed that the DG structure

provides better dynamic characteristics and superior HF noise performances such

as larger maximum oscillation frequency (fmax), smaller NFmin and larger

associated gain (Gass), due to its inherent immunity to SCE, lower channel noise

and better gate control ability.