NCL30186 - Quasi-Resonant Controller, Power Factor

© Semiconductor Components Industries, LLC, 2016

September, 2019 − Rev. 31 Publication Order Number:

NCL30186/D

Quasi-Resonant Controller, Power Factor Corrected, Analog/Digital Dimmable

NCL30186The NCL30186 is a controller targeting isolated and non−isolated

“smart−dimmable” constant−current LED drivers. Designed to supportflyback, buck−boost, and SEPIC topologies, its proprietary current−control algorithm provides near−unity power factor and tightly regulatesa constant LED current from the primary side, thus eliminating the needfor a secondary−side feedback circuitry or an optocoupler.

Housed in the SOIC10 which has the same body size as a standardSOIC8, the NCL30186 is specifically intended for very compactspace−efficient designs. The device is highly integrated with aminimum number of external components. A robust suite of safetyprotections is built in to simplify the design. To ensure reliableoperation at elevated temperatures, a user configurable currentfoldback circuit is also provided. In addition, it supports analog andPWM dimming with a dedicated dimming input intended to controlthe average LED current.

Pin−to−pin compatible to the NCL30086, the NCL30186 providesthe same benefits with in addition, an increased resolution of thedigital current−control algorithm for a 75% reduction in the LEDcurrent quantization ripple.

Features• Quasi−resonant Peak Current−mode Control Operation

• Valley Lockout Optimizes Efficiency over the Line/Load Range

• Constant Current Control with Primary Side Feedback

• Tight LED Constant Current Regulation of ±2% Typical

• Power Factor Correction

• Analog or PWM dimming

• Line Feedforward for Enhanced Regulation Accuracy

• Low Start−up Current (10 �A typ.)

• Wide Vcc Range

• 300 mA / 500 mA Totem Pole Driver with 12 V GateClamp

• Robust Protection Features♦ Brown−Out Detection♦ OVP on VCC♦ Programmable Over Voltage / LED Open Circuit

Protection♦ Cycle−by−cycle Peak Current Limit♦ Winding Short Circuit Protection♦ Secondary Diode Short Protection♦ Output Short Circuit Protection♦ Current Sense (CS) Short Detection

♦ User programmable NTC Based Thermal Foldback♦ Thermal Shutdown

• −40 to 125°C Operating Junction Temperature

• Pb−Free, Halide−Free Product

• Four Versions: NCL30186A, B, C and D (See Table 1)

Typical Applications• Integral LED Bulbs

• LED Light Engines

• LED Driver Power Supplies

• Smart LED Lighting Applications

SOIC−10CASE 751BQ

PIN CONNECTIONS

MARKING DIAGRAM

(Top View)

See detailed ordering and shipping information in the packagedimensions section on page 27 of this data sheet.

ORDERING INFORMATION

NC

VCC

DRV

GND

DIM 1

CS

VS

COMP

ZCD

SD

L30186x = Specific Device Codex = A, B, C, D

A = Assembly LocationL = Wafer LotY = YearW = Work Week� = Pb-Free Package

L30186xALYW

�

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http://www.onsemi.com/

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Figure 1. Typical Application Schematic in a Flyback Converter

.

.Aux

.

NCL30186

1

2

3

4

5

8

6

7

9

10

VDIM

Rsense

Figure 2. Typical Application Schematic in a Buck−Boost Converter

.Aux

.

NCL30186

1

2

3

4

5

8

6

7

9

10

VDIM

Rsense


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Table 1. FOUR NCL30186 VERSIONS

Part Number Protection ModeCurrent Regulation Reference Voltage

(VREF)Recommended for (*):

NCL30186A Latching−off 250 mV

Isolated converters.Non−isolated converters with

Vout � 2� � (Vin,rms)LL

NCL30186B Auto−recovery 250 mV

Isolated converters.Non−isolated converters with


NCL30186C Latching−off 200 mV

Non−isolated converters with


NCL30186D Auto−recovery 200 mV

Non−isolated converters with


*(Vin,rms)LL designates the lowest line rms voltage. Refer to AND9217/D for more details. (http://www.onsemi.com/pub_link/Collateral/AND9217−D.PDF).

Table 2. PIN FUNCTION DESCRIPTION

Pin No Pin Name Function Pin Description

1 DIM Analog / PWM Dimming This pin is used for analog or PWM dimming control. An analog signal that can bevaried between VDIM0 and VDIM100 or a PWM signal can be used to adjust theLED current.

2 ZCD Zero Crossing Detection Connected to the auxiliary winding, this pin detects the core reset event.

3 VS Input Voltage Sensing This pin monitors the input voltage rail for:Power Factor CorrectionValley lockoutBrownout Detection

4 COMP Filtering Capacitor This pin receives a filtering capacitor for power factor correction. Typical valuesranges from 1 − 4.7 �F.

5 SD Thermal Foldback andShutdown

Connecting an NTC to this pin allows the user to program thermal current fold-back threshold and slope. A Zener diode can also be used to pull−up the pin andstop the controller for adjustable OVP protection.

6 CS Current Sense This pin monitors the primary peak current.

7 GND − Controller ground pin.

8 DRV Driver Output The driver’s output to an external MOSFET

9 VCC IC Supply Pin This pin is the positive supply of the IC. The circuit starts to operate when VCCexceeds 18 V and turns off when VCC goes below 8.8 V (typical values). Afterstart−up, the operating range is 9.4 V up to 26 V (VCC (OVP ) minimum level).

10 NC − −


https://cma.onsemi.com/pub/Collateral/AND9217-D.PDF

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Internal Circuit Architecture

SDThermalFoldback

Over Temp. Protection

Over Voltage Protection

ZCD

Zero Crossing Detection Logic(ZCD Blanking, Time−Out, ...)

Valley Selection

CS Power Factor andConstant−Current

Control

LeadingEdgeBlanking

Winding andOutput diodeShort Circuit

Protection

Max. PeakCurrent

Limit

Ipkmax

WOD_SCP

DRV

VCC ManagementVCC

DRV

VCC Over VoltageProtection

VCC

InternalThermal

Shutdown

(Auto−recovery or Latched)

FaultManagement

ClampCircuit

VSBrown−Out

BO_NOK

S

R

Q

Q

CS_reset

STOP

UVLO

OFF

Latch

STOP

WOD_SCP

BO_NOK

GND

STOP

Aux. Winding Short Circuit Prot.

Aux_SCP

Aux_SCP

VCC_max

FF_mode

V

Linefeed−forward

VS

VVS

Ipkmax

VTF

VREFVDD

VREF

VVS

Enable

CS ShortProtection

CS_ok

CS_ok

Frequency Foldback

FF_mode

Maximumon time

UVLO on,maxt

on,maxt

VVS

COMP

VREFX

DIMDimmingcontrol

DIM_disable

VREFX

TFV

DIM_disable

DIM_disable

Figure 3. Internal Circuit Architecture

(Auto−recovery or Latched)


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Table 3. MAXIMUM RATINGS TABLE(S)

Symbol Rating Value Unit

VCC(MAX)

ICC(MAX)

Maximum Power Supply voltage, VCC pin, continuous voltageMaximum current for VCC pin

−0.3 to 30Internally limited

VmA

VDRV(MAX)

IDRV(MAX)

Maximum driver pin voltage, DRV pin, continuous voltageMaximum current for DRV pin

−0.3, VDRV (Note 1)−300, +500

VmA

VMAX

IMAX

Maximum voltage on low power pins (except DRV and VCC pins)Current range for low power pins (except DRV and VCC pins)

−0.3, 5.5 (Notes 2 and 5)−2, +5

VmA

RθJ−A Thermal Resistance Junction−to−Air 180 °C/W

TJ(MAX) Maximum Junction Temperature 150 °C

Operating Temperature Range −40 to +125 °C

Storage Temperature Range −60 to +150 °C

ESD Capability, HBM model (Note 3) 3.5 kV

ESD Capability, MM model (Note 3) 250 V

ESD Capability, CDM model (Note 3) 2 kV

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionalityshould not be assumed, damage may occur and reliability may be affected.1. VDRV is the DRV clamp voltage VDRV(high) when VCC is higher than VDRV(high). VDRV is VCC otherwise.2. This level is low enough to guarantee not to exceed the internal ESD diode and 5.5−V Zener diode. More positive and negative voltages can

be applied if the pin current stays within the −2 mA / 5 mA range.3. This device contains ESD protection and exceeds the following tests: Human Body Model 3500 V per JEDEC Standard JESD22−A114E,

Machine Model Method 250 V per JEDEC Standard JESD22−A115B, Charged Device Model 2000 V per JEDEC Standard JESD22−C101E.4. This device contains latch−up protection and has been tested per JEDEC Standard JESD78D, Class I and exceeds ±100 mA.5. Recommended maximum VS voltage for optimal operation is 4 V. −0.3 V to +4.0 V is hence, the VS pin recommended range.

Table 4. ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values TJ = 25°C, VCC = 12 V, VZCD = 0 V, VCS = 0 V, VSD = 1.5 V) For min/max values TJ = −40°C to +125°C, VCC = 12 V)

Description Test Condition Symbol Min Typ Max Unit

STARTUP AND SUPPLY CIRCUITS

Supply VoltageStartup ThresholdMinimum Operating VoltageHysteresis VCC(on) – VCC(off)

Internal logic reset

VCC risingVCC risingVCC falling

VCC(on)

VCC(off)

VCC(HYS)

VCC(reset)

16.08.284

18.08.8−5

20.09.4−6

V

VCC Over Voltage Protection Threshold VCC(OVP) 25.5 26.8 28.5 V

VCC(off) noise filterVCC(reset) noise filter

tVCC(off)

tVCC(reset)

−−

520

−−

�s

Startup current ICC(start) − 13 30 �A

Startup current in fault mode ICC(Fault) 58 75 �A

Supply CurrentDevice Disabled/FaultDevice Enabled/No output load on DRV pinDevice Switching

VCC > VCC(off)

Fsw = 65 kHzCDRV = 470 pF, Fsw = 65 kHz

ICC1

ICC2

ICC3

0.8–−

1.02.63.0

1.24.04.5

mA

CURRENT SENSE

Maximum Internal current limit VILIM 0.95 1.00 1.05 V

Leading Edge Blanking Duration for VILIM tLEB 240 300 360 ns

Propagation delay from current detection to gateoff−state

tILIM − 100 150 ns

6. Guaranteed by Design7. A NTC is generally placed between the SD and GND pins. Parameters RTF(start), RTF(stop), ROTP(off) and ROTP(on) give the resistance the

NTC must exhibit to respectively, enter thermal foldback, stop thermal foldback, trigger the OTP limit and allow the circuit recovery afteran OTP situation.

8. At startup, when VCC reaches VCC(on), the controller blanks OTP for more than 250 �s to avoid detecting an OTP fault by allowing theSD pin voltage to reach its nominal value if a filtering capacitor is connected to the SD pin.


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Description UnitMaxTypMinSymbolTest Condition

CURRENT SENSE

Maximum on−time ton(MAX) 26 36 46 �s

Threshold for immediate fault protection activation VCS(stop) 1.35 1.50 1.65 V

Leading Edge Blanking Duration for VCS(stop) tBCS − 150 − ns

Current source for CS to GND short detection ICS(short) 400 500 600 �A

Current sense threshold for CS to GND short de-tection

VCS rising VCS(low) 30 65 100 mV

GATE DRIVE

Drive ResistanceDRV SinkDRV Source

RSNK

RSRC

−−

1330

−−

�

Drive current capabilityDRV Sink (Note 6)DRV Source (Note 6)

ISNK

ISRC

−−

500300

−−

mA

Rise Time (10% to 90%) CDRV = 470 pF tr – 40 − ns

Fall Time (90% to 10%) CDRV = 470 pF tf – 30 − ns

DRV Low Voltage VCC = VCC(off)+0.2 VCDRV = 470 pF, RDRV = 33 k�

VDRV(low) 8 – − V

DRV High Voltage VCC = VCC(MAX)CDRV = 470 pF, RDRV = 33 k�

VDRV(high) 10 12 14 V

ZERO VOLTAGE DETECTION CIRCUIT

Upper ZCD threshold voltage VZCD rising VZCD(rising) − 90 150 mV

Lower ZCD threshold voltage VZCD falling VZCD(falling) 35 55 − mV

ZCD hysteresis VZCD(HYS) 15 − − mV

Propagation Delay from valley detection to DRVhigh

VZCD falling TDEM − 100 300 ns

Blanking delay after on−time VREFX > 30% VREF TZCD(blank1) 1.12 1.50 1.88 �s

Blanking delay at light load VREFX < 25% VREF TZCD(blank2) 0.56 0.75 0.94 �s

Timeout after last DEMAG transition TTIMO 5.0 6.5 8.0 �s

Pulling−down resistor VZCD = VZCD(falling) RZCD(PD) − 200 − k�

CONSTANT CURRENT AND POWER FACTOR CONTROL

Reference Voltage at TJ = 25°C A and B versionsC and D versions

VREF 245195

250200

255205

mV

Reference Voltage TJ = 25°C to 100°C A and B versionsC and D versions

VREF 242.5192.5

250.0200.0

257.5207.5

mV

Reference Voltage TJ = −40°C to 125°C A and B versionsC and D versions

VREF 240190

250200

260210

mV

Current sense lower threshold VCS falling VCS(low) 20 50 100 mV

Vcontrol to current setpoint division ratio Vratio − 4 − −

Error amplifier gain VREFX = VREF GEA 40 50 60 �S





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CONSTANT CURRENT AND POWER FACTOR CONTROL

Error amplifier current capability VREFX = VREF (no dimming)VREFX = 25%* VREF

IEA ±60±240

�A

COMP Pin Start−up Current Source COMP pin grounded IEA_STUP 140 �A

LINE FEED FORWARD

VVS to ICS(offset) conversion ratio KLFF 18 20 22 �S

Line feed−forward current on CS pin DRV high, VVS = 2 V IFF 35 40 45 �A

Offset current maximum value Ioffset(MAX) 80 100 120 �A

VALLEY LOCKOUT SECTION

Threshold for high− line range (HL) detection VVS rising VHL 2.28 2.40 2.52 V

Threshold for low−line range (LL) detection VVS falling VLL 2.18 2.30 2.42 V

Blanking time for line range detection tHL(blank) 15 25 35 ms

FREQUENCY FOLDBACK

Minimum additional dead time in frequency fold-back mode

tFF1LL 1.4 2.0 2.6 �s

Additional dead time VREFX = 5% VREF tFF2HL − 40 − �s

Additional dead time VREFX = 0% VREF tFF3HL 90 − �s

FAULT PROTECTION

Thermal Shutdown (Note 6) FSW = 65 kHz TSHDN 130 150 170 °C

Thermal Shutdown Hysteresis TSHDN(HYS) − 50 – °C

Threshold voltage for output short circuit or aux.winding short circuit detection

VZCD(short) 0.8 1.0 1.2 V

Short circuit detection Timer VZCD < VZCD(short) tOVLD 70 90 110 ms

Auto−recovery timer duration trecovery 3 4 5 s

SD pin Clamp series resistor RSD(clamp) 1.6 k�

Clamped voltage SD pin open VSD(clamp) 1.13 1.35 1.57 V

SD pin detection level for OVP VSD rising VOVP 2.35 2.50 2.65 V

Delay before OVP or OTP confirmation TSD(delay) 22.5 30.0 37.5 �s

Reference current for direct connection of an NTC(Note 8)

IOTP(REF) 80 85 90 �A

Fault detection level for OTP (Note 7) VSD falling VOTP(off) 0.47 0.50 0.53 V

SD pin level for operation recovery after an OTPdetection

VSD rising VOTP(on) 0.66 0.70 0.74 V

OTP blanking time when circuit starts operating(Note 8)

tOTP(start) 250 370 �s

SD pin voltage where thermal fold−back starts(VREF is decreased)

VTF(start) 0.94 1.00 1.06 V

SD pin voltage at which thermal fold−back stops(VREF is clamped to VREF50)

VTF(stop) 0.64 0.69 0.74 V

VTF(start) over IOTP(REF) ratio (Note 7) TJ = +25°C to +125°C RTF(start) 10.8 11.7 12.6 k�





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FAULT PROTECTION

VTF(stop) over IOTP(REF) ratio (Note 7) TJ = +25°C to +125°C RTF(stop) 7.4 8.1 8.8 k�

VOTP(off) over IOTP(REF) ratio (Note 7) TJ = +25°C to +125°C ROTP(off) 5.4 5.9 6.4 k�

VOTP(on) over IOTP(REF) ratio (Note 7) TJ = +25°C to +125°C ROTP(on) 7.5 8.1 8.7 k�

VREFX @ VSD = 600 mV (as percentage of VREF) SD pin falling (no OTPdetection)

VREF(50) 40 50 60 %

BROWN−OUT

Brown−Out ON level (IC start pulsing) VS rising VBO(on) 0.95 1.00 1.05 V

Brown−Out OFF level (IC shuts down) VS falling VBO(off) 0.85 0.90 0.95 V

BO comparators delay tBO(delay) 30 �s

Brown−Out blanking time tBO(blank) 15 25 35 ms

VS pin Pulling−down Current VS = VBO(on) IBO(bias) 50 250 450 nA

DIMMING SECTION

DIM pin voltage for zero output current(OFF voltage)

VDIM falling VDIM0 0.66 0.70 0.74 V

DIM pin voltage for maximum output current (VREFX = VREF)

TJ = −40°C to +125°CTJ = +25°C to +85°C (NCL30186D only)TJ = +25°C (NCL30186D only)

VDIM rising VDIM100

−2.322.335

2.452.452.450

2.602.572.555

V

DIM pin voltage for 50% output current (VREFX = 50% VREF)

VDIM rising or falling VDIM50 1.35 1.57 1.75 V

Output Current Internal Reference (VREFX) @VDIM = 0.8225 V) (NCL30186D only)

TJ = +25°C to +50°C

VDIM = 0.8225 V VREF7

9.4 14 18.6

mV

Dimming range VDIM(range) 1.75 V

Dimming pin pull−up current source IDIM(pullup) 7.5 9.6 12 �A





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TYPICAL CHARACTERISTICS

Figure 4. VCC Start−up Threshold vs.Temperature

Figure 5. VCC Minimum Operating Voltage vs.Temperature

TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

1251007550250−25−5016.0

16.5

17.0

17.5

18.0

19.0

19.5

20.0

1251007550250−25−508.28.3

8.5

8.7

8.9

9.0

9.2

9.4

Figure 6. Hysteresis (VCC(on) − VCC(off)) vs.Temperature

Figure 7. VCC(reset) vs. Temperature


1251007550250−25−507.5

8.0

8.5

9.0

9.5

10.5

11.0

11.5

1251007550250−25−504.0

4.2

4.6

4.8

5.0

5.4

5.8

6.0

VC

C(o

n) (

V)

VC

C(o

ff) (

V)

VC

C(h

ys) (

V)

VC

C(r

eset

) (V

)

150

18.5

150

8.4

8.6

8.8

9.1

9.3

150

10.0

150

4.4

5.2

5.6


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Figure 8. VCC Over Voltage ProtectionThreshold vs. Temperature

Figure 9. Start−up Current vs. Temperature


1251007550250−25−5025.6

26.0

26.2

26.6

27.0

27.427.6

28.0

1251007550250−25−500

5

10

15

20

30

35

40

Figure 10. Start−up Current in Fault Mode vs.Temperature

Figure 11. ICC1 vs. Temperature


1251007550250−25−500

25

50

75

100

125

150

1251007550250−25−500.4

0.6

0.8

1.0

1.2

1.6

1.8

2.0

Figure 12. ICC2 vs. Temperature Figure 13. ICC3 vs. Temperature


1251007550250−25−501.2

1.6

2.0

2.42.6

3.0

3.4

3.8

1251007550250−25−501.0

1.5

2.0

2.5

3.0

4.0

4.5

5.0

VC

C(o

vp) (

V)

I CC

(sta

rt) (�A

)

I CC

(sfa

ult) (�A

)

I CC

1 (m

A)

I CC

2 (m

A)

I CC

3 (m

A)

150

25.8

26.4

26.8

27.2

27.8

150

25

150 150

1.4

150

1.4

1.8

2.2

2.8

3.2

3.6

150

3.5


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Figure 14. Maximum Internal Current Limit vs.Temperature

Figure 15. Leading Edge Blanking vs.Temperature


1251007550250−25−500.95

0.97

0.98

1.00

1.03

1.05

1251007550250−25−50200

220

240

260

280

320

340

400

Figure 16. Current Limit Propagation Delay vs.Temperature

Figure 17. Maximum On−time vs. Temperature


1251007550250−25−500

10

50

70

100

120

150

1251007550250−25−503032

34

38

40

44

48

50

Figure 18. VCS(stop) vs. Temperature Figure 19. Leading Edge Blanking Duration forVCS(stop) vs. Temperature


1251007550250−25−501.38

1.42

1.46

1.48

1.50

1.54

1.60

1251007550250−25−50100110

130

140

170

210220

VIL

IM (

V)

TLE

B (

ns)

TIL

IM (

ns)

TO

N(m

ax) (�s)

VC

S(s

top)

(V

)

TB

CS (

ns)

150

0.96

0.99

1.01

1.02

1.04

150

300

150 150

42

150

1.40

1.44

1.52

1.58

150

180

360

380

203040

60

8090

110

130140

36

46

1.56

120

150

190

160

200


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Figure 20. ICS(short) vs. Temperature Figure 21. VCS(low), VCS Rising vs.Temperature


1251007550250−25−50400

420

440

480

540

560

600

1251007550250−25−5020

30

40

50

60

80

90

100

Figure 22. Sink Gate Drive Resistance vs.Temperature

Figure 23. Source Gate Drive Resistance vs.Temperature


1251007550250−25−500

2

6

10

12

16

20

1251007550250−25−5010

1416

20

24

32

36

40

Figure 24. Gate Drive Rise Time vs.Temperature

Figure 25. Gate Drive Fall Time(CDRV = 470 pF) vs. Temperature


1251007550250−25−500

15

25

35

40

50

1251007550250−25−5005

10

20

25

40

45

50

I CS

(sho

rt) (�A

)

VC

S(lo

w) (

mV

)

RS

NK (�

)

RS

RC

(�

)

t r (n

s)

t F (

ns)

150

460

500

520

580

150

70

150 150

28

150

5

10

20

30

45

150

30

4

8

14

18

12

18

22

26

30

34

38

15

35


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Figure 26. DRV Low Voltage vs. Temperature Figure 27. DRV High Voltage vs. Temperature


1251007550250−25−508.2

8.4

8.6

8.8

9.4

9.8

1251007550250−25−5010.010.5

11.0

12.0

12.5

13.5

14.5

15.0

Figure 28. Upper ZCD Threshold Voltage vs.Temperature

Figure 29. Lower ZCD Threshold vs.Temperature


1251007550250−25−5030

50

70

90

100

130

150

1251007550250−25−5030

35

40

50

55

70

75

80

Figure 30. ZCD Hysteresis vs. Temperature Figure 31. ZCD Blanking Delay vs.Temperature


1251007550250−25−5005

15

25

35

40

50

1251007550250−25−501.0

1.1

1.2

1.4

1.5

1.7

1.9

2.0

VD

RV

(low

) (V

)

VD

RV

(hig

h) (

V)

VZ

CD

(ris

ing)

(m

V)

VZ

CD

(fal

ling)

(m

V)

VZ

CD

(HY

S) (

mV

)

t ZC

D(b

lank

1) (�s)

150

9.0

9.2

9.6

150

13.0

150 150

60

150

10

20

30

45

150

1.6

11.5

14.0

40

60

80

110

120

140

45

65

1.3

1.8


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Figure 32. ZCD Time−out vs. Temperature Figure 33. Reference Voltage vs. Temperature(A and B versions)


1251007550250−25−505.8

6.2

6.6

7.0

7.2

7.4

7.8

1251007550250−25−50244245

247

248

250

253

254

256

Figure 34. Current Sense Lower Threshold(VCS Falling) vs. Temperature

Figure 35. Error Amplifier Trans−conductanceGain vs. Temperature


1251007550250−25−5010

20

40

60

80

90

110

1251007550250−25−5042

44

46

48

50

56

58

60

Figure 36. Feedforward VVS to ICS(offset)Conversion Ratio vs. Temperature

Figure 37. Line Feedforward Current on CSPin (@ VVS = 2 V) vs. Temperature


1251007550250−25−5018.0

18.5

19.0

20.0

21.5

22.0

1251007550250−25−5036

37

38

39

40

42

43

44

TT

IMO

(�s)

VR

EF (

mV

)

VC

S(lo

w) (

mV

)

GE

A (�S

)

KLF

F (�S

)

I FF (�A

)

150

6.0

6.4

6.8

7.6

150

251

150 150

54

150

19.5

20.5

21.0

150

41

246

249

252

255

30

50

70

100

52


NCL30186

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Figure 38. Ioffset(MAX) vs. Temperature Figure 39. Threshold for High−line RangeDetection vs. Temperature


1251007550250−25−5080

85

90

95

110

120

1251007550250−25−502.25

2.30

2.35

2.40

2.50

2.55

Figure 40. Threshold for Low−line RangeDetection vs. Temperature

Figure 41. Blanking Time for Low−line RangeDetection vs. Temperature


1251007550250−25−502.20

2.25

2.35

2.40

2.50

2.55

2.60

1251007550250−25−5020

22

24

28

30

34

38

40

Figure 42. Threshold Voltage for Output ShortCircuit Detection vs. Temperature

Figure 43. Short Circuit Detection Timer vs.Temperature


1251007550250−25−500.80

0.85

1.00

1.15

1.20

1251007550250−25−5075

80

85

90

95

105

110

115

I offs

et(M

AX

) (�A

)

VH

L (V

)

VLL

(V

)

TH

L(bl

ank)

(m

s)

VZ

CD

(sho

rt) (

V)

t OV

LD (

ms)

150

100

105

115

150

2.45

150 150

32

150

0.90

0.95

1.05

1.10

150

100

2.30

2.45

26

36


NCL30186

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Figure 44. Auto−recovery Timer Duration vs.Temperature

Figure 45. SD Pin Clamp Series Resistor vs.Temperature


1251007550250−25−503.00

3.25

3.50

3.75

4.50

5.00

1251007550250−25−501.001.10

1.30

1.40

1.60

1.90

2.00

2.20

Figure 46. SD Pin Clamp Voltage vs.Temperature

Figure 47. SD Pin OVP Threshold Voltage vs.Temperature


1251007550250−25−501.101.15

1.30

1.35

1.45

1.50

1.60

1251007550250−25−502.40

2.42

2.44

2.46

2.50

2.54

2.56

2.58

Figure 48. TSD(delay) vs. Temperature Figure 49. IOTP(REF) vs. Temperature


1251007550250−25−5022

24

30

38

1251007550250−25−507980

82

83

85

88

89

91

Tre

cove

ry (

s)

RS

D(c

lam

p) (

k�)

VS

D(c

lam

p) (

V)

VO

VP (

V)

TS

D(d

elay

) (�s)

I OT

P(R

EF

) (�A

)

150

4.00

4.25

4.75

150

1.70

150 150

2.52

150

26

28

32

34

36

150

86

1.20

1.50

1.80

2.10

1.20

1.25

1.40

1.55

2.48

81

84

87

90


NCL30186

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Figure 50. RTF(start) vs. Temperature Figure 51. RTF(stop) vs. Temperature


1251007550250−25−5011.0

11.211.3

11.6

11.9

12.112.2

12.5

1251007550250−25−507.67.7

7.9

8.0

8.2

8.5

8.7

8.8

Figure 52. ROTP(off) vs. Temperature Figure 53. ROTP(on) vs. Temperature


1251007550250−25−505.4

5.5

5.7

5.9

6.0

6.3

6.4

1251007550250−25−507.67.7

7.9

8.0

8.2

8.5

8.6

8.8

Figure 54. Ratio VREF(50) over VREF vs.Temperature

Figure 55. Brown−out ON Level vs.Temperature


1251007550250−25−5045

48

50

52

53

55

1251007550250−25−500.95

0.96

0.97

0.98

0.99

1.03

1.04

1.05

RT

F(s

tart

) (k�

)

RT

F(s

top)

(k�

)

RO

TP

(off)

(k�

)

RO

TP

(on)

(k�

)

VR

EF

(50)

(%

)

VB

O(o

n) (

V)

150

11.1

11.5

11.7

12.0

12.4

150

8.3

150 150

8.4

150

46

47

49

51

54

150

1.01

11.4

11.8

12.3

7.8

8.1

8.4

8.6

5.6

5.8

6.1

6.2

7.8

8.1

8.3

8.7

1.00

1.02


NCL30186

www.onsemi.com18


Figure 56. Brown−out OFF Level vs.Temperature

Figure 57. Brown−out Blanking Time vs.Temperature


1251007550250−25−500.85

0.86

0.87

0.89

0.91

0.92

0.93

0.95

1251007550250−25−5020

22

2425

27

31

33

35

Figure 58. VS Pin Pulling−down Current vs.Temperature

TJ, JUNCTION TEMPERATURE (°C)

1251007550250−25−500

50

200

250

300

400

500

VB

O(o

ff) (

V)

t BO

(bla

nk) (

ms)

I BO

(bia

s) (

nA)

150

0.88

0.90

0.94

150

29

150

21

23

26

28

30

32

34

100

150

350

450


NCL30186

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Application Information

The NCL30186 is a driver for power−factor correctedflyback and non−isolated buck−boost/ SEPIC converters. Itimplements a current−mode, quasi−resonant architectureincluding valley lockout and frequency fold−backcapabilities for maintaining high−efficiency performanceover a wide load range. A proprietary circuitry ensures bothaccurate regulation of the output current (without the needfor a secondary−side feedback) and near−unity power factorcorrection. The circuit contains a suite of powerfulprotections to ensure a robust LED driver design without theneed of extra external components or overdesign• Quasi−Resonance Current−Mode Operation:

implementing quasi−resonance operation in peakcurrent−mode control, the NCL30186 optimizes theefficiency by turning on the MOSFET when itsdrain−source voltage is minimal (valley). In light−loadconditions, the circuit changes valleys to reduce theswitching losses. For a stable operation, the valley atwhich the MOSFET switches on remains locked untilthe input voltage or the output current set−pointsignificantly changes.

• Primary−Side Constant−Current Control withPower Factor Correction: a proprietary circuitryallows the LED driver to achieve both near−unitypower factor correction and accurate regulation of theoutput current without requiring any secondary−sidefeedback (no optocoupler needed). A power factor ashigh as 0.99 and an output current deviation below ±2%are typically obtained.

• Linear or PWM dimming: the DIM pin allowsimplementing both analog and PWM dimming.

• Main protection features:♦ Over Temperature Thermal Fold−back/

Shutdown/Over Voltage Protection: theNCL30186 features a gradual current foldback toprotect the driver from excessive temperature downto 50% of the programmed current. If thetemperature continues to rise after this point to asecond level, the controller stops operating. Thismode would only be expected to be reached undernormal conditions if there is a severe fault. The firstand second temperature thresholds depend on the

NTC connected to the circuit SD pin. The SD pincan also be used to shutdown the device by pullingthis pin below the VOTP(off) min level. A Zenerdiode can also be used to pull−up the pin and stopthe controller for adjustable OVP protection. Bothprotections are latching−off (A and C versions) orauto−recovery (the circuit can recover operationafter 4−s delay has elapsed − B and D versions).

♦ Cycle−by−cycle peak current limit: when thecurrent sense voltage exceeds the internal thresholdVILIM, the MOSFET is immediately turned off.

♦ Winding or Output Diode Short−CircuitProtection: an additional comparator senses the CSsignal and stops the controller if it exceeds 150% xVILIM for 4 consecutive cycles. This feature canprotect the converter if a winding is shorted or if theoutput diode is shorted or simply if the transformersaturates. This protection is latching−off (A and Cversions) or auto−recovery (B and D versions).

♦ Output Short−circuit protection: if the ZCD pinvoltage remains low for a 90−ms time interval, thecontroller detects that the output or the ZCD pin isgrounded and hence, stops operation. This protectionis latching−off (A and C versions) or auto−recovery(B and D versions).

♦ Open LED protection: if the VCC pin voltageexceeds the OVP threshold, the controller shutsdown and waits 4 seconds before restartingswitching operation.

♦ Floating or Short Pin Detection: NCL30186protections aid in pass safety tests. For instance, thecircuit stops operating when the CS pin is groundedor open.

Power Factor and Constant Current ControlThe NCL30186 embeds an analog/digital block to control

the power factor and regulate the output current bymonitoring the ZCD, VS and CS pin voltages (signals ZCD,VS and VCS of Figure 59). This circuitry generates thecurrent setpoint (VCONTROL/4) and compares it to thecurrent sense signal (VCS) to dictate the MOSFET turningoff event when VCS exceeds VCONTROL/4.

Power Factor andConstant−Current

Control

PWM Latch reset

STOP VVS REFV

COMP

ZCD

C1

CSV

DIM_disable

Figure 59. Power Factor and Constant−Current Control


NCL30186

www.onsemi.com20

The VS pin provides the sinusoidal reference necessaryfor shaping the input current. The obtained current referenceis further modulated so that when averaged over a half−lineperiod, it is equal to the output current reference (VREFX).This averaging process is made by an internal OperationalTrans−conductance Amplifier (OTA) and the capacitorconnected to the COMP pin (C1 in Figure 59). TypicalCOMP capacitance is 2.2 �F and should not be less than 1 �Fto ensure stability. The COMP ripple does not affect thepower factor performance as the circuit digitally eliminatesit when generating the current setpoint.

If the VS pin properly conveys the sinusoidal shape, powerfactor will be close to 1. Also, the Total Harmonic Distortion(THD) will be low, especially if the output voltage ripple issmall. In any case, the output current will be well regulatedfollowing the equation below:

Iout �VREFX

2NPSRsense(eq. 1)

Where:• NPS is the secondary to primary transformer turns NPS

= NS / NP

• Rsense is the current sense resistor (see Figure 1).

• VREFX is the output current internal reference. VREFX =VREF (250 mV in A and B versions and 200 mV in Cand D versions, typically) at full load.

The output current reference (VREFX) is VREF unlessthermal fold−back is activated by the SD pin voltage beingreduced below 1 V typical (see “protections” section) orunless the DIM pin voltage is below VDIM100 (see analogdimming section).

If a major fault is detected, the circuit enters thelatched−off or auto−recovery mode and the COMP pin isgrounded (except in an UVLO condition). This ensures aclean start−up when the circuit resumes operation.

Start−up SequenceGenerally an LED lamp is expected to emit light in < 1 sec

and typically within 300 ms. The start−up phase consists of

the time to charge the VCC capacitor, initiate startup andbegin switching and the time to charge the output capacitoruntil sufficient current flows into the LED string. Tospeed−up this phase, the following defines the start−upsequence:• The COMP pin is grounded when the circuit is off. The

average COMP voltage needs to exceed the VS pinpeak value to have the LED current properly regulated(whatever the current target is). To speed−up the COMPcapacitance charge and shorten the start−up phase, aninternal 80−�A current source adds to the OTA sourcedcurrent (60 �A max typically) to charge up the COMPcapacitance. The 80−�A current source remains on untilthe OTA starts to sink current as a result of the COMPpin voltage sufficient rise. At that moment, the COMPpin being near its steady−state value, it is only drivenby the OTA.

• If VCC drops below the VCC(off) threshold because thecircuit fails to start−up properly on the first attempt, anew attempt takes place as soon as VCC is recharged toVCC(on). The COMP voltage is not reset at thatmoment. Instead, the new attempt starts with theCOMP level obtained at the end of the previousoperating phase.

• If the load is shorted, the circuit will operate in hiccupmode with VCC oscillating between VCC(off) andVCC(on) until the AUX_SCP protection trips(AUX_SCP is triggered if the ZCD pin voltage doesnot exceed 1 V within a 90−ms operation period of timethus indicating a short to ground of the ZCD pin or anexcessive load preventing the output voltage fromrising). The NCL30186A and NCL3006C latch off inthis case. With the B and D versions, the AUX_SCPprotection forces the 4−s auto−recovery delay to reducethe operation duty−ratio. Figure 60 illustrates a start−upsequence with the output shorted to ground, in thissecond case.


NCL30186

www.onsemi.com21

CC(on)V

CC(off)V

( )4recoveryt s�

( )��

1t

2t3t

( )1 2 3

90OVLD

OVLD

AUX_SCPtrips

as t t t

t ms

+�

1t

2t3t

( )4recoveryt s�

( )��

CCV

DRV

time

time

Figure 60. Start−up Sequence in a Load Short−circuit Situation (auto−recovery versions)

t + =

Zero Crossing Detection BlockThe ZCD pin detects when the drain−source voltage of the

power MOSFET reaches a valley by crossing below the55−mV internal threshold (VZCD(TH)). At startup or in caseof extremely damped free oscillations, the ZCD comparatormay not be able to detect the valleys. To avoid such a

situation, the NCL30186 features a time−out circuit thatgenerates pulses if the voltage on ZCD pin stays below the55−mV threshold for 6.5 �s nominal. The time−out also actsas a substitute clock for the valley detection and simulatesa missing valley in case the free oscillations are too damped.

Figure 61. Zero Current Detection Block

+

−

ZCD

VZCD(TH)

Time−Out

Clock

+

−VZCD(short) +

−S

R

Q

Q

Aux_SCP

90−ms Timer

4−s Timer (auto−recovery version)

FF_mode

t ZCD(blank2)

tZCD(blank1)tZCD(blank)

Vcc<Vcc(reset) (latching−off version)


NCL30186

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If the ZCD pin or the auxiliary winding happen to beshorted, the time−out function would normally make thecontroller keep switching and hence lead to improper LEDcurrent value. The “AUX_SCP” protection prevents such astressful operation: a secondary timer starts counting that isonly reset when the ZCD voltage exceeds the VZCD(short)threshold (1 V typically). If this timer reaches 90 ms (noZCD voltage pulse having exceeded VZCD(short) for this timeperiod), the controller detects a fault and stops operation for4 seconds (B and D versions) or latches off (A and Cversions).

The “clock” shown in Figure 61 is used by the “valleyselection frequency foldback” circuitry of the block diagram(Figure 3), to generate the next DRV pulse (if no faultprevents it):• Immediately when the clock occurs in QR mode at low

line or valley 2 at high line (full load)

• After the appropriate number of “clock” pulses inthermal foldback mode

For an optimal operation, the maximum ZCD levelshould be maintained below 5 V to stay safely below thebuilt in clamping voltage of the pin.

Line Range DetectionAs sketched in Figure 62, this circuit detects the low−line

range if the VS pin remains below the VLL threshold (2.3 Vtypical) for more than the 25−ms blanking time. High−lineis detected as soon as the VS pin voltage exceeds VHL (2.4 Vtypical). These levels roughly correspond to 184−V rms and192−V rms line voltages if the external resistors dividerapplied to the VS pin is designed to provide a 1−V peak valueat 80 V rms.

Figure 62. Line Range Detection

In the low−line range, conduction losses are generallydominant. Adding a dead−time would further increase theselosses. Hence, only a short dead−time is necessary to reachthe MOSFET valley. In high−line conditions, switchinglosses generally are the most critical. It is thus efficient toskip one valley to lower the switching frequency. Hence,under normal operation, the NCL30186 optimizes the

efficiency over the line range by turning on the MOSFET atthe first valley in low−line conditions and at the secondvalley in the high−line case. This is illustrated by Figure 63that sketches the MOSFET Drain−Source voltage in bothcases. In the event that thermal foldback is activated,additional valleys can be skipped as the power is reduced.

Figure 63. Full−load Operation − Quasi−resonant Mode in low line (left), turn on at valley 2 when in high line(right)

Line FeedforwardTo compensate for current regulation errors due to AC line

variation, the NCL30186 includes a method to add linefeedforward adjustment. As illustrated by Figure 64, theinput voltage is sensed by the VS pin and converted into a

current. By adding an external resistor in series between thesense resistor and the CS pin, a voltage offset proportionalto the input voltage is added to the CS signal for theMOSFET on−time.


NCL30186

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Bulk rail

VS

CS

vDD

Rsense

RCSICS(offset)

Q_drv

Figure 64. Line Feed−Forward Schematic

In Figure 64, Q_drv designates the output of the PWM latch which is high for the on−time and low otherwise.

PWM or Linear Dimming DetectionThe DIM pin of the NCL30186 is provided to implement

linear and/or PWM dimming of the LED current.Applying a voltage on the DIM pin voltage (VDIM) forces

the output current internal reference to operate in one ofthree regions:

VREFX � 0 (eq. 2)if VDIM � VDIM0

VREFX � VREF if VDIM � VDIM100

VREFX �VDIM VDIM0

VDIM100 VDIM0VREF otherwise

VDIM0 and VDIM100 respectively, are 0.7 V and 2.45 Vtypically.

The output current can then be controlled by the DIM pinas follows:

Iout � 0 (eq. 3)if VDIM � VDIM0

Iout � Iout,nom �VREF

2 NPSRsenseif VDIM � VDIM100

Iout �VDIM VDIM0

VDIM100 VDIM0Iout,nom otherwise

Where:• NPS is the secondary to primary transformer turns

NPS � NSNP

• Rsense is the current sense resistor (see Figure 1).

• VREF is the output current internal reference (250 mVtypically)

• Iout,nom is the full−load output current.The DRV output is disabled whenever the DIM pin

voltage is lower than VDIM0 and the output current setpointis maximal when VDIM exceeds VDIM100. Thus, for PWMdimming, a PWM signal with a low−state value belowVDIM0 and a high−state value above VDIM100 should beapplied.

In this case, the output current will be:

Iout � Iout,nom � d (eq. 4)

Where d is the duty ratio of the DIM pin signal.

VDIM0

VDIM

VDIM100

Iout,nom

Iout

0 A

time

time

Figure 65. Pin DIM Chronograms


NCL30186

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Notes:• The current does not immediately reach its new target

value when the PWM dimming signal state changes dueto system time constants like the time necessary tocharge or discharge the output capacitor to the requiredlevel. The output current settling time can hence affectthe obtained output current, particularly if the PWMsignal frequency is high.

• If either the high−state (VDIM(high)) or low−state level(VDIM(low)) of the input or both are between VDIM0 andVDIM100, the output current will be proportionallyreduced as both analog and PWM dimming aresimultaneous active, thus the output current will be:

Iout � �VDIM(high) VDIM0

VDIM100 VDIM0d �

VDIM(low) VDIM0

VDIM100 VDIM0(1 d) Iout,nom if VDIM0 � VDIM(low) � VDIM(high) � VDIM100

Iout �VDIM(high) VDIM0

VDIM100 VDIM0d � Iout,nom if VDIM0 � VDIM(high) � VDIM100 and VDIM(low) � VDIM0

Iout � �d �VDIM(low) VDIM0

VDIM100 VDIM0(1 d) Iout,nom if VDIM(high) � VDIM100 and VDIM0 � VDIM(low) � VDIM100

• If thermal foldback is activated as well, the currentreduction is cumulative. For instance, if the DIM pinvoltage and the thermal foldback respectively, reducesthe output current setpoint by 50% and 20%respectively, the output current will be 80%*50% that is40% of its nominal level.

The DIM pin is pulled up internally by a 10−�A current source.Thus, if the pin is let open, the controller is able to start.

For any power factor corrected single stage architecturethere will be a component of line ripple (100 / 120 Hz) on theoutput. If PWM dimming is used, it is recommended toselect the dimming frequency to be sufficiently high not togenerating beat frequencies that could create opticalartifacts.

>> As a general rule, the minimum PWM frequencyshould be at least 2.5x the line ripple frequency and notbe set near multiples of the line frequency.

ProtectionsThe circuit incorporates a full suite of protection features

listed below to make the LED driver very rugged.

Output Short Circuit SituationAn overload fault is detected if the ZCD pin voltage

remains below VZCD(short) for 90 ms. In such a situation, thecircuit stops generating pulses until the 4−s delayauto−recovery time has elapsed (B and D versions) orlatches off (A and C versions).

Winding or Output Diode Short Circuit ProtectionIf a transformer winding happens to be shorted, the

primary inductance will collapse leading the current to rampup in a very abrupt manner. The VILIM comparator (currentlimitation threshold) will trip to open the MOSFET andeventually stop the current rise. However, because of theabnormally steep slope of the current, internal propagationdelays and the MOSFET turn−off time, a current rise > 50%of the nominal maximum value set by VILIM is possible. Asillustrated in Figure 66, an additional circuit monitors forthis current overshoot to detect a winding short circuit. Theleading edge blanking (LEB) time for short circuitprotection (LEB2) is significantly faster than the LEB timefor cycle−by−cycle protection (LEB1). Practically, if fourconsecutive switching periods lead the CS pin voltage toexceed (VCS(stop) = 150% * VILIM), the controller enters theauto−recovery mode (4−s operation interruption betweenactive bursts with versions B and D) or latches off (versionsA and C).


NCL30186

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Figure 66. Winding Short Circuit Protection, Max. Peak Current Limit Circuits

S

R

Q

Q

CS

LEB1 +

−

S

R

Q

Q

VCC

aux

Vccmanagement

Vdd

VCCreset(grandreset)

DRV

Ipkmax

PWMreset

VILIMIT

+

−

LEB2

VCS(stop)

WOD_SCP

+

−

STOP

SD Pin OVP(OVP2)

UVLO

S

R

Q

Q

OTP

4−s timer

OFF

latch

latch

4−s timer

VCCreset

4−pulsecounter

AUX_SCP

VCC(ovp)

UVLOBONOK

TSD

Vcontrol / 4

AUTORECOVERY(B and D versions)

LATCHING−OFF(A and C versions)

VCC Over Voltage ProtectionThe circuit stops generating pulses if VCC exceeds

VCC(OVP) and enters auto−recovery mode. This featureprotects the circuit in the event that the output LED string isdisconnected or an individual LED in the string happens tofail open.

Programmable Over Voltage Protection (OVP2)In addition to the VCC OVP protection, it is possible to

connect a Zener diode between VCC and the SD pin toimplement programmable VCC OVP monitoring (DZ ofFigure 67). The triggering level is (VZ+VOVP) where VOVP isthe 2.5−V internal threshold. If this protection trips, theNCL30186A and NCL30186C latch off while theNCL30186B and NCL30186D enter the auto−recovery mode.

S

R

Q

Q

grand reset

SD

VCC

IOTP(REF)

+

−

Vdd

+

−

Cla

mp

Rclamp

Vclamp

Latch

OTP(off)V / V

OVPV

NTC

TFV

S

R

Q

Q

4−s Timer

OFF

ThermalFoldback

OTP(start)T

SD(delay)T

OTP(on)

SD PIN OVP (OVP2) DETECTION

OTP DETECTION

ZD

NCL30186B / NCL30186D(autorecovery versions)

NCL30186A / NCL30186C(latching off versions)

Figure 67. Thermal Foldback and OVP/OTP Circuitry


NCL30186

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The SD pin is clamped to about 1.35 V (Vclamp) througha 1.6−k� resistor (Rclamp). It is then necessary to inject about

�VOVP Vclamp

Rclamp

that is

�2.50 1.351.6 k

� 700 �A typically, to trigger the OVP protection. This current helpsensure an accurate detection by using the Zener diode farfrom its knee region.

Programmable Over Temperature Foldback Protection(OTP)

Connect an NTC between the SD pin and ground to detectan over−temperature condition. In response to a hightemperature (detected if VSD drops below VTF(start)), thecircuit gradually reduces the LED current down to 50% (>50% reduction in output power) of its initial value when VSDreaches VTF(stop), in accordance with the characteristic ofFigure 68 (Note 9).

At this point, if the temperature continues to rise and thesecondary OTP level is reached, (VSD drop below VOTP), thecircuit latches off (A and C versions) or enters auto−recoverymode (B and D versions) and cannot resume operation untilVSD exceeds VOTP(on) to provide some temperature hysteresis(around 10°C typically). The OTP thresholds nearlycorrespond to the following resistances of the NTC:• Thermal foldback starts when RNTC ≤ RTF(start)

(11.7 k�, typically)• Thermal foldback stops when RNTC ≤ RTF(stop) (8.0 k�,

typically)• OTP triggers when RNTC ≤ ROTP(off) (5.9 k�, typically)

• OTP is removed when RNTC ≤ ROTP(on) (8.0 k�,typically) (Note 10)

Figure 68. Output Current Reduction versus SDPin Voltage

At startup, when VCC reaches VCC(on), the OTPcomparator is blanked for at least 180 �s which allows theSD pin voltage to reach its nominal value if a filteringcapacitor is connected to the SD pin. This avoids flickeringof the LED light during turn on.

Brown−Out ProtectionThe NCL30186 prevents operation when the line voltage

is too low for proper operation. As sketched in Figure 69, thecircuit detects a brown−out situation if the VS pin remainsbelow the VBO(off) threshold (0.9 V typical) for more thanthe 25−ms blanking time. In this case, the controller stopsoperating. Operation resumes as soon as the VS pin voltageexceeds VBO(on) (1.0 V typical) and VCC is higher thanVCC(on). To ease recovery, the circuit overrides the VCCnormal sequence (no need for VCC cycling down belowVCC(off)). Instead, its consumption immediately reduces toICC(start) so that VCC rapidly charges up to VCC(on) and thecircuit re−starts operation.

Figure 69. Brown−out Circuit

9. The above mentioned initial value is the output current before the system enters the thermal foldback, that is, its maximum level if PWM oranalog dimming is not engaged or a lower one based on the dimming value.

10.This condition is sufficient for operation recovery of the B and D versions. For the A and C versions which latches off when OTP is triggered,the circuit further needs to be reset by the VCC drop below VCC(reset).


NCL30186

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Die Over Temperature (TSD)The circuit stops operating if the junction temperature (TJ)

exceeds 150°C typically. The controller remains off until TJgoes below nearly 100°C.

Pin Connection Faults

The circuit addresses most pin connection fault cases:• CS Pin Short to Ground

The circuit senses the CS pin impedance every time itstarts−up and after DRV pulses terminated by the 36−�smaximum on−time. If the measured impedance doesnot exceed 120 � typically, the circuit stops operating.In practice, it is recommended to place a minimum of250 � in series between the CS pin and the currentsense resistor to take into account parasitics.

• Fault of the GND ConnectionIf the GND pin is properly connected, the supplycurrent drawn from the positive terminal of the VCCcapacitor, flows out of the GND pin to return to thenegative terminal of the VCC capacitor. If the GND pinis not connected, the circuit ESD diodes offer anotherreturn path. The accidental non−connection of the GNDpin is monitored by detecting that one of the ESD diodeis conducting. Practically, the ESD diode of CS pin ismonitored. If such a fault is detected for 200 �s, thecircuit stops generating DRV pulses.

More generally, incorrect pin connection situations(open, grounded, shorted to adjacent pin) are covered byAND9204/D.

Fault Management

OFF Mode

The circuit turns off in the case of an incorrect feeding of thecircuit: “UVLO high”. The UVLO signal becomes highwhen VCC drops below VCC(off) and remains high untilVCC exceeds VCC(on).

The circuit also turns off whenever a major faultycondition prevents it from operating:• Severe OTP (VSD level below VOTP(off))

• VCC OVP

• OVP2 (additional OVP provided by SD pin)

• Output diode short circuit protection: “WOD_SCPhigh”

• Output / Auxiliary winding Short circuit protection:“Aux_SCP high”

• Die over temperature (TSD)

In this mode, the DRV pulses generation is interrupted.In the case of a latching−off fault, the circuit stops pulsing

until the LED driver is unplugged and VCC drops belowVCC(reset). At that moment, the circuit resumes operation.

In the auto−recovery case, the circuit cannot generateDRV pulses for the auto−recovery 4−s delay. When this timehas elapsed, the circuit recovers operation as soon as theVCC voltage has exceeded VCC(on). In the B and D versions,all these protections are auto−recovery. The SD pin OTP andOVP, WOD_SCP and AUX_SCP functions are latching offin the A and C versions (see Table 5).

Table 5. PROTECTION MODES

AUX_SCP WOD_SCP SD Pin OTP SD Pin OVP

NCL30186A* Latching off Latching off Latching off Latching off

NCL30186B Auto−recovery Auto−recovery Auto−recovery Auto−recovery

NCL30186C* Latching off Latching off Latching off Latching off

NCL30186D Auto−recovery Auto−recovery Auto−recovery Auto−recovery

ORDERING INFORMATION

Device Package Type Shipping

NCL30186ADR2G*

SOIC−10(Pb−Free/Halide Free) 2500 / Tape & Reel

NCL30186BDR2G

NCL30186CDR2G*

NCL30186DDR2G

*Please contact local sales representative for availability


SOIC−10 NBCASE 751BQ

ISSUE BDATE 26 NOV 2013

SEATINGPLANE

15

610

hX 45�

NOTES:1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.2. CONTROLLING DIMENSION: MILLIMETERS.3. DIMENSION b DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE PROTRUSIONSHALL BE 0.10mm TOTAL IN EXCESS OF ’b’AT MAXIMUM MATERIAL CONDITION.

4. DIMENSIONS D AND E DO NOT INCLUDEMOLD FLASH, PROTRUSIONS, OR GATEBURRS. MOLD FLASH, PROTRUSIONS, ORGATE BURRS SHALL NOT EXCEED 0.15mmPER SIDE. DIMENSIONS D AND E ARE DE-TERMINED AT DATUM F.

5. DIMENSIONS A AND B ARE TO BE DETERM-INED AT DATUM F.

6. A1 IS DEFINED AS THE VERTICAL DISTANCEFROM THE SEATING PLANE TO THE LOWESTPOINT ON THE PACKAGE BODY.

D

EH

A1A

SCALE 1:1

DIM

D

MIN MAX

4.80 5.00

MILLIMETERS

E 3.80 4.00

A 1.25 1.75

b 0.31 0.51

e 1.00 BSC

A1 0.10 0.25A3 0.17 0.25

L 0.40 0.80

M 0 8

H 5.80 6.20

CM0.25

M

� �

XXXXX = Specific Device CodeA = Assembly LocationL = Wafer LotY = YearW = Work Week� = Pb−Free Package

GENERICMARKING DIAGRAM*

1

10

*This information is generic. Please referto device data sheet for actual partmarking. Pb−Free indicator, “G”, mayor not be present.

DIMENSION: MILLIMETERS

*For additional information on our Pb−Free strategy and solderingdetails, please download the ON Semiconductor Soldering andMounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

XXXXXALYWX

�1

10

h 0.37 REF

L2 0.25 BSC

A

TOP VIEW

C0.202X 5 TIPS A-B D

C0.10 A-B

2X

C0.10 A-B

2X

e

C0.10

b10XB

C

C0.10

10X

SIDE VIEW END VIEW

DETAIL A

6.50

10X 1.18

10X 0.58 1.00PITCH

RECOMMENDED

1

L

F

SEATINGPLANEC

L2 A3

DETAIL A

D

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regardingthe suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specificallydisclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor therights of others.

98AON52341EDOCUMENT NUMBER:

DESCRIPTION:

Electronic versions are uncontrolled except when accessed directly from the Document Repository.Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

PAGE 1 OF 1SOIC−10 NB

© Semiconductor Components Industries, LLC, 2019 www.onsemi.com

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