NANOLAB: A Tool for Evaluating Reliability of Defect-Tolerant NanoArchitectures

Debayan Bhaduri Sandeep ShuklaFermat Lab

Bradley Department of Electrical and Computer EngineeringVirginia Tech, Blacksburg, VA-24061 U.S.A

{dbhaduri, shukla}@vt.edu

Abstract

As silicon manufacturing technology reaches the nanoscale,architectural designs need to accommodate the uncertaintyinherent at such scales. These uncertainties are germane inthe miniscule dimension of the devices, quantum physicaleffects, reduced noise margins, system energy levels reach-ing computing thermal limits, manufacturing defects, agingand many other factors. Defect tolerant architectures andtheir reliability measures will gain importance for logic andmicro-architecture designs based on nano-scale substrates.Recently, Markov Random Field (MRF) has been proposedas a model of computation for nanoscale logic gates. Inthis paper, we take this approach further by automating thiscomputational scheme and a Belief Propagation algorithm.We have developed MATLAB based libraries and toolset forfundamental logic gates that can compute output probabil-ity distributions and entropies for specified input distribu-tions. Our tool eases evaluation of reliability measures ofcombinational logic blocks. The effectiveness of this au-tomation is illustrated in this paper by automatically de-riving various reliability results for defect-tolerant archi-tectures, such as Triple Modular Redundancy (TMR), Cas-caded Triple Modular Redundancy (CTMR) and multi-stageiterations of these. These results are used to analyze trade-offs between reliability and redundancy for these architec-tural configurations.1

1. Introduction

As electronic devices get smaller, the probability of errorsdue to manufacturing defects, aging, and transient faults in-creases. This necessitates the use of defect-tolerant and re-liable architectures. The analysis of such architectures isbecoming a central priority [13, 14, 20, 5, 19, 12] in view

1This work was supported by NSF Grant CCR-0340740

of reliability issues related to nanoscale devices. Fault tol-erance in the presence of defective devices, noisy intercon-nects, thermal perturbations, and random errors has to bebuilt into architectures in the form of redundancy of devicesand functional units. The resulting increase in device den-sity is acceptable at the nano level because of the abundanceof devices of such small feature size. But as shown in [20],addition of more unreliable devices could decrease the reli-ability of an architecture. This means that for a given fail-ure distribution of devices, there is a redundancy/reliabiltytrade-off for each specific architecture and any change in re-dundancy may lead to less reliable computation. A proba-bility based design methodology based on Markov RandomFields (MRF) [18] has been proposed in [2] which exploitsthe fact that maximizing the probability of Boolean stateconfigurations is equivalent to minimizing the entropy ofa suitable energy distribution that depends on neighboringnodes. The probability of a logic variable can be calcu-lated by marginalizing over the set of possible states of theneighboring logic variables. The probability of the set ofpossible states for such a logic variable can be propagatedto the next node in a Boolean network by using an algorithmcalled Belief Propagation [15]. In this paper we describe aMATLAB based tool (code named NANOLAB since it isbased on MATLAB) that allows automatic computation ofthe set of possible states of different logic variables. Thesestates are then propagated through the logic circuit from theinputs to the outputs. The logic compatibility function [2]of the different components of the Boolean network and theprobability distribution of the states at the primary inputsare the inputs to the tool. Entropy at different points of theBoolean network are also calculated for analysis of differ-ent fault tolerant architectures. The novelty of this work canbe summarized as follows:

• Our tool and libraries allows fast reliability/redun-dancy trade-offs for alternative defect tolerant archi-tectures. For example in Figure 4, the curves gener-

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ated by our tool clearly show that for a NAND gate,iterating CTMR more than once results in lesser reli-ability by quickly reaching high entropy, whereas inFigure 5, one can see that 2nd order CTMR configu-ration gives better reliability. These could help systemdesigners to quickly evaluate the redundancy schemefor defect tolerance while building the designs targetedfor nanoscale substrates.

• The idea of a new model of computation in [2] foruncertainty based computation is extended in the di-rection of reliability evaluation. We believe this it-self is a novel contribution since in [2] they only showtheir MRF based computation scheme as viable, anddo not extend it in the direction of reliability/redun-dancy trade-off analysis.

• We have used this probabilistic model of computationas a vehicle to measure reliability and compared theresults against the standard Boolean logic based modelof computation (with probabilities attached for makingwrong Boolean output) and found that the reliabilityresults are similar. Our results on the standard modelof computation with probabilistic Boolean transitionare in [5, 20].

• From our literature search, we found that the resultson reliability measures for different defect tolerant ar-chitectures were all analytical [22, 13, 19, 12], exceptfor our work with a different model of computation[20, 5]. However, for complex network of gates, suchanalytical results may be error prone, For example in[20] we discovered an error in one of the bounds ana-lytically computed in [13]. As a result, we believe thata scalable automation to quickly evaluate these figuresof merits is crucial for practical use by engineers.

1.1. Reliability, Entropy, and Model of Computa-tion

[2] not only provides a different non-discrete model of com-putation, in fact, it relates information theoretic entropy andthermal entropy of computation in a way so as to connectreliability to entropy. It has been shown that the thermo-dynamic limit of computation is KbT ln 2 [3] where KbTis the thermal energy and is expressed in normalized unitsrelative to the logic state energy (Kb is the Boltzmann con-stant and T is the temperature in Kelvin). What this meansis that the minimum entropy loss due to irreversible compu-tation amounts to thermal energy that is proportional to thisvalue. If we consider energy levels close to these thermallimits, the reliability of computation is likely to be affected,and if we can keep our systems far from the temperaturevalues that might bring the systems close to this amount of

entropy loss, the reliability is likely to improve. This ideais also taken into account by [2] and a Gibbs distributionbased technique is used to characterize the computations byBoolean gates and networks. NANOLAB automates thisnon-discrete model of computation. This automation en-tails parameterized library functions to compute the outputdistributions given the input distributions for all the genericlogic gates. These can be used to calculate the probabilityof the state configurations and entropy values at the primaryoutputs of any arbitrary Boolean network.

B-bits

B-bits

B-bits

B- Bit

Majority

Gate

Unit 1

Unit 2

Unit 3

Figure 1. Generic Triple Modular RedundancyConfiguration

The usefulness of such a library and methodology is il-lustrated by modeling and computing various reliability fig-ures of merit for interesting defect-tolerant architectures.One of the architectures shown as an illustration is a Triplemodular redundancy (TMR) [19] configuration where threeNAND gates work in parallel, and their outputs are com-pared with a majority gate. The TMR configuration isshown in Figure 1 and the units in the figure are NANDgates.

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

z (output of TMR) →

p(z)

→

The probability of a NAND TMR configuration for different values of B and T

BT = 0.1

BT = 0.25

BT = 0.5

BT = 1

Figure 2. The probability of the TMR outputfor different values of kbT

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The probability of the state configurations of the outputof the TMR configuration are plotted in Figure 2 for differ-ent values of KbT. The results obtained by our methodologyare consistent with our analysis. The probability p(z) of theTMR output z for the different state configurations of z areoutlined in Figure 2. As it can be observed, the probabil-ity at z = 0 for different values of KbT is very high and de-creases as z approaches 1 in all the cases. This is because thethree NAND gates in the TMR configuration shown in Fig-ure 2 have input probability distributions where p(inputs=0)= 0.1 and p(inputs=1) = 0.9. Therefore, the output of themajority logic gate z in Figure 1 has a high probability of be-ing at 0. Also, it is observed that as the KbT values increase,the likelihood of the occurrence of intermediate values forthe state configurations of the output goes up to the extentthat the probability of occurrence of these values is almostthe same as z being logic low or high (valid state configu-rations). TMR blocks cascaded together to form differentorders of Cascaded triple modular redundancy configura-tion (CTMR) [19] yield interesting findings. This indicatesthe fact that our methodology can be used conveniently toevaluate different architectures for nanoscale devices.

2. Related Work

Nanotechnology currently involves various technologiesthat exploit the quantum-mechanical effects of small de-vices. Some of these emerging technologies are single elec-tron transistors [9], nanowire transistors [11], quantum dots[23], quantum cellular automata [17], resonant tunnelingdevices [6], negative differential resistors (NDR) [7] andreconfigurable switches [8, 10]. In all the cases the fabri-cated devices are of the order of a few nanometers. Suchminiaturization leads to high density of devices on systemon chips (SOCs) but there is a price to be paid for usage ofsmaller devices. There is going to be a very high degree offailures due to (i)manufacturing defects, (ii) transient faultsresulting from reduced noise tolerance at reduced voltageand current levels, and (iii) faults due to aging [20]. De-fect tolerant architectures are possible solutions to this prob-lem specifically by using redundant devices and functionalunits. It has been observed that there are optimal redun-dancy factors for each specific architecture under investiga-tion. Theoretical models have been used in the past [14, 13]to obtain optimal redundancy levels so as to analyze thereliability-redundancy tradeoff. Interesting work in [20] ona defect tolerant architecture called NAND multiplexing de-veloped by Von Neumann in 1952 [24], takes this analysisfurther by applying a CAD framework namely a probabilis-tic symbolic model checker called PRISM [21, 16]. Thework in [20] found some errors in analytically computedbounds and shows the power, flexibility and need of a ro-bust CAD framework for conveniently and quickly analyz-

ing different defect tolerant architectures.

2.1. Detailed Methodology From [2]

The basis for the architectural approach in [2] is the Markovrandom network which is based on Markov random fields(MRF) [18]. The Markov random field is defined as a finiteset of random variables, Λ = {λ1,λ2,......, λk}. Each vari-able λi has a neighborhood, Ni, which are variables from{Λ - λi}. The probability distribution of a given variabledepends only on a (typically small) neighborhood of othervariables that is called a clique. These variables may rep-resent states of nodes in a Boolean network and we mightbe able to consider effects of noise and other uncertaintyfactors on a node by considering the conditional probabili-ties of energy values with respect to its clique. Due to theHammersley-Clifford theorem [4],

P(λi|{Λ − λi}) =1Z

e−1kbT

∑c∈C Uc(λ) (1)

The conditional probability in equation 1 is called theGibbs distribution. Z is the normalizing constant. For agiven node i, C is the set of cliques. Uc is the clique en-ergy function and depends only on the neighborhood of thenode whose state probability is being calculated. The logicmargins of nodes in a Boolean network decrease at highervalues of KbT and become significant at lower values. Thisformulation also allows correct analysis of entropy values.Let us take a specific example to walk through the method-ology in [2]. For a two input NAND gate, there are threenodes in the assumed logic network: the inputs x0 and x1,and the output x2. The operation of the gate is designated bythe logic compatibility function �(x0,x1,x2). � = 1 whenx2 = (x0 ∧ x1)′ (valid logic operations). The axioms ofBoolean ring are used to relate the logic compatibility func-tion to a Gibb’s energy form. Also, the valid input/outputstates should have lower clique energies than invalid states.Thus the clique energy is the summation over the mintermsof the valid states and is calculated as :

U(x0,x1,x2) = −∑

i

�(x0,x1,x2) (2)

where �i = 1, and the minterms are transformed usingBoolean ring rules. The clique energy for the NAND gate is:

U(x0,x1,x2) = -1 - x2 + 2x0x1x2 - x0x1

The probability of the different state configurations of x2 is:

p(x2) =1Z

∑

x0∈{0,1}p(x0)

∑

x1∈{0,1}p(x1) e−

1kbTU(x0,x1,x2)

(3)

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As according to equation 3, the probability of x2 is cal-culated as a function of x2 after marginalizing over the dis-tributions of x0 and x1. The probability of the state con-figurations of the outputs of any logic gate can be calcu-lated by the methodology above. Given the input proba-bility distributions and logic compatibility functions, usingBelief Propagation algorithm it is also possible to calcu-late entropy and probability of the state configurations atdifferent nodes of the network. Thus, [2] gives a proba-bilistic model of computation which we exploit to computereliability-redundancy tradeoffs for different nanoscale ar-chitectures.

3. NANOLAB : A MATLAB Based Tool

In this section, we briefly describe our automationmethodology and a detailed example.

3.1. Our Methodology

Our tool consists of a library of functions implementedin MATLAB [1]. The library currently consists of threefunctions based on the probabilistic non discrete model ofcomputation discussed in the Related Work section. Thesework for any generic one, two and three input logic gatesand can be extended to handle n-input logic gates. The in-puts of these gates are assumed to be independent of eachother. The functions are parameterized and take in as inputsthe logic compatibility function and the initial probabilitydistribution of the inputs of a gate. The probability of theoutput of a gate (as shown in equation 3) being in differentstate configurations ∈ { 0, 0.1, 0.2, 0.3, ., 1.0} is calculatedby marginalizing over the set of possible values of the nodesthat belong to the same clique. In the case of generic gatesthese nodes are their inputs. These probabilities are returnedas vectors by these functions and indicate the probability ofthe output node being at different energy levels between 0and 1. These probabilities are also calculated over differentvalues of KbT so as to analyze thermal effects on the node.The Belief Propagation algorithm [15] is used to propagatethese probability values to the next node of the networkto perform the next marginalization process. The tool cancalculate entropy values at different nodes of the logic net-work and can model random noise so as to access signal andstructural errors. It also verifies that for each logical com-ponent of a Boolean network, the valid states have an en-ergy level less than the invalid states as shown theoreticallyin [2]. Arbitrary Boolean networks in any defect-tolerantconfiguration can be analyzed by writing simple MATLABscripts that use the NANOLAB library functions. Mostwork in evaluation of reliability-redundancy tradeoffs fordifferent defect-tolerant architectures is done analytically.A few implementation methodologies have been proposed

such as a probabilistic methodology in [20] and a reconfig-uration based methodology for stuck at fault models [22].Our methodology automates the recently proposed proba-bilistic model of computation in [2], that is ideal to modelnanoscale computation. NANOLAB expedites the evalu-ation process of different architectural alternatives for ap-plication specific Boolean networks and eases the work ofhardware/system designers. Also, generic architecture con-figurations like TMR are being converted into library func-tions such that these can be utilized in larger Boolean net-works where more than one kind of defect-tolerant schememay be used for higher reliability of computation.

1 bit

1 bit

1 bit

1 bit

MG

MG

MG

MG

x2

x2

y2

y2

x2y2

x1

x1

y1

x1

y1

y1

x3

x3

y3

x3

y3

y3

MG = Majority Gate

Figure 3. Cascaded Triple Modular Redun-dancy

3.2 Detailed Example

We now discuss a detailed example to indicate the powerof our methodology.

Figure 3 shows a CTMR configuration with three TMRblocks working in parallel with a majority gate logic. TheNANOLAB functions and Belief Propagation algorithm areused in a MATLAB script to evaluate the probability of thestate configurations of the output of the CTMR. The prob-ability distributions for x1, y1, x2, y2, x3 and y3 for theNAND gates as shown in Figure 3 are specified as vectors.These vectors specify the probabilities of the inputs being a0 or a 1. The input probability distributions for all the TMRblocks are the same in this case but these can be varied byhaving separate input vectors for each TMR block.

The NANOLAB functions return vectors similar to theone shown in table 1. These indicate the probability of the

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0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 11.5

2

2.5

3

3.5

4

Different values of kbT (Thernmal energy levels) →

En

tro

py

→

The entropy at different values of KbT for a NAND gate

uniformprob(1) = 0.8

(a) The entropy of a NAND gate for differentinput distributions

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 11

1.5

2

2.5

3

3.5

4

Different values of kbT (Thermal energy levels)

Entr

opy

0th order CTMR1st order CTMR2nd order CTMR

(b) Entropy of a CTMR NAND configurationwhen inputs are uniformly distributed

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 11

1.5

2

2.5

3

3.5

4

Different values of kbT (Thermal energy levels)

Entr

opy

0th order CTMR1st order CTMR2nd order CTMR

(c) Entropy of a CTMR NAND configurationwhen inputs are logic high with 0.8 probability

Figure 4. Entropies for the output of a single NAND gate and CTMR configuration of a NAND gate atdifferent KbT values.

z=0.0 z=0.2 z=0.5 z=0.8 z=1.0

0.809 0.109 0.006 0.025 0.190

0.798 0.365 0.132 0.116 0.201

0.736 0.512 0.324 0.256 0.263

0.643 0.547 0.443 0.379 0.356

Table 1. Probability of the output z of a logicgate being at different energy levels for valuesof KbT ∈ {0.1.0.25.0.5.1.0}

output of a logic network being at specified energy levels atdifferent KbT values. In the CTMR configuration, for eachTMR block, the state configurations of the outputs for eachof the three NAND gates are obtained from the function fora two input gate. Then these probabilities are used as in-put probability distributions to the function for a three inputgate. This computes the state configuration probabilities ofthe output of the majority logic gate. Similarly, the prob-abilities of the final output of the CTMR is calculated. Itcan be seen that our methodology provides a very conve-nient way of evaluating this CTMR configuration and onlyrequires minor modifications to be extended to any i-th or-der CTMR.

Additionally, it is desired that valid input/output statesshould have lower clique energies than invalid states [2].This is the reason that the clique energy is the negated sum-

mation over the valid states in equation 2. We have checkedfor the conformance to this property for the different cliqueenergy functions which are generated by NANOLAB.

4. Experiments and Results

Reliability and Entropy Measures of a NAND Gate:

Figure 4 shows the entropy curves at the outputs for a sin-gle NAND gate and a CTMR configuration at different KbTvalues. The output probability distribution of a NAND gateis asymmetrical. This should be expected since only oneinput combination produces a logic 0 at the output. Figure4(a) indicates that the entropy is lower when the inputs ofthe single NAND gate are uniformly distributed. At higherKbT values, in both the uniform and non-uniform probabil-ity distribution cases, the entropy increases resulting in thelogic margins (probability of being in valid sate configura-tions) being reduced. This indicates that the logic marginsin both scenarios of distribution almost approach zero asKbT values increase. When thermal energy becomes equalto logic energy (KbT = 1), the entropy values in the caseof the uniform distribution is lower implying that the logicmargins are better than when the inputs have a higher prob-ability of being logic high.

Figure 4(b) shows the entropy curves for different ordersof a NAND CTMR configuration at different KbT values.The inputs in this case are uniformly distributed. It can beobserved that the 0th order CTMR (TMR) has higher en-tropy value i.e. less logic margin than the 1st order CTMR

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at lower KbT values and in both cases the entropy valuesalmost converge at KbT = 0.5. At this point logic marginsat the output of the CTMR become insignificant and thereis total disorder. Computation becomes unpredictable. Theinteresting plot is for the 2nd order CTMR. The entropyshoots up at a KbT value of 0.25 indicating that the optimalredundancy level for a NAND CTMR configuration is the1st order. This aptly shows that every architecture has anoptimal redundancy level and even if redundancy levels areincreased beyond this point, the reliability for the architec-ture either remains the same or worsens.

Figure 4(c) indicates the entropy values when the inputsare non-uniformly distributed with a probability of 0.8to be logic high. In this case too, it is observed that the1st order CTMR is the optimal redundancy level for theconfiguration. The entropy values values are higher thanFigure 4(b) for all values of KbT. This is because the inputdistribution being at a higher probability of being a logichigh implies that the output of the NAND gate will be a 0and only one input combination can cause this to happeni.e. when both inputs are high. Thus, the logic margins area bit reduced and the entropy has higher values than theprevious experiment.

x0

x1

x2

x5

x3x4

z

Figure 5. A Boolean network having the logicfunction z = x2 ∧ (x0 ∨ x1′)

Reliability and Entropy Measures of a CTMR Configu-ration for the Logic Block:

Figure 6 shows the entropy curves at the outputs of theCTMR configurations for the logic block shown in Figure 5.These values are indicated at different KbT values. Fig-ure 6(a) shows the entropy when the input distribution isuniform. It can be observed that the 0th order CTMR hashigher entropy value (less logic margin) than the 1st or 2ndorder CTMR at lower KbT values and in all the cases the en-tropy converges at KbT = 0.5. This indicates that at higherthermal energy, increase in redundancy level does not im-prove the logic margins at the output of the CTMR. Thereliability measures remain the same. The configurationof the logic block has not reached the optimal redundancypoint. This is because the 2nd order CTMR has entropy val-ues less than the 1st order at lower thermal energy levels.

Whereas, in the NAND CTMR configuration, the 2nd orderCTMR had higher entropy at lower KbT values indicatingdegradation in reliability of computation. This experimentillustrates that each specific Boolean network has an uniquereliability-redundancy tradeoff point. It can also be inferredthat the redundancy level is proportional to the device den-sity of a logic network.

Figure 6(b) indicates the entropy values when the inputshave a non-uniform probability distribution i..e the proba-bility of being logic high is 0.8. The same facts are observedin this case as in figure 6(a). But, the entropy is higher thanthe previous experiment for all KbT values. This is becausethe inputs being at a higher probability of being logic highmeans that the output of the logic block will be a 1 and onlya few input combinations can cause this to happen. Thus,the logic margins are slightly reduced as compared to thescenario of uniform distribution.

We conduct this experiment to explore the flexibility androbustness of our tool in evaluating any arbitrary Booleannetwork (in this case a logic block).

5. Conclusion and Future work

In this paper, we propose a methodology which relieson computation of probability of states at different primaryoutputs of a Boolean network. We also describe a toolwe developed which allows automatic computation of thesestate probabilities. Our tool is built on top of MATLAB,and employs a set of libraries we developed together witha Belief Propagation algorithm. So, our tool NANOLABconsists of a library of generic functions that can calculatestate probabilities of one, two and three input generic logicgates. The logic compatibility function and the probabilitydistributions of the inputs of a gate are supplied as input pa-rameters to these functions. We have shown that differentdefect tolerant architectures can be evaluated effectively fornetworks of gates. We find it useful compared to analyt-ically computing these, since analytical computation maybe error prone and cumbersome for large networks. Weshow that optimal redundancy levels for specific architec-tures can be determined based on the required level of re-liability. Our ongoing work in [5] using PRISM [21] andNANOLAB have given very encouraging preliminary re-sults. Future work includes extending the tool to supportevaluation of different logic structures under random noise,and to support evaluation of sequential circuits. We are alsoin the process of building generic libraries for frequentlyused fault tolerance schemes.

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0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 11.5

2

2.5

3

3.5

4

Different values of kbT (Thernmal energy levels) →

Ent

ropy

→

The entropy at different values of KbT for the different CTMR configurations of the logic block

0th order CTMR1st order CTMR2nd order CTMR

(a) inputs are uniformly distributed

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 11

1.5

2

2.5

3

3.5

4

Different values of kbT (Thernmal energy levels) →

Ent

ropy

→

The entropy at different values of KbT for the different CTMR configurations of the logic block

0th order CTMR1st order CTMR2nd order CTMR

(b) inputs are logic high with 0.8 probability

Figure 6. Entropy for different orders of CTMR configurations for the logic block in Figure 5 at differentKbT values.

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