Motivation for Lecture Design Methodologies Market for … · 2011-11-07 · Market for Memories According to a new technical market research report, semiconductor Memory: Technologies

Viktor Öwall, Inst. för Elektro- och Informations Teknologi, Lunds Universitet, www.eit.lth.se!

Design Methodologies

Viktor Öwall

•  Storage (registers and memories) •  Computational platforms •  Design Methodologies


Motivation for Lecture •  Memories is a crucial part of most designs:

–  What different type of memories are there? –  How do we implement them?

•  Computational Platforms: –  What options do we have? –  What are the trade-offs?

•  Design Methodologies: –  What does a modern digital design

environment look like?


Cell-phone ASIC complexity and cost!

Courtesy: Sven Mattisson, Ericsson


Market for Memories According to a new technical market research report, semiconductor Memory: Technologies and Global Markets, the value of the global semiconductor memory industry was nearly $46.2 billion in 2009, but is expected to increase to nearly $79 billion in 2014, for a 5-year compound annual growth rate (CAGR) of 11.3%. The largest segment of the market, DRAM, or dynamic random access memory, is projected to increase at a CAGR of 10.4% to $41.5 billion in 2014, after being valued at nearly $25.2 billion in 2009. NAND, or nonvolatile/NANO RAM, which is the second-largest segment of the market, is estimated at $12.8 billion in 2009, and is expected to increase at a 5-year CAGR of 15% to reach more than $25.7 billion in 2014.

Source: Semiconductor Memory: Technologies and Global Markets, April 2010 From http://www.electronics.ca/presscenter/articles/1272/1/Global-Market-For-

Semiconductor-Memory-To-Be-Worth-79-Billion-In-2014/Page1.html Report Price: Price:USD $4,850.00!!!

Motivation behind the quest for new memory technologies!


Example: FFT Design 8k points FFT for DVB (Digital Video Broadcasting) 1996-97 in 0.5mm CMOS

Several embedded memories who’s properties and size is crucial to the implementation


Sequential Circuits & D flip-flop

From Lecture 3.

Properties: •  can be dynamic or static •  Latch or Register

•  Latch - level sensitive •  Register - edge triggered

Flip-flop most often refer to an edge triggered register.


Latches and Registers

Figures from Digital IC Design Viktor Öwall, Inst. för Elektro- och Informations Teknologi, Lunds Universitet, www.eit.lth.se!

Dynamic or Static

Positive Feedback Data is kept as long as power supply is there

Stored on capacitance Data will change due to leakage. Refresh needed to keep data.


Master Slave Registers

If a single latch we can get a race when the latch is open

We then use a Master-slave register. Viktor Öwall, Inst. för Elektro- och Informations Teknologi, Lunds Universitet, www.eit.lth.se!

Dynamic or Static


We have registers, why memories?

Static D Flip-flop : 252µm2 SRAM Memory element : 30µm2

0.35µm CMOS technology process


Flip-flops vs. SRAM

0 500 1000 1500 2000 2500 3000 3500 4000 45000

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

memory elementssq

uare

mm

Flip-flopsDual port memorySingle port memoryDouble width memory

Alcatel Microelectronics 0.35µm CMOS technology process Process and library dependent.

Flip-flops

SRAM


A memory is more than the storage elements, i.e. the memory cells.

Address decoders, sense amplifiers,

clock buffers, etc


The Complete Memory

An Overview of Logic Architectures Inside Flash Memory Devices ANDREA SILVAGNI, GIUSEPPE FUSILLO, ROBERTO RAVASIO, MASSIMILIANO PICCA, AND STEFANO ZANARDI PROCEEDINGS OF THE IEEE, VOL. 91, NO. 4, APRIL 2003

Memory

array


Semiconductor Memory Classification Read-Write Memories

(RWM) Nonvolatile

RWM (NVRWM)

Read-Only Memories (Nonvolatile)

Random Access

Non-Random Access

SRAM

DRAM Register-

Bank

FIFO

LIFO(Stack)

Shiftregister

PROM

EPROM

E2PROM

FLASH

ROM

PLA

Nonvolatile = data kept when supply voltage turned off PROM = Programmable rom EPROM = erasable programmable ROM E2PROM & Flash= electrically erasable programmable ROM


XXPROM & Flash

Nonvolatile = data kept when supply voltage turned of PROM = Fuse based a One time programmable EPROM = Usually erasable by UV-light

Usually high voltage for programming a removed from circuit when programmed

EEPROM or E2PROM = Individual bytes can be erased a slow but versatile

Larger than EPROM Flash= Larger sections are erased a faster than EEPROM


We will now look at some basic implementations

•  ROM •  FLASH •  RAM

–  Static –  Dynamic


Pseudo NMOS ROM

WL[0]

V DD Pull Up

WL[2]

WL[3]

WL[1]

BL[3] BL[0] BL[1] BL[2]

The placements of transistors decide memory content.

Do we recognize this?


Pseudo-NMOS Gates V

DD

B

GND

A OUT

Pull up network

Pull down network

Properties: + fewer transistors - Static power consumption -  Low input ”not 0”

From last lecture: What was the function?

A B OUT

0 1

1 1 1

0 0

0


Pseudo NMOS NAND ROM

All transistors ON pulls down Bit Line Non-selected WL =1

WL lines reversed

A B Q 0 0 1 0 1 1 1 0 1 1 1 0

Select WL[2] a WL[0,1,3]=1 and WL[2] = 0

1

1

0

1

on

on

on

off off

Transistor on selected line shuts off path to GND

WL[0]

V DD Pull Up

WL[2]

WL[3]

WL[1]

BL[3] BL[0] BL[1] BL[2]


Pseudo NMOS NOR ROM

NMOS NOR ROM GND lines overhead Area Reduced by Mirroring

One transistor ON pulls down Bit Line

A B Q 0 0 1 0 1 0 1 0 0 1 1 0

No transitors = always pulled up

BL[0]

V DD

Pull Up

BL[1] BL[2] BL[3]

GND

GND WL[2]

WL[3]

WL[1]

WL[0]


Pseudo NMOS NOR ROM

NMOS NOR ROM GND lines overhead Area Reduced by Mirroring

One transistor ON pulls down Bit Line

A B Q 0 0 1 0 1 0 1 0 0 1 1 0

Select WL[2] a WL[0,1,3]=0 and WL[2] = 1 0 0 1 1

V DD

Pull Up

GND

GND WL[2]=1

WL[3]=0

WL[1]=0

WL[0]=0


NOR or NAND?

•  NOR is faster – no series transistors.

•  NAND is smaller – no GND lines.

You can see this if you look at e.g. FLASH memories


What is a Flash memory?

•  ROM – Read Only Memory

•  RAM – Random Access Memory

•  FLASH


What is a Flash memory?

•  ROM – Read Only Memory –  data doesn’t change –  data remain when powered down

•  RAM – Random Access Memory –  data can be both read and stored –  data disappears when powered down

•  FLASH –  data can be both read and stored –  data remain when powered down


Floating Gate Transistor (FAMOS) electrically programmable VTH

n + n +

Floating gate Control gate

•  Control gate is connected to wordline •  Floating gate is left unconnected

–  If charged heavily negative a High VTH a No channel –  If charged removed a Low VTH a Channel

•  EPROM, EEPROM and Flash has different ways of controlling the charge of the floating gate

WL BL


Flash EEPROM

Control gate

erasure

p- substrate

Floating gate

Thin tunneling oxide

n 1 source n 1 drain programming


FLASH stucture V DD

Pull Up

GND

GND word2

word3

word1

word0

Floating gate transistors everywhere!


FLASH write, e.g. trap charge V DD

Pull Up

GND

GND word2

word3

word1

word0

= trapped charge. Transitor is always off a Same content as ROM.


Read-Write Memories (RAM)

•  Static (SRAM) –  Data stored as long as supply is applied –  Large cells (6 transistors/cell) –  Fast

•  Dynamic (DRAM) –  Periodic refresh required –  Small cells (1-3 transistors/bit) –  Slower


Dynamic or Static RAM 6-transistor SRAM Cell

WL

BL BL

M5 Q

M1 M3

M6

M4 M2 Q

V dd

M 1 C S

WL

BL

C BL

1-transistor DRAM

Compare dynamic latch/register Viktor Öwall, Inst. för Elektro- och Informations Teknologi, Lunds Universitet, www.eit.lth.se!

Computational Platforms


Software vs. Hardware

Algorithm

Dedicated Hardware

Processor

•  Programmable •  “Low” Design cost

CPUs, micro processors, micro controllers, …

•  Process chips •  High Performance •  Low Power •  High cost

Programmble Hardware

•  Reconfigurable hardware •  No processing

Programble Logic Devices (PLD): PLA, PAL, FPGAs, Gate array (include processing), … Viktor Öwall, Inst. för Elektro- och Informations Teknologi, Lunds Universitet, www.eit.lth.se!

Software or Hardware? •  Flexibility •  Performance Requirements

–  Power Consumption –  Throughput

•  Cost –  Volume –  Know how –  Time to Market


Dedicated Hardware Architecture, i.e. you design hardware that makes what you want!

Special Purpose

PLD, e.g. FPGA

Field Programmable Gate Arrays •  Reconfigurable •  Fast Turn Around •  Prototyping

Gate Array

ASIC

Application/Algorithm Specific Integrated Circuit •  High Calculation Capacity •  High Utilization •  Low Power •  Low Price at Volume


Virtex from Xilinx BANK 0 BANK 1

BANK 5 BANK 4

BA

NK

6

BA

NK

7

BA

NK

3

BA

NK

2

IOB

Block RAM

CLB

Timing

Routing


Example: Xilinx FPGAs

CLB CLB

CLBCLB

HorizontalRoutingChannel

VerticalRoutingChannel

Interconnectpoint

Switchingmatrix

Configurable Logic Block

R Q 1 D CE R Q 2 D CE

F G

F G

F

G

R D in

Clock CE

F

G

A B/Q 1 /Q 2 C/Q 1 /Q 2

D A

B/Q 1 /Q 2 C/Q 1 /Q 2

D E

Combinational logic Storage elements

Any function of up to 4 variables

Any function of up to 4 variables


Basic Spartan Architecture – Low end FPGA


Xilinx Virtex-II Pro – Heterogeneous Programmable Platforms

Courtesy Xilinx High-speed I/O

Embedded PowerPc Embedded memories

Hardwired multipliers

FPGA Fabric


From Xilinx: www.xilinx.com


Examples of FPGA Development Boards e.g. from Digilent (http://www.digilentinc.com)

Spartan3 Board •  US$193 (2011) •  Xilinx Spartan-3 FPGA w/ twelve 18-bit multipliers, 216Kbits of block RAM •  2Mbit Platform Flash •  Serial port, VGA port, and PS/2 mouse/keyboard port •  1Mbyte on-board 10ns SRAM •  etc

Virtex-II Pro Board •  US$1599, (499 academic) (2011) •  Virtex-2 Pro XC2VP30 FPGA with 30,816 Logic Cells, 136 18-bit multipliers, 2,448Kb of block RAM •  DDR SDRAM DIMM that can accept up to 2Gbytes of RAM •  10/100 Ethernet port, USB2 port, XSGA Video port •  Audio Codec •  Compact Flash card slot •  etc


Gate Arrays – “the old way” Fabricating with an array of n- and p-transistors and using design-specific metalization in routing channels.

Before metalization After metalization


Design Hardware, i.e. ASIC (Application Specific Integrated Circuit)

ASIC

Full Custom Synthesis

Behavioral or Structural Synthesis •  Use Cell library •  “Fast” Design Process •  Simplified re-design

Design for Performance •  Layout of all cells

•  Highest Calculation Cap. •  Lowest Power •  Smallest area •  Highest Design Cost

Semi Custom


Design Methodologies


Design Methodology Three abstractions: Behavioral, structural and geometrical


Design Methodology, contnd.

Moving betwen the domains Amount of Automatization increase


“Standard” Design Flow of Today


RTL- Implementation, we specify registers and operations

without clocking separately. 32

48

Y=A*B+C

A

B C

Y


Design Flow: a simplified view HDL (VHDL/Verilog/...)

P&R

Cell library

Configuration Post-layout sim.

Simulation

Synthesis

Fabrication


Very High Speed Integrated Circuit (VHSIC) Hardware Description Language

A Technology Independent, Standard Hardware description Language

(HDL), used for digital system modeling, simulation, and synthesis.

VHDL was developed as a language for modeling and simulation. Consequence: Mismatch between simulation and synthesis -- Most constructs in VHDL are fine for simulation, but cannot be synthesized, e.g., after, time, etc. With restrictions, VHDL can be used for synthesis.

VHDL


Some small examples of designing with VHDL.

You’re not expected to learn VHDL but just

get an impression what it looks like


Combinational and Sequential Parts


Process – Multiplexer


Process – Example II


Process – Example II process (clk, reset) begin if clk’event and clk=’1’

then if (Reset = '0') then Q <= '0'; elseif enable=’1’ then Q <= D; end if; end if; end process ;

register with synchrounus reset


Case command •  Example: Multiplexer

architecture behv1 of Mux is begin process(I3,I2,I1,I0,S) --nested in process begin -- use case statement case S is when "00" => Op <= I0; --sequential statements when "01" => Op <= I1; when "10" => Op <= I2; when "11" => Op <= I3; when others => Op <= "ZZZ"; -- end case;

end process; end behv1;

S

I0 I1 I2 I3


IF vs. CASE statements If and case statements generate different HW

If statement If (c1= ’1’) then q <= a; Elseif (c2 = ’1’) then q <= b; Else q <= c; End if;

b

Mux

q

Mux

c

a

c2 c1

Case statement Case c is when ”01” => q <= a; when ”10” => q <= b; when others => q <= c; End case;

b Mux q

c

c

a

Use case if you have more than 3 inputs Viktor Öwall, Inst. för Elektro- och Informations Teknologi, Lunds Universitet, www.eit.lth.se!

You need to understand the underlying hardware and what the tools do to be

able to write good HDL code.

The same as for any other program!


Basic State Machine

St1 St0 ”01” / ”01”

”00” / ”11”

”01” / ”01” ”00” / ”00”

”00” / ”11”

”00” / ”00”

”01” / ”10”

”01” / ”10” A Typical state machine

St3 St2


Transforming a State Machine into HW

Behavioural Logic

D

Combinatonial part

SequenAal part

Output q

Input d

State r

Clock next state rin

Generic Architecture for FSMs

St1 St0 ”01” / ”01”

”00” / ”11”

”01” / ”01” ”00” / ”00”

”00” / ”11”

”00” / ”00”

”01” / ”10”

”01” / ”10” Typical FSM

St3 St2


Realization of FSMs

Entity declaration library IEEE;use IEEE.STD_LOGIC_1164.all; entity state_machine is port (clk : in STD_LOGIC; reset : in STD_LOGIC; input : in STD_LOGIC_VECTOR(1 downto 0); output : out STD_LOGIC_VECTOR(1 downto 0) );

end state_machine;

St1 St0 ”01” / ”01”

”00” / ”11”

”01” / ”01” ”00” / ”00”

”00” / ”11”

”00” / ”00”

”01” / ”10”

”01” / ”10”

St3 St2


Realization of FSMs- cont’d

Architecture declaration (combinatonial part) architecture implementation of state_machine is type state_type is (st0, st1,st2, st3); -- defines states; signal state, next_state : state_type; signal next_output STD_LOGIC_VECTOR (1 downto 0);

begin combinatonial : process (input,state,state) begin case (state) is -- Current state and input dependent when st0 => if (input = ’01’) then next_state <= st1; output <= ”01” end if; when .... when others => next_state <= next_state; -- Default

output <= ”00”; end case; end process;

St1 St0 ”01” / ”01”

”00” / ”11”

”01” / ”01” ”00” / ”00”

”00” / ”11”

”00” / ”00”

”01” / ”10”

”01” / ”10”

St3 St2


Realization of FSMs- cont’d

Sequential part: synchronous : process (clk,reset) begin if clk’event and clk = ’1’ then if reset = ’1’ then state <= st0; else state <= next_state; end if;

end if; end process; end architecture;

St1 St0 ”01” / ”01”

”00” / ”11”

”01” / ”01” ”00” / ”00”

”00” / ”11”

”00” / ”00”

”01” / ”10”

”01” / ”10”

St3 St2

Behavioural Logic

D

Combinatonial part

SequenAal part

Output q

Input d

State

Clock

next _state


You can learn more in

ETIN20 Digital IC-design.

and

EITF35 Introduction to Structured VLSI Design

Documents

Motivation for Lecture Design Methodologies Market for … · 2011-11-07 · Market for Memories According to a new technical market research report, semiconductor Memory: Technologies