VLSI Design IThe MOSFET modelWow ! Are device models as nice as Cindy ?
Overview The large signal MOSFET model and second order effects. MOSFET capacitances. Introduction in fet process technology Goal: You can use the large signal equivalent MOS device equation. You are familiar with second order effects like body effect, channel length modulation. You know the MOS capacitances. You know the basic steps in MOS fabrication.MicroLab, VLSI-2 (1/24)JMM v1.4
Lets build a MOSFETThere are lots of different recipes to choose from. Like most things in life, you get what you pay for: the ability to have good bipolar devices, radiation hardness, reduced latch-up and substrate noise, are all extra cost options. Well consider a general process: bulk CMOS with a p-type substrate:
Use surface to minimize surface charge
500um slice of a silicon ingot that has been doped with an acceptor (typically boron) to increase the concentration of holes to 1014/cm3 - 1018 /cm3.
p-type Back is metallized to provide a good ground connection.
Good for n-channel fets, but p-channel fets will need a n-type well (or tub) to live in!MicroLab, VLSI-2 (2/24)JMM v1.4
Next, a thick (0.4um) layer of silicon dioxide, called field oxide, is formed on the surface by oxidation in wet oxygen. This is then etched to expose surface where we want to make a mosfet:
Now grow a thin (0.01um = 100 ) layer of silicon dioxide, called gate oxide, on the surface by exposing the wafer to dry oxygen.
The gate oxide needs to be of high quality: uniform thickness, no defects! The thinner the gate oxide, the more oomph the fet will have (well see why soon) but the harder it is to make it defect free.
MicroLab, VLSI-2 (3/24)JMM v1.4
On top of the thin oxide a 0.7um thick layer of polycrystalline silicon, called polysilicon or poly for short, is deposited by CVD. The poly layer is patterned and plasma etched (thin ox not covered by poly is etched away too!) exposing the surface where the source and drain junctions will be formed:gate oxide (only under poly)
exposed surface for source and drain junctions
Poly has a high sheet resistance (25 ohms/square) which can be reduced by adding a layer of a silicided refractory metal such titanium (TiSi2), tantalum (TaSi2) or molybdenum (MoSi2). These have sheet resistances of 1, 3 or 5 ohms per square, respectively. This is great for memory structures that have lots of poly wiring.
MicroLab, VLSI-2 (4/24)JMM v1.4
The entire surface is doped, either by diffusion or ion implantation, with phosphorus (an electron donor) which creates two n-type regions in the substrate. The phosphorus also penetrates the poly reducing its resistance and affecting the nfets threshold.diffusions are self-aligned with poly n+ n+ wires: 20-30 ohms/sq. n+ p
Finally an intermediate oxide layer is grown and then reflowed to flatten its surface. Holes are etched in the oxide (where contacts to poly/diff are wanted) and aluminum deposited, patterned and etched.metal wires (0.08 ohms/square)
??? diff contact (0.25 - 10 ohms)
n- channel MOS field effect transistor!MicroLab, VLSI-2 (5/24)
NFET OperationPicture shows configuration when Vgs < Vto S G D Ids = 0
n+ p mobile holes, fixed negative ions B
no mobile carriers, but fixed negative ions (slight intrusion into n+, but mostly in p area) Other symbols: S
mobile electrons, fixed positive ions (n+ means heavily doped with donors, doesnt imply positive charge!) Terminal with higher voltage is labelled D, the other is labelled S so Ids >= 0. D
almost always groundMicroLab, VLSI-2 (6/24)
FET = field effect transistorThe four terminals of a fet (gate, source, drain and bulk) connect to conducting surfaces that generate a complicated set of electric fields in the channel region which depend on the relative voltages of each terminal.Picture shows configuration when Vgb > Vto gate inversion happens here Eh source Ev drain
bulk INVERSION: A sufficiently strong vertical field will attract enough electrons to the surface to create a conducting n-type channel between the source and drain. CONDUCTION: If a channel exists, a horizontal field will cause a drift current from the drain to the source. Expect Ids proportional to Vds*(W/L)?MicroLab, VLSI-2 (7/24)JMM v1.4
Threshold voltageThe gate voltage required to form the channel is called the threshold voltage. Many factors affect the gate-source voltage at which the channel becomes conductive. Threshold voltage for source-bulk voltage zero:
VTO ? V t ? ms ? Vfb?? ? ? ? ?? ? ? ? Q Q VTO ? 2 ? b ? b ? ? ms ? fc ? C C ox ox0.7V for n-channel 2 kT ln? NA ? ? ? -0.7V for p-channel q ? n i ? ? ?
? ox t ox
kT ? NDN A ? ln? 2 ? q ? ni ? ? ?2 ? si qN A 2 ? b
MicroLab, VLSI-2 (8/24)JMM v1.4
Body effect (second order)As Vsb increases, the depth of the depletion region increases, exposing more of the fixed acceptor (i.e. negative) ions in the substrate. Thus the second term in the threshold voltage equation on the previous slide increases from to2 ? siqNA 2 ?b b
2 ? siqNA ?Vsb ? 2 ?
the threshold voltage of the n-channel transistor is now:Vtn ? Vtn0 ? ? ? Vsb ? 2 ? b ? 2 ?b
2? siqN A C ox
As well see, this effect comes into play in series-connected fets where only one of the fets will have Vsb = 0 and the other fets will have Vsb > 0 and a higher threshold voltage.JMM v1.4
Vsb>0 T1 Vt2> Vt1 Vsb=0
MicroLab, VLSI-2 (9/24)
Basic DC equationsMOS transistors have 3 regions of operation: ?cutoff region (subthreshold) ?linear region (triode region) ?saturated region (active region)polysilicon gate SiO2 source diffusion W L
Cutoff or subthreshold region: Vgs Vt 0 < Vds < VdsatIds
Larger Vgs creates deeper channel which increases Ids channel length is almost always min allowable mobility (un > up)
Larger Vds increases drift current but also reduces vertical field component which in turn makes channel less deep. Channel will pinch-off, when
Vds = Vgs - Vt = Vdsat2 Vds ? ? 2 ?
fet gain factor k=Cox
W ? ? ox ? I ds ? ? Vgs ? V t Vds ? L t ox ?
max value at Vds = Vdsat, but then channel is pinched off (see next slide)JMM v1.4
only linear when Vds is small, otherwise parabolicMicroLab, VLSI-2 (11/24)
Saturated operating regionVs Vgs > Vt Vdsat < VdsIds
Voltage at channel end remains essentially constant at Vdsat so drift current also remains constant: device is in saturation .
Electrons arriving from source are injected into drain depletion region and accelerated towards drain by field proportional to Vds - Vdsat usually reaching the drift velocity limit.
W ? ? ox I ds ?sat ? ? Vgs ? Vt 2 L t ox
this is just Ids from previous slide evaluated at Vds = VdsatMicroLab, VLSI-2 (12/24)JMM v1.4
Channel-length modulation (second order)Vs Vgs > Vt Vdsat < VdsIds
L = L - dL dL
This looks just like a fet with a channel length of L < L. Shorter L implies greater Ids...
As Vds increases, dL get larger
As Vds increases the effective channel length gets shorter so Ids(sat) increases. dL is proportional to Vds ? Vdsat but most people approximate channel length modulation as a linear effect:W ? ? ox I ds ?sat ? ? Vgs ? Vt 2 L t ox
? ?1 ? ? V2
MicroLab, VLSI-2 (13/24)JMM v1.4
NFET Ids curvesPut it together and what have you got?
plot of Ids vs. Vds for Vgs = 0 ,1, 2, 3, 4 and 5V
Can you find the following in the plot? Ids vs. Vds when Vgs = 0V Ids vs. Vds when Vgs = 5V value of Vt value of Vdsat evidence of body effect evidence of channel length modulationMicroLab, VLSI-2 (14/24)JMM v1.4
SPICE ModelsThere are different models used in circuit simulators: ? level 1 is our simple model including the most important second order effects described ?level 2 model is based on device physics ?level 3 is a semi-empirical model allowing to match equations to the real circuit: example BSIM model from Berkeley models subthreshold characteristics ?summary of the main SPICE DC parameters used in all three models at the end of this chapter
. M1 4 3 5 0 nfet W=1u L=0.5u AS=1p AD=1p PS=3u PD=3u . . .MODEL nfet NMOS +TOX=1E-8 +CGB0=345p CGS0=138p CGD0=138p +CJ=775u CJSW=344p MJ=0.35 MJSW=0.26 PB=0.75 +. . . . . .MicroLab, VLSI-2 (15/24)JMM v1.4
MOSFET Capacitance Estimationthe dynamic response of MOS systems strongly depends on the parasitic capacitances associated with the MOS device. The total load capacitance on the output of a CMOS gate is the sum of: ?gate capacitance (of other inputs connected to out) ?diffusion capacitance (of drain/source regions) ?routing capacitances (output to other inputs)Cgd gate Cgs source Cgb Cgs source Csb Cgb channel depletion layer substrateMicroLab, VLSI-2 (16/24)JMM v1.4
Cdb substrate Csb gate Cgd tox drain Cdb
MOSFET gate capacitancesCg = Cgd + Cgs + Cgb Oxide-related capacitances come in two forms: ? overlap capacitance (extrinsic) since gate slightly overhangs diffusions and bulk:for both Cgs and Cgd amount of overlap
C(overlap) = W LD Cox C(overlap) = 2L CGB0for Cgb
for SPICE Cgs = W CGS0 Cgd = W CGD0 Cgb = 2L CGB0
?channel-charge related capacitances (intrinsic): cut-off: Cgb = Cox W L Cgs = Cgd = 0 linear:shielded by channel Cgb = 0 Cgs = Cgd = 0.5 Cox W L
equally shared between S and D note c