EKV3 MOSFET Model Status, Analog/RF Capabilities, and

EKV3 Workshop CSEM, Neuchatel, June 30, 2008

EKV3 MOSFET ModelStatus, Analog/RF Capabilities, and ongoing Developments

Matthias BucherTechnical University of Crete (TUC), Greece

2EKV3-Day, CSEM, June 30, 2008M. Bucher TUC

Outline

�Team & partnerships�Moderate Inversion in Advanced CMOS

� Modeling �� Characterization �� Circuit Design

�Current Status of EKV3� Verilog-A Code� IV, CV, T scaling

�Analog/RF capabilities of EKV3�Conclusions


EKV team, industry, r&d projects

� EPFL, Switzerland� François Krummenacher, Jean-Michel

Sallese, Christian Enz, Ananda Roy

� TUC Greece� Matthias Bucher, Antonios Bazigos

� GMC-Suisse� Wladek Grabinski

� Companies supporting EKV3: � Atmel� austriamicrosystems� Cypress Semiconductor� Infineon� Toshiba� XFAB

� COMON FP7 Project (2008-2011)� FinFET and HVMOS modelling


Moderate inversion – low- frequency

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

0.001 0.01 0.1 1 10 100 1000

IC = ID / Ispec [-]

gms

* U

T /

ID [-

]

10x1010x210x110x0.510x0.310x0.2510x0.210x0.1610x0.1410x0.13510x0.125

IC

ICGI

Ug

D

Tms

++==⋅

41

21

1)(

Moderate Inversion

measured

VD=VG

LNormalized Transconductance Normalized Output Conduc tance

SPEC

D

I

IIC =

L

WCnUI oxTSpec ′= µ22

Inversion Coefficient

Specific Current�Normalization factor for drain current: Ispec�Normalized gm and gds vs. IC and L�Anomalous scaling of output conductance in WI

0.1

1

10

100

1000

0.001 0.01 0.1 1 10 100 1000

IC = ID / Ispec [-]

VA

= ID

/gds

[1/V

]

10x1010x210x110x0.510x0.310x0.2510x0.210x0.1610x0.1410x0.13510x0.125

Moderate Inversion


Moderate inversion – high frequency

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5

VG [V]

C /

Cox

*Wef

f*Le

ff [-

]

CGG Vc=0VEKV3.0CGC Vc=0VEKV3.0CGC Vc=0.5VEKV3.0CGC Vc=1VEKV3.0

Moderate InversionOverlap & fringing caps.

(do NOT scale with L)

Moderate Inversion in MOSFETs – highly important for analog/RF IC design� Good trade-off among gain, speed, linearity, noise, matching� Low-medium saturation voltage, Series resistance effect negligible� Reduced impact of mobility effects (vertical field) and velocity saturation

CV characteristics of MOSFETs

Moderate Inversion

Transit Frequency f T of MOSFETs


EKV3 model overview

� Due to CMOS scaling, ICs operate more and more in moderate and weak inversion

� Design methods and models are required– ‘classical’ methods don’t cover moderate inversion

� EKV3 is a Compact MOS Transistor Model dedicated to Analog/RF IC design� Developed as a successor of EKV2.6 (since 1997)� Charge-based approach – close to physics and design� Special attention to analog/RF IC design requirements� Covers essential effects down to 65nm CMOS� Scaling over Technology – Width – Length – T – Bias� EKV3 available in CAD tools (ELDO, Cadence, Smash).� Available Parameter Extraction Toolkits


EKV3 – charge model basics

� Basis of charge model development is surface potential equation & inversion charge linearization� Same parameters as surface potential model� Preserves the essence of a surface potential model.

� Extensions for CV:� Vertical non-uniform doping� Polydepletion� Quantum effects

� Extensions of IV:� Charge-based vertical field mobility � Charge-based velocity saturation� Charge-based CLM� Gate tunnelling


EKV3 mobility modelling

� Effective-field based mobility modelling

� Surface-roughness scattering (high vertical field)

� Phonon-scattering intermediate field strengths

� Coulomb scattering effects(low vertical field; particularly at very high Nsub, low T)

� 5 parameters in all:

� E0, E1, ETA, THC, ZC

� Local mobility is integrated along the channel

ibeff QQE ⋅+∝ η


EKV3 velocity saturation/CLM modelling

� Variable-order (1st-2nd), charge-based velocity-field relationship

� Continuous at VD=VS

� Requires 2 parameters:

UCRIT, DELTA [1..2]

� Scales mobility with channel Length

� Charge-based channel length modulation (CLM) model.

� Continuous at VD=VS

LAMBDA

1.0

0.9

0.8

0.7

0.6

0.5

0.4

µ / µ

0 [-]

10-7

2 3 4 5 6 7 8

10-6

2 3 4 5 6 7 8

10-5

2 3 4 5

L [µm]

Velocity saturation models: first order ( β=1): EC=5MV/m second order ( β=2): EC=2.9MV/m variable order ( δ=1.7): EC=3.45MV/m

EII*L=0.5V

1.00

0.98

0.96

0.94

µ / µ

0 [-]

-40x10-3

-20 0 20 40

EII / EC [-]

δ=1.7

δ=1

β=1

β=2 δ=2


EKV3 model scaling effects

� RSCE, INWE, combined short&narrow-channel effects� DIBL, charge-sharing� Halo/Pocket implant effects

� including @long channel

� Bias-dependent overlap & inner fringing capacitances� Bias-dependent series resistance � Geometry & temperature scaling� Parasitic effects modelling

� Layout dependent stress� Edge conduction� Gate tunneling� ….


Phenomena covered by EKV3

[Channel Segmentation]NQS

[Appropriate Scaling of RG, RSUBswith W, L and NF]

RF ModelExternal Sub-Circuit

IBA, IBB, IBNImpact Ionization Current

KG, XB, UBGate Current (IGS, IGD, IGB)

LOV, GAMMAOV(NOV), VFBOVBias-Dependent Overlap Capacitances

KP(U0), E0, E1, ETA

ZC, THC

Mobility (Reduction due to Vertical Field Effect) Surface Roughness-, Phonon-, Coulomb Scattering

COX(TOX), PHIF, GAMMA(NSUB), VTO(VFB), GAMMAG(NGATE)

Physical Modelling of Charges Including Accumulation RegionPolysilicon Depletion, Quantum Mechanical Effects

Modelled effect Related Parameters / Comments


Phenomena covered by EKV3

WEDGE, DGAMMAEDGE, DPHIEDGEEdge Conduction

AF, KFNoiseFlicker Noise, Short-Channel Thermal Noise,Induced Gate and Substrate Noise

LETA0Halo/Pocket implant effects

Various ParametersTemperature Effects

Various Parameters (DL, WQLR, … )Geometrical Effects, Width scaling

LETA, {LETA2}, WETASource and Drain Charge Sharing

LR, QLR, NLRReverse Short Channel Effect

WR, QWR, NWRInverse Narrow Width Effect

ETAD, SIGMADDrain Induced Barrier Lowering

UCRIT(VSAT), LAMBDA,

DELTA

Longitudinal Field EffectVelocity Saturation, Channel Length Modulation

TOTAL

Modelled effect Related Parameters / Comments

<140


EKV3 parameter set

* Long-ch. gds degr. * Gate current+ PDITS = 2.58E-6 + KG = 50.0E-6+ PDITSD = 0.91 + XB = 5.5+ PDITSL = 0.0 + EB = 21.0E+9+ FPROUT = 1.85E+6 + LOVIG = 40.0E-12+ DDITS = 0.1 * Temperature par.* Matching par. + TNOM = 30.0+ AVTO = 0.0 + TCV = 600.0E-6+ AKP = 0.0 + BEX = -1.6+ AGAMMA = 0.0 + TE0EX = -4.15* Vsat & CLM par. + TE1EX = 0.0+ UCRIT = 5.0E+6 + TETA = 2.0E-3+ DELTA = 1.5 + UCEX = 1.2+ LAMBDA = 0.5 + TLAMBDA = 0.15+ ACLM = 0.85 + TCVL = 0.0* Geometrical par. + TCVW = 0.0+ DL = -16.7E-9 + TCVWL = 0.0+ DLC = -23.0E-9 + WDL = 0.0+ LL = 0.0 + LLN = 1.0+ DW = -45.3E-9 + DWC = 0.0+ LDW = 0.0

* Flags * Charge sharing+ SIGN = 1 + LETA0 = 1.0E+6+ TG = -1 + LETA = 1.3* Scale parameters + LETA2 = 0.0+ SCALE = 1.0 + WETA = 1.0+ XL = 0.0 + NCS = 0.5+ XW = 0.0 * DIBL* Cgate parameters + ETAD = 0. 75+ COX = 8.58E-3 + SIGMAD = 1.0+ GAMMAG = 18.4 * RSCE+ AQMA = 0.0 + LR = 100E-9+ AQMI = 0.0 + QLR = 580E-6+ ETAQM = 0.75 + NLR = 100.0E-3* Nch. parameters + FLR = 2+ VTO = 400.0E-3 * INWE+ PHIF = 450.0E-3 + WR = 80.0E-9+ GAMMA = 300.0E-3 + QWR = 500.0E-6+ XJ = 30.0E-9 + NWR = 12.0E-3+ N0 = 1.025 * Series resistance* Mobility + RLX = 170.0E-6+ KP = 390.0E-6 * Overlap & fringing+ E0 = 438.0E+6 + LOV = 25.0E-9+ E1 = 159.0E+6 + GAMMAOV = 5.0+ ETA = 0.57 + VFBOV = 0.0+ ZC = 1.0E-6 + KJF = 150.0E-12+ THC = 0.0 + CJF = 300.0E-3


EKV3 parameter extraction sequence

� Use conventional IV & CV data� Sequence: CV, then wide/long IV, wide/short IV, narrow/long IV, narrow/short IV,

T.� IF specific measurements can be made, use Pinch-off voltage technique� Has been implemented in IC-CAP (Agilent)

Parameter Extraction in Moderate Inversion


Pinch-off voltage measurement in MI

-0.2

0

0.2

0.4

0.6

0.8

1

1.2

0 0.2 0.4 0.6 0.8 1 1.2

VG [V]

VP

[V

]

DataEKV3

1

1.02

1.04

1.06

1.08

1.1

0 0.2 0.4 0.6 0.8 1 1.2

VG [V]

n [-

]

DataEKV3

� VP = 0V corresponds to VTO = 125mV , n0 ~= 1.07

� Substrate effect (GAMMA) and other substrate parameters (PHIF ) can be extracted as well

VTO~= 125mV

nO ~= 1.07

W =

2um

, L =

0.5

um

IB ~= 0.6*Ispec moderate inversion


VTO and n0 vs. W, L

� Threshold voltage VTO� vs. L shows known reverse short-channel effect (RSCE)� Less pronounced RSCE @ narrow channel.

� Slope factor n0� vs. L: n0 reduced due to charge-sharing, DIBL� vs. W: almost unaffected.

L [um]L [um]

W [um]W [um]

VTO [V] n0 [-]


EKV3 – ID-VG

0.0E+00

5.0E-03

1.0E-02

1.5E-02

2.0E-02

2.5E-02

3.0E-02

-0.5 0 0.5 1 1.5 2 2.5

VG [V]

sqrt(

ID)

[sqr

t(A

)]

Data

EKV3

Series3

Series4

Series5

Series6

Series7

Series8

Series9

Series10

1.0E-11

1.0E-10

1.0E-09

1.0E-08

1.0E-07

1.0E-06

1.0E-05

1.0E-04

1.0E-03

-0.5 0 0.5 1 1.5 2 2.5

VG [V]

ID [

A] Series1

Series2Series3Series4Series5Series6Series7Series8Series9Series10

W =

2um

, L =

0.5

um

0.0E+00

1.0E-04

2.0E-04

3.0E-04

4.0E-04

5.0E-04

6.0E-04

7.0E-04

8.0E-04

9.0E-04

-0.5 0 0.5 1 1.5 2 2.5

VG [V]

gm [S

]

DataEKV3Series4Series5Series6Series7Series8Series9Series10EKV3Series12Series13Series14Series15EKV3 Series17Series18Series19Series20

E1 = 90M

70M

50M

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0E-09 1.0E-08 1.0E-07 1.0E-06 1.0E-05 1.0E-04 1.0E-03

ID [A]

gm .

UT

/ ID

[-]

Series1

Series2

Series3

Series4

Series5

Series6

Series7

Series8

Series9

Series10


EKV3 – gate current

1.0E-15

1.0E-14

1.0E-13

1.0E-12

1.0E-11

1.0E-10

1.0E-09

1.0E-08

-0.5 0 0.5 1 1.5 2 2.5VG [V]

|IG|

[A]

DataEKV3

� All the tunneling current components are included� Extract tunneling current coefficients KG, XB, UB


EKV3 – STI edge conduction effectNMOS 10um/10um

0.0001

0.001

0.01

0.1

1

10

100

-20 0 20 40 60 80 100

vgb[-]

id[-]

NMOS 10um / 80nm VD = 1V

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100

id[-]

gm/id

[-]

NMOS 10um/10um VD=1V

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

0.0001 0.001 0.01 0.1 1 10 100

id[-]

gm/id

[-]

NMOS 10um / 80nm VD=1V

0.000001

0.00001

0.0001

0.001

0.01

0.1

1

10

100

-20 0 20 40 60 80 100

vgb[-]

id[-]

NMOS 10um / 10um VD = 50mV

1.0E-14

1.0E-13

1.0E-12

1.0E-11

1.0E-10

1.0E-9

1.0E-8

1.0E-7

1.0E-6

-0.5 0 0.5 1 1.5 2 2.5

VGB[V]

IG [A

]

NMOS 10um / 80nm VD = 50mV

1.0E-14

1.0E-13

1.0E-12

1.0E-11

1.0E-10

1.0E-9

1.0E-8

-0.5 0 0.5 1 1.5 2 2.5

VGB[V]

IG[A

]

Edge conduction effect on ID-VG, gm/ID-ID, and IG-V G

W =

10u

m, L

= 1

0um

W =

10u

m, L

= 8

0nm


EKV3 short-channel

� Correct weak & moderate inversion behavior� Smoothness and correct asymptotic behavior� Correct weak inversion slope and DIBL modeling

� Transconductance-to-current ratio vs. drain current (log. axis)

L=70nm VD=1.5V

1.0E-10

1.0E-09

1.0E-08

1.0E-07

1.0E-06

1.0E-05

1.0E-04

1.0E-03

1.0E-02

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8

VG [V]

ID [A

]

measuredEKV3.0

L=70nm VD=1.5V

0.0E+00

1.0E-01

2.0E-01

3.0E-01

4.0E-01

5.0E-01

6.0E-01

7.0E-01

8.0E-01

1.00E-08 1.00E-07 1.00E-06 1.00E-05 1.00E-04 1.00E-03 1.00E-02

ID [A]

GM

*UT

/ID [-

]

measuredEKV3.0


EKV3 short-channelL=70nm VB=0V

0.0E+00

1.0E-03

2.0E-03

3.0E-03

4.0E-03

5.0E-03

6.0E-03

7.0E-03

8.0E-03

9.0E-03

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8

VD [V]

ID [A

]

measuredEKV3.0

L=70nm VB=0V

1.0E-04

1.0E-03

1.0E-02

1.0E-01

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8

VD [V]

gds

[A/V

]

measuredEKV3.0

L=70nm VB=-1V

1.0E-05

1.0E-04

1.0E-03

1.0E-02

1.0E-01

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8

VD [V]

gds

[A/V

]

measuredEKV3.0

L=70nm VB=-1V

0.0E+00

1.0E-03

2.0E-03

3.0E-03

4.0E-03

5.0E-03

6.0E-03

7.0E-03

8.0E-03

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8

VD [V]

ID [A

]

measuredEKV3.0

�Illustrates combination of: DIBL, CS, velocity saturation, CLM modeling @ Lgate = 70nm


EKV3 temperature scaling

� ID – VG and ID (gds) - VD vs. T� NMOS transistors in 150nm CMOS


EKV3 temperature scaling

� VT vs. L and vs. T, VD = 2V� Single model cards for each type of device, all conditions

NMOS W = 25um PMOS W = 25um


EKV3 CV modeling

� Continuous model, symmetric and good reciprocity� Extension to cover depletion/accumulation� Bias-dependent overlap & inner fringing capacitance

� LOV, GAMMAOV(NOV), VFBOV, CJF, KJF

L = 120nm0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5

VG [V]

C /

Cox

*Wef

f*Le

ff [-

]

CGG Vc=0VEKV3.0CGC Vc=0VEKV3.0CGC Vc=0.5VEKV3.0CGC Vc=1VEKV3.0

2.5 V-1/2GAMMAOV

7 V-1/2GAMMAG

20 nmLOV

0 VVFBOV

200 mV-1/2GAMMA

250 mV (-900mV)VTO(VFB)

12mF/m2 (2.9 nm)COX(Tox)

400mVPHIF / Φf


EKV3 model for RF

� Non quasi-static model (NQS)� channel segmentation� consistent AC/transient

� Gate- and substrate- parasitics scale with multi-finger layout

~L/(Wf*NF)RDSB

~1/WfRB

~1/WfRSB, RDB

~Wf/(L*NF)RG


Multi-finger RF MOSFETs

� Layout of RF multi-finger MOSFET� Number of fingers – NF

� Finger Width – Wf

� Gate Length – L

G

Source=Bulk

Drain

� Ground-Signal-Ground (GSG) RF Pads� 2 port configuration

� Actual MOSFETs� Open-Short de-embedding structures

G G G

G G G G G

G

DrainGate

Source=Bulk

Source=Bulk

150 µm pitch

Wid

th o

f fin

ger


STI stress in multi-finger RF MOSFETs

� NMOS, L=180nm, Wf=2µm� Stress effects due to shallow-trench isolation (STI)

� Threshold voltage VT vs. NF

� Max. drain current ID / NF vs. NF

– EKV3□ meas.

VDS=50m, 0.5, 1V


EKV3 – NQS model @ RFNMOS Lg=80nm NMOS Lg=2um

Multifinger devices @ various VG values, saturation


EKV3 RF modeling

� fT versus IC in 110nm CMOS, EKV301.02 model� Highest fT is reached at IC ~10-30 (!)� Most probable range for biasing of RF circuits for low noise is:

1 < IC < 10 (depending on technology)

NMOS, L = 110nm PMOS, L=110nm


R2R current dividing circuit using MOSFETs

� Normalized branch currents vs. bias current in the R2R-MOSFET show correct current division principle� Requires that all MOSFETs share the same gate and bulk voltage� EKV3.0 (similarly as former versions of EKV) show correct behavior� The circuit was initially proposed for model benchmarking, M. Bucher, FSA

modeling committee meeting Aug. 1997

R2R MOSFET Current Division Circuit with EKV3.0

0.980

0.990

1.000

1.010

1.020

1.0E-07 1.0E-06 1.0E-05 1.0E-04

Ifs [A]

Nor

mal

ized

Bra

nch

Cur

rent

s [-

]

I(VI1)

I(VI2)

I(VI3)

I(VI4)

I(VI5)

I(VI6)


R2R circuit & matching

� 200 Monte-Carlo runs� includes matching for β, VTO, γ� Shows relative spread of branch current increases due to matching

� ELDO (C-Code) implementation used here� Matching can be implemented

� Verilog-A ?!� How to implement statistics? In particular, correlations?

Ifs=64uA, 200 MC Simulations

0

5

10

15

20

1.0E-06 1.0E-05 1.0E-04Current [A]

Occ

urre

nces

[-] I1

I2I3I4I5I6

Ifs=64uA, 200 MC simulations

0

5

10

15

0.90 0.95 1.00 1.05 1.10Normalized Current [-]

Occ

urre

nces

[-]

I1I6


Current code status: EKV301.02

� EKV3 model code releases:� 301.02: June 2008� 301.01: November 2007 (Available in ELDO, Cadence, Smash)� 301.00: September 2007� 300.02: April 2007� 300.01: October 2006� 300.00: March 2005

� Improvements in 301.01 � 301.02� Enhanced Operating Point Information� Corrected Junction Charges Calculation� Enhanced Width Effect on Overlap Charges� Included DITS Effect on Edge Device� Enhanced Geometric Effects Calculation for Multi-finger RF Devices� Matching Parameters are Model Parameters� Verilog-AMS Related Improvements (Nesting of Internal Functions)


EKV3 Verilog-A code

� The Verilog-A Code of EKV3� Hierarchical Structure

� 18 files� one main file

� many smaller

� In total: ~100KB� Compatible with (at least) ELDO, ADS,

SPECTRE, ADMS, …� Used as the Reference Code for all

Model Implementations� ADMS provides “standard” C-code

Various Simulators.

ekv301.02.va“include statements”

ekv3_extrinsic .va

ekv3_overlap .va

ekv3_gate_current .va

ekv3_noise .va

…


EKV3 implementation status

� EKV3 Verilog-A code compatible with ADMS v2.2.4� Tested with XML Interface for SPICE3� Different XML Interfaces for Different Simulators

� Implementations available for EKV301.01� ELDO (Mentor Graphics)� Spectre (Cadence)� Smash (Dolphin Integration)� ADS (Agilent)

� Tiburon Interface used for actual EKV3 design kits.� GoldenGate.


Developments in EKV3.1

� More flexible mobility modeling of short-channel transistors.� Improved modeling of output conductance of long-channel

halo-implanted devices.� Improved vertical/lateral Non-Uniform Doping.� Extended accounting for layout-dependent stress effects. � Noise model enhancements.

� Improved Accounting for carrier heating/velocity saturation in induced gate noise.

� Refined scaling of 1/f noise model equations & parameters.

� Statistical aspects / device matching.� Refined matching models for ID� Accounting for IG current matching


EKV3 summary

�EKV3: a design-oriented, charge-based, compact model for analog/RF IC design.� Implementations in ELDO (Mentor), Smash (Dolphin), Spectre

(Cadence), ADS/GoldenGate (Agilent).� Parameter extraction support (GMC Suisse & AdMOS)

�Relation to advanced analog/RF IC design.� Characterization methods based on design needs.� Small-signal characterization method vs. IC & L.� Pinch-off voltage method.� Simple model structure & parameter extraction.� Example validations on 110nm, 90nm CMOS.� Extensions in EKV3.1: emphasis on RF, noise, and advanced

technology scaling aspects.


Acknowledgments

� All EKV Team, esp.� François Krummenacher, Christian Enz, Jean-

Michel Sallese, Ananda Roy� Antonios Bazigos for code development &

support� Wladek Grabinski, for Web-site and Verilog-A

support

� Contact: Prof. Matthias BucherElectronics LaboratoryTechnical University of Crete73100 Chania, Crete, Greecephone: +30 28210 37210fax: +30 28210 37542bucher `at` electronics.tuc.grhttp://www.electronics.tuc.grhttp://www.rfic.tuc.gr


Recent references on EKV3

� M. Bucher, A. Bazigos, S. Yoshitomi, N. Itoh, “A Scalable Advanced RF IC Design-Oriented MOSFET Model“, Int. Journal of RF and Microwave Computer Aided Engineering, Vol. 18, N°4, pp. 314-325, 2008.

� M. Bucher, A. Bazigos, “An Efficient Channel Segmentation Approach for a Large-Signal NQS MOSFET Model“, Solid-State Electronics, Vol. 52, N°2, pp. 275-281, February 2008 (DOI: 10.1016/j.sse.2007.08.015).

� A. Bazigos, M. Bucher, P. Sakalas, M. Schroter, W. Kraus, “High-frequency Compact Modelling of Si-RF CMOS“, accepted, Phys. Status Solidi (c), Current Topics in Solid State Physics.

� S. Yoshitomi, A. Bazigos, M. Bucher, “The EKV3 Model Parameter Extraction andCharacterization of 90nm RF-CMOS Technology“, 14th Int. Conf. on Mixed Design of IntegratedCircuits and Systems (MIXDES'2007), (available on ieeexplore) pp. 74-79, Ciechocinek, Poland, June 21-23, 2007.

� A. Bazigos, M. Bucher, F. Krummenacher, J.-M. Sallese, A.-S. Roy, C. Enz, “EKV3 Compact MOSFET Model Documentation, Model Version 301.01“, Technical Report, Technical Universityof Crete, November 23, 2007.

� C. Enz, E. Vittoz, “Charge-based MOS Transistor Modeling, The EKV model for low-power and RF IC design”, ISBN 978-0-470-85541-6, Wiley, 2006.

� M. Bucher, A. Bazigos, F. Krummenacher, J.-M. Sallese, C. Enz, “EKV3.0: An Advanced ChargeBased MOS Transistor Model”, in W. Grabinski, B. Nauwelaers, D. Schreurs (Eds.), TransistorLevel Modeling for Analog/RF IC Design, pp. 67-95, ISBN 1-4020-4555-7, Springer, 2006.

� J.-M. Sallese, M. Bucher, F. Krummenacher, P. Fazan, “Inversion Charge Linearization inMOSFET Modeling and Rigorous Derivation of the EKV Compact Model”, Solid-State Electronics, Vol. 47, pp. 677-683, 2003.

Documents

EKV3 MOSFET Model Status, Analog/RF Capabilities, and