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Ultra Low Voltage Analog RF
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Designing Analog and RFCircuits for Ultra-low Supply
Voltages
Peter Kinget
COLUMBIA UNIVERSITY IN THE CITY OF NEW YORK
© Peter Kinget 12
Thick oxide VDD
Thin oxide VDD
Thin oxide VT
Technology node [nm]
[ITRS'05]
–O– High Perf.
–!– Low Standby
–V– Low Power
Nano CMOS : Supply Voltage
© Peter Kinget 13
Ultra-low Voltage Analog/RF
• What analog/RF is possible in core nanoscaledigital?
• Scavenging applications– E.g., single solar cell VDD 0.4-0.5V
• Ultra-low energy digital systems– Optimal DVDD is 0.3-0.5V
– Analog support functions for digital
• SOC designs– Analog/RF powered from on-chip LDO
– AVDD is 0.2V below DVDD
• Interesting research…– Explore boundaries, develop design techniques
© Peter Kinget 14
MOST Biasing: CS or VCCS
• Transconductor or Current SourceVDS > 0.15 V (for VGS-VT ! 0.2 V)
• Moderate to Strong Inversion(VGS-VT) ! 0.15 V & VT = 0.15V ! VGS = 0.3V
Weak
Inversion
Strong
Inversion
5!T
© Peter Kinget 15
Ultra-LV Challenges in OTAs
CMFB
Vin+ Vin-Vout+ Vout-
Vcasp Vcasp
VcasnVcasn
0.5V
0.25V0.25V"" "
""
"0.15V
0.15V0.15V
0.15V
0.15V
0.3V0.15V
0.15V
0.3V
© Peter Kinget 16
Device Level
• RSCE
• Forward Body-Bias
VT! as L"
deep n-wellNMOS
VDD
VBS=0.5V "VT~ -50mV
© Peter Kinget 17
0.5 V Gate-input OTA stage
Vin+ Vin-
Vout+Vout-
VbnVNR
0.5 V
© Peter Kinget 18
0.5 V OTA in 0.18um CMOS
© Peter Kinget 19
On-chip biasing circuits
Vbn
generating circuit
Level shift biasing circuit
(Simplified OTA)
© Peter Kinget 20
Error amplifier for biasing
• 20 kHz GBW for 1 pF load
• 2 !A current
• Controlled body voltage
sets the amplifier threshold
Vin
Vout
Vo
ut [V
]
Vin [V]
© Peter Kinget 21
OTA DC transfer characteristicsand VNR generation
VNR
generating circuit
Replica of OTA
stage 1
Input differential voltage [mV]
Outp
ut diff voltage [V
]
Increasing VNR
© Peter Kinget 22
Open loop performance (meas.)G
ain
[d
B]
42 dB
GBW: 10 MHz
CL= 10 pF (diff.)
RL= 50 k"
IDD= 150 µA
62 dB 350 mV; automatic bias
Frequency [Hz]
© Peter Kinget 23
Low-voltage tunable integrator
0.25 V0.25 V
0.4 V
+
-V
inV
out
+
-
VDD
VDD
© Peter Kinget 24
0.5 V Fully integrated 5th order LPF
• Operation at 0.45 V to 0.6 V
• 1.1 mW power dissipation
• 57 dB dynamic range
Filter PLL
Biasing circuits
OTAs
1mm
1m
mFrequency [kHz]
Gain
[dB
]
[Chatterjee, ISSCC05,
JSSC05]
© Peter Kinget 25
Performance summary at 27C
727285104VCO feed-thru @280kHz [!V rms]
69.0
150.5
84.5
148.0
88.0
154.5
96.5
153.0
Tuning range [kHz] Vtune
= VDD
Vtune
= 0.0 V
58575755Dynamic range [dB]
5353Out-of-band IIP3 [dBV]
-3-3-3-5In-band IIP3 [dBV]
50505050Input [mV rms] (100kHz / 1% THD)
65687487Noise [!V rms]
4.33.32.21.5Total current [mA]
135.0135.0135.0135.0-3 dB cut-off frequency [kHz]
0.600.550.500.45VDD
[V]
Functionality tested from 5C to 85C at 0.5 V
• Measured CMRR (10 kHz common mode tone): 65 dB
• Measured PSRR (10 kHz tone on power supply): 43 dB
© Peter Kinget 26
0.5V 1Msps 60dB T/H amplifier
• 0.25!m CMOS
• |Vt|= 0.6V
• 60dB SNDR
• 1Msps
• 0.6mA at 0.5VTrack-and-holds
Biasing circuits
• True low voltage
• No clk boosting
• [Chatterjee, VLSI 06, JSSC07]Input amplitude [dBV]
SN
DR
© Peter Kinget 27
0.5V Differential Track and Hold
•Gate-input OTA used.
•Track phase during #1,
hold phase during #2.
•During track phase, pole
and zero cancel out to
enable fast response.
•pMOS switches have VT
of about 0.5V.
© Peter Kinget 28
Track mode operation
• Resistors to 0.5Vmaintain requiredOTA input CMvoltage of 0.4V.
• To enable betterswitching, both gateand body of theswitch are used.
• No voltage swing oneither side of theswitches.
© Peter Kinget 29
Hold mode operation
• Gate and body of theswitch used forbetter switching.
• No signal swing onboth sides of theswitches.
• OTA input voltagesheld constant.
© Peter Kinget 30
Measured SNDR
Input differential rms [dBV]
SN
DR
[dB
]
© Peter Kinget 31
Measured performance
3.9MHzTrack mode bandwidth
0.8mVPedestal on diff. output
7.6"V/"VHold mode droop rate on diff. output
57dBPeak SNDR fIN=495kHz; Vin,diff=100mVRMS
60dBPeak SNDR fIN=50kHz; Vin,diff=178mVRMS
188"VRMSDiff. input refd. integrated noise
1MspsSampling rate
600"ACurrent consumption
0.5VPower supply
© Peter Kinget 32
0.5 V 74 dB SNDR 25kHz !" Modulator
•0.18 !m CMOS
•MIM caps
•Triple-well devices
•High-res resistors
•Body-input, gate-
clocked logic
•Return-to-open
feedback
• [Pun, Chatterjee,
Kinget, ISSCC 06]
© Peter Kinget 33
Digital
Output
Q
Q
+
Vin
-
#DAC
3rd order CT !" Modulator
Using Active RC integrators
#DAC
© Peter Kinget 34
Digital
Output
Q
Q
+
Vin
-
#DAC
3rd order CT !" Modulator
Using Active RC integrators
#DAC
Using Body-Input OTAs (2stages)
Vin+
Vin-
Vout+
Vout-
0.5 V
© Peter Kinget 35
Digital
Output
Q
Q
+
Vin
-
#DAC
3rd order CT !" Modulator
Using Active RC integrators
#DAC
LatchPre-Amp
VDD
+Vin -Vin
Q
!
! !
!
! !
Q
M1 M2 M5 M6
M4M3
M8M7
Gate-clocked Body-input Comparator
© Peter Kinget 36
Digital
Output
Q
Q
+
Vin
-
#DAC
3rd order CT !" Modulator
Using Active RC integrators
#DAC
© Peter Kinget 37
RZ Challenge: Switches at VDD/2
0.25 V
0.25 V
0.25 V
0.5V 0V
RZ DAC_n
0.5V 0V
RZ DAC_p
Ri
C
CRdac
Rdac
VCM
!RZ
D0 D1
VCM
!RZD1 D0
+Vin 0.25 V
Switch Conductance
0.5V
0VTs
Vdac
t
v2
v1
Vcm,ota
V1
V2
© Peter Kinget 38
Ts t
D0
Ts t
Q
Ts t
D1
Solution: Return-to-Open
v2
0.5V
0VTs
Vdac
t
v2
v1
Vcm,ota
v1
When RZ:
(Q=1)
Ri
C
CRdac
Rdac
0.5V 0V
D0 D1
0.5V 0V
D1 D0
RTO DAC_n
RTO DAC_p
+Vin
RZ
Problem
switches
removed
0.25 V
© Peter Kinget 39
Ts t
D0
Ts t
Q
Ts t
D1
Solution: Return-to-Open
v2
0.5V
0VTs
Vdac
t
v2
v1
Vcm,ota
v1
When RZ:
(Q=1)
Ri
C
CRdac
Rdac
0.5V 0V
D0 D1
0.5V 0V
D1 D0
RTO DAC_n
RTO DAC_p
+Vin
RZVREFN
VREFP
"DAC
Q VDACp
"DAC
"DAC
Problem
switches
removed
© Peter Kinget 40
Return-to-open CT SDM
BW = 25kHz, fs = 3.2MHz,
Vin,max = 1Vppdiff.
Split Return-to-open DAC
Only switches to VDD or VSS
Digital
Output
R2ap
(88k$ )
C2p
(7.8pF)
R2an
(88k$)
C2n
(7.8pF)
R2bn
(145k$)
R2bp
(145k$ )
R3ap
(66k$)
C3p
(5.2pF)
R3an
(66k$)
C3n
(5.2pF)
R3bn
(93k$)
R3bp
(93k$ )
!
Q
Q
!DAC
!DAC
!DAC
!DAC
R1ap
(275k$ )
C1p
(31.25pF)
R1an
(275k$)
C1n
(31.25pF)
R1bn
(86k$)
R1bp
(86k$ )
+
Vin
-
!DAC
!DAC
© Peter Kinget 41
Performance Summary at 25°C
0.6 mm2Active die area
370 µW
300 µW
70 µW
0.8V0.5V0.45VSupply Voltage
76 dB
74 dB
0.18 µm CMOS
(standard VT, triple-well, MIM, and HiRes Poly)
76 dB
71 dB
1 Vppdiff.
3.2 MHz / 64
25 kHz
1-bit, 3rd order, continuous-time
74 dB
74 dB
Technology
Power consumption (total)
Sigma Delta Modulator
Output buffers
SNR @ Vin = 1Vppdiff.
SNDR @ Vin = 1Vppdiff.
Input range
Sampling frequency / OSR
Signal bandwidth
Modulator type
© Peter Kinget 46
Recent Work in 90nm CMOS
0.65/0.5V 2.4-2.6GHz Fractional N
Freq. Synthesizer
0.5V 2.4GHz Sliding-IF Receiver + I/Q Baseband
0.5V 10Msps 8bit Pipelined ADC
© Peter Kinget 47
0.65V/0.5V 2.4-2.6GHzFractional-N Synthesizer
• Swings on all VCO nodes arekept within the supply rails forreliability.
• Forward body bias to enhancethe divider speed.
• Fractional-N DSM ditheringshifted to later divider stages toprevent noise injection intoforward biased body.
• Staggered clock to preventjittering caused by simultaneousswitching.
• 90nm CMOS
• [S. Yu & P. Kinget, ISSC07]
© Peter Kinget 49
Performance Summary
Ph
ase n
ois
e (
dB
c/H
z)
Frequency (MHz)
Co
ntr
ol w
ord
–!– @10kHz
–"– @1MHz
–#– @3MHz
$ ctrl word
• AVDD 0.5V - 2.5mW
• DVDD 0.65V - 3.5mW
• 0.14mm2 - 90nm CMOS
• RVT devices
• 2.4-2.6GHz
• Phase noise:-120dBc/Hz @ 3MHz
• Spurs: -52dBc
© Peter Kinget 50
A 0.5V 8bit 10Msps Pipelined ADCin 90nm CMOS
• No internal voltage or clock boosting
• Regular devices
• Cascaded sampling technique toreduce the channel leakage of theswitches
• 1.5bit/stage (remark: stages identical, stages
scaling not exploited)
• Front-end S/H amplifier eliminated bywith an S/H for the sub-ADC.
• 0.5V OTAs with local CMFB
• 90nm CMOS
• [J. Shen & P. Kinget, VLSI07]
© Peter Kinget 53
A 0.5V 2.4GHz Receiver
• ISM band applications
• Sliding IF topology
• LNA, Mixers, VGA +on chip RF, IF & BBfiltering
[Stanic, Balankutty,Kinget, Tsividis,RFIC07]
© Peter Kinget 58
0.5V Analog Roadmap
2004 2005 2006
Body-input
OTA
Gate-input
OTA & Biasing
0.5V Varactor
10b 1Ms
THA
135kHz LPF
+ Tuning
CT 74dB 25kHz
#$ A/D
2007
DT $# ADC
Basic blocks
Co
mp
lexit
y
Comparators
2.4GHz RCV
2.4GHz Synth.
8b 10Ms A/D
90nm
180nm
250nm
900MHz RF
Front-end
© Peter Kinget 59
Where do we go from here…
• Other nanoscale challenges:– Gate & subthreshold (OFF) leakage,
– Smaller gm/go,
– Reduced body effect.
• Opportunities– Device speed significantly improves:
• Scale device operating points for larger (gm/ID),
– FinFETs, dual gate devices, ….
– Calibrate using abundant digital gates.
• But, some fundamental limitations areagainst us…
© Peter Kinget 60
!
P " 8 kT f SNR2
!
v2n,RMS =
kT
C
!
SNR =VRMS
vn,RMS2
!
IDC = 2 f C 2VRMS
Power Dissipation Limits
!
P " 24 CoxAVT2
f Acc2
!
" 2(Vos) =CoxAVT
2
C
!
Acc =VRMS
3" (Vos)
!
IDC = 2 f C 2VRMS
• Noise limited circuits [Vittoz90]:
• Mismatch limited circuits [Kinget96]:
!
VDD = 2 2VRMS
ideal class B
© Peter Kinget 61
Low Voltage Power Penalty
• Finite VDSsat:VDSsat
!
Penalty factor =1+2VDSsat
(VDD " 2VDSsat )
!
VDD = 2 2VRMS + 2VDSsat
© Peter Kinget 62
LV Challenge: Interfaces
50#
CKT
0.5 - 1.0V4dBm (2.5mW) @ 1.0Vpp
-2dBm (0.625mW) @ 0.5Vpp
Z
Transf.
Filt./Z
Match
CKT
50#
out
in
© Peter Kinget 63
Ultra Low Voltage Analog DesignTechniques
• Device Level:– Use body terminal for bias control or signal,
– Use RSCE, optimize L to reduce VT.
• Building Block Level:– Eliminate transistor stacks,
– Use LCMFB, CMFF & Neg. G.
• Functional Level:– Revise signaling & architecture,
– New tuning & biasing strategies.
• Demonstrated in 0.5V analog & RF buildingblocks & systems:– filters, THA, ADCs, RF front-ends, freq. synthesizers,
– in 0.18um CMOS (|VT|=VDD) & 90nm CMOS.
© Peter Kinget 64
Selection of Recent Publications0.5V Analog/RF Integrated Circuits:• S. Chatterjee, K.P. Pun, N. Stanic, Y. Tsividis and P. Kinget, “Analog Circuit Design Techniques at 0.5V”, Springer, in press, 2007.• J. Shen, and P. Kinget, "A 0.5V 8bit 10Msps Pipelined ADC in 90nm CMOS," IEEE Symposium on VLSI circuits, accepted, June 2007.• N. Stanic, A. Balankutty, P. Kinget, and Y. Tsividis,"A 0.5 V Receiver in 90 nm CMOS for 2.4GHz Applications," IEEE Radio Frequency
Integrated Circuits Conference (RFIC), accepted, June 2007.• S.A. Yu and P. Kinget, "A 0.65V 2.5GHz Fractional-N Frequency Synthesizer in 90nm CMOS" in Digest of Technical Papers IEEE
International Solid-State Circuits Conference (ISSCC), Feb. 2007.• S. Chatterjee, and P. Kinget, "A 0.5-V 1-Msps Track-and-Hold Circuit with 60-db SNDR," IEEE Journal of Solid-State Circuits, vol. 42, no.
4, pp. 722-729, Apr. 2007.• K.P. Pun, S. Chatterjee, and P. Kinget, "A 0.5-V 74-dB SNDR 25-kHz Continuous-Time Delta-Sigma Modulator with a Return-to-Open
DAC," IEEE Journal of Solid-State Circuits, Vol. 42, no 3, pp. 496-507, March 2007.• N. Stanic, P. Kinget and Y. Tsividis, “A 0.5 V 900 MHz Receiver Front End”, IEEE Symposium on VLSI Circuits, June 2006.• S. Chatterjee, Y. Tsividis and P. Kinget, "0.5 V Analog Circuit Techniques and Their Application in OTA and Filter Design," IEEE Journal of
Solid-State Circuits, vol. 40, no 12, pp. 2373 - 2387, Dec. 2005.
RF Integrated Oscillators:• B. Soltanian, H. Ainspan, W. Rhee, D. Friedman and P. Kinget, "An Ultra Compact Differentially Tuned 6 GHz CMOS LC VCO with
Dynamic Common Mode Feedback", IEEE Journal of Solid-State Circuits, in press, 2007.• B. Soltanian, and P. Kinget, "A Low Phase Noise Quadrature LC VCO Using Capacitive Common-Source Coupling", European Solid-State
Circuits Conference, pp. 436-439, Sept. 2006• F. Zhang and P. Kinget, "Design of Components and Circuits Underneath Integrated Inductors" IEEE Journal of Solid-State Circuits, vol.
41, no. 10, pp. 2265-2271, Oct. 2006.• B. Soltanian and P. Kinget, “AM-FM Conversion by the Active Devices in MOS LC-VCOs and its Effect on the Optimal Amplitude”, IEEE
RFIC Symposium, June 2006.• B. Soltanian and P. Kinget, " Tail Current-Shaping to Improve Phase Noise in LC Voltage Controlled Oscillators " IEEE Journal of Solid-
State Circuits, vol. 41, no. 8, pp. 1792-1802, Aug. 2006.
Ultra-wideband Pulse Radio:• Tien-Ling Hsieh, P. Kinget, Ranjit Gharpurey, "An Approach to Interference Detection for Ultra Wideband Radio Systems", Fifth IEEE
Dallas Circuits and Systems Workshop, pp. 91-94, Oct. 2006.• F. Zhang and P. Kinget, "Low Power Programmable Gain CMOS Distributed LNA" IEEE Journal of Solid-State Circuits, vol. 41, no 6, pp.
1033-1043, June 2006.• A. Jha, R. Gharpurey and P. Kinget, "Quadrature-DAC based pulse generation for UWB pulse radio transceivers" in Digest of Technical
Papers IEEE International Symposium on Circuits and Systems, pp. 666-669, May 2006.
Injection-locking:• G. Gangasani and P. Kinget, "A time-domain model for predicting the injection locking bandwidth of non-harmonic oscillators" in
Transactions on Circuits and Systems II, pp. 1035-1038, Oct. 2006.• G. Gangasani and P. Kinget, "Injection-Lock Dynamics in Non-Harmonic Oscillators" in Digest of Technical Papers IEEE International
Symposium on Circuits and Systems, pp. 1675-1678, May 2006.
Device Mismatch:• P. Kinget, "Device mismatch and Tradeoffs in the Design of Analog Circuits", IEEE Journal of Solid-State Circuits, vol. 40, no 6, pp. 1212-
1224, June 2005.
© Peter Kinget 65
Acknowledgments
• Collaborators:– Y. Tsividis (Columbia), K. P. Pun (City Univ. Hong
Kong), S. Chatterjee (now IIT Delhi), B. Soltanian(now LSI)
– A. Balankutty, Y. Feng, A. Jha, J. Shen, N. Stanic,S. Yu, F. Zhang.
• Analog Devices, Bell Labs, Intel, NSF,Realtek, Silicon Labs, SRC for financialsupport.
• Europractice, Philips (now NXP) and UMC forfabrication support.
Thank you for your attention
Any Questions, contact:
http://www.ee.columbia.edu/~kinget