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MOSFET
n+n+
p-substrate
DSG
B
VGS
+
-
Depletion
Region
n-channel
MOSFET
NMOS
0 0.5 1 1.5 2 2.50
1
2
3
4
5
6x 10
-4
VDS (V)
I D(A
)
VGS= 2.5 V
VGS= 2.0 V
VGS= 1.5 V
VGS= 1.0 V
Resistive Saturation
VDS = VGS - VT
NMOS
-2.5 -2 -1.5 -1 -0.5 0-1
-0.8
-0.6
-0.4
-0.2
0x 10
-4
VDS (V)
I D(A
)
Assume all variablesnegative!
VGS = -1.0V
VGS = -1.5V
VGS = -2.0V
VGS = -2.5V
PMOS
Tecnologia CMOS (1/2)
Tecnologia CMOS (2/2)
Processo CMOS Dual-Well
p-well n-well
p+
p-epi
SiO2
AlCu
poly
n+
SiO2
p+
gate-oxide
Tungsten
TiSi2
Vin Vout
CL
VDD
Funzionamento dell’inverter CMOS
Threshold Drops
VDD
VDD 0
0 VDD
CL
CL
VDD
0 VDD - VTn
CL
VDD
VDD
VDD |VTp|
CL
S
D S
D
VGS
S
SD
D
VGS
Funzionamento dell’inverter CMOS
Funzionamento dell’inverter CMOS
Caratteristica di trasferimento
Vin
= VDD
+VGSp
IDn
= - IDp
Vout
= VDD
+VDSp
Vin = V DD +VGSp
IDn = - I Dp
Vout = V DD +VDSpVin = V DD +VGSp
IDn = - I Dp
Vin = V DD +VGSp
IDn = - I Dp
Vout = V DD +VDSpVout = V DD +VDSp
Vout
CMOS Inverter VTC
VDD
F(In1,In2,…InN)
In1In2
InN
In1In2
InN
PUN
PDN
PMOS only
NMOS only
PUN e PDN sono reti logiche duali
Static CMOS
CMOS Properties
