Mos Mosfet Operation

8/10/2019 Mos Mosfet Operation

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MOS capacitor operation


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Energy bands of a crystal

In a single atom, electrons occupy discreteenergy levels

What happens when a large number of atoms

are brought together to form a crystal?


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Permitted energy levels - Silicon


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Valence and conduction bands

A and Bmetal

Csemiconductor or insulator


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Semiconductor and insulator

Distinction between insulator and semiconductor

Based on the value of the energy gap Semiconductors

Room-temperature thermal energy or excitation fromvisible-light photons can give electrons enough energyfor "jumping" from the valence into the conduction

band Energy gap of 1.12 eV (silicon), 0.67 eV (germanium),

and 1.42 eV (gallium arsenide)

Insulators Insulators have significantly wider energy bandgaps

Room temperature thermal energy is not large enoughto place electrons in the conduction band

9.0 eV (SiO2), 5.47 eV (diamond), and 5.0 eV (Si3N4)


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Fermi level in semiconductor and insulator

In an insulator or a semiconductor, we know that

the valence band is full of electrons, and the

conduction band is empty at 0 K

Therefore, the Fermi level lies somewhere in thebandgap, between ECand EV

In a metal, the Fermi level lies within an energy

band


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Understanding electron and hole concept


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In this water analogy, A drop of water - an electron

A bubble or absence of water - a hole

Hence, a hole is equivalent to a missing electron inthe crystal valence band A hole is not a particle and it does not exist by itself

It draws its existence from the absence of an

electron in the crystal, just like a bubble in a pipeexists only because of a lack of water

Holes can move in the crystal through successive"filling" of the empty space left by a missing electron

The hole carries a positive charge +q, as theelectron carries a negative charge q (q=1.6x1019Coulomb)


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Density of states and Fermi probability


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Intrinsic semiconductor

A semiconductor is said to be "intrinsic" if thevast majority of its free carriers (electrons andholes) originate from the semiconductor atomsthemselves

In that case if an electron receives enoughthermal energy to "jump" from the valence bandto the conduction band, it leaves a hole behindin the valence band

Every hole in the valence band corresponds toan electron in the conduction band, and thenumber of conduction electrons is exactly equalto the number of valence holes, p=n=ni


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niversus temperature


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Extrinsic semiconductor

The silicon used in the semiconductor industryhas a purity level of 99.9999999%

One can, however, intentionally introduce in

silicon trace amounts of elements which areclose to silicon in the periodic table, such asthose located in columns III (boron) or V(phosphorus, arsenic)

If, for instance, an atom of arsenic is substitutedfor a silicon atom, it will form four bonds bysharing four electrons with the neighboringsilicon atoms


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Donor impurity

A Arsenic atom introduces an extra electron in crystal

An electron is released by Arsenic atom and it moves

freely in the crystal


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Jump of an electron from donor energy level (Ed)


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Introduction of a donor atom in silicon

Donor atoms phosphorus (P) or arsenic (As)

Gives rise to a permitted energy level in thebandgap Located a few meV below the bottom of the

conduction band

At very low temperature contains the electrons whichcan be given by the impurity atoms to the crystal

At room temperature these electrons possess enoughthermal energy (equal to kT/q = 25.6 meV) to breakfree from the impurity atoms and move freely in thecrystal or, in other words, it can "jump" from the

energy level introduced by the impurity into theconduction band

When an electron moves away from a donoratom, such as arsenic (As), the atom becomes

ionized and carries a positive charge, +q (referprevious figure)


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Acceptor impurity

A Boron atom introduces a missing electron in crystal

A hole is released by boron atom and it moves

freely in the crystal


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Introduction of an acceptor atom in silicon

Acceptor atom - boron (B)

Gives rise to a permitted energy level in thebandgap This level is located a few meV above the top of the

valence band

At room temperature electrons in the top of the valenceband possess enough thermal energy to "jump" into theenergy levels created by the impurity atoms (or: valenceelectrons are "captured" by acceptor atoms), which givesrise to holes in the valence band.

These holes are free to move in the crystal

When an electron is captured by an acceptor atom,a hole is thus released in the crystal, and theacceptor atom (boron) becomes ionized andcarries a negative charge, -q (refer previous figure)


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Main elements used in semiconductor

technology


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Classes of semiconductors

Intrinsic: no= po = ni

n-type: no> po, since Nd> Na

p-type: no< po, since Nd< Na

Compensated: no=po=ni, w/ Na- = Nd

+> 0

Note: n-type and p-type are usually partially

compensated since there are usually some

opposite- type dopants


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Charge neutrality under thermodynamic

equilibrium

Electron and hole concentration in N type

semiconductor

Electron and hole concentration in P type

semiconductor

da NpNn

d

id

N

npandNn

2

a

i

a

N

nnandNn

2


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Position of the Fermi Level

Efiis the Fermi level

when no= po (often

denoted as Ei )


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Calculation of Fermi levelN Type

semiconductor

Calculation of Fermi potentialN Type

semiconductor

F=Ei-EF=Fermi potential


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Calculation of Fermi levelP Type

semiconductor

Calculation of Fermi potentialP Type

semiconductor

F=Ei-EF=Fermi potential


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Fermi levels in P and N type semiconductors


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P-N junction


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Depletion region in P-N junction


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Band diagram for

p+-n jctn* at Va= 0

EcEfNEfi

Ev

Ec

EfPEfi

Ev

0 xnx

-xp-xpc xnc

qp < 0

q

n> 0

qVbi= q(n -p)

*Na> Nd-> |p|> np-type for x0


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Drift Current

The drift current density (amp/cm2) is

given by the point form of Ohm Law

J= (nqmn

+pqmp

)(Ex

i+ Ey

j+ Ez

k), so

J= (sn+ sp)E=sE, where

s= nqmn+pqmpdefines the conductivity

The net current is

SdJI


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Drift current resistance (cont.)

Consequently, since

R = rl/A

R = (nqmn+ pqmp)-1

(l/A) For n >> p, (an n-type extrinsic s/c)

R = l/(nqmnA)

For p >> n, (a p-type extrinsic s/c)R = l/(pqmpA)


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MOSFET or IGFET


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N-channel MOS transistor


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MOSFET with gate voltage zero

The gate voltage is equal to zero while the P-type

substrate and the source are grounded The drain is connected to a positive voltage

Since the source and the substrate are at thesame potential there is no current flow in the

source-substrate junction The drain-substrate junction is reverse biased and

except for a small negligible reverse leakagecurrent no current flows in that junction either

Under these conditions there is no channelformation, and therefore, no current flow fromsource to drain.


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MOSFET current vs voltage characteristics

MOS (M t l O id


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MOS (Metal-Oxide-

Semiconductor)

Assume work function of metal and

semiconductor are same.


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MOS materials


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The ideal two-terminal MOS structure

(VFB=0)

CG s

ox

QV

C

oxox

ox

AC

t

;G ox oxG ox

ox

Q CQ C

A A t

A- capacitor area,

tox- oxide thickness

ox-permittivity of oxide

M

OS

+

s

_

GG s

ox

QV

C

CQ

GQ

0G CQ Q

GV


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Example: oxide capacitance(a) Calculate the oxide capacitance per unit area for

tox= 5 and 20 nm assuming ox= 3.90, where 0=

8.8510-14F/cm is the permittivity of free space. (b)

Determine the area of a 1pF metal-oxide-metal

capacitor for the two oxide thicknesses given in

(a).

Answer: (a) =690 nF/cm2= 6.9 fF/mm2for tox=5 nm

and = 172 nF/cm2= 1.7 fF/mm2for tox= 20 nm. The

capacitor areas are 145 and 580 mm2for oxide

thicknesses of 5 and 20 nm, respectively.


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MOS structure

Shown is the semiconductor substrate with a thin oxide layerand a top metal contact, also referred to as the gate.

A second metal layer forms an Ohmic contact to the back of the

semiconductor, also referred to as the bulk. The structure shown has a p-type substrate.

We will refer to this as an n-type MOS capacitorsince theinversion layer contains electrons.
http://ece-www.colorado.edu/~bart/book/book/chapter6/ch6_2.htm


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Structure and principle of operation

To understand the different bias modes of anMOS we consider 3 different bias voltages.

(1) below the flatband voltage, VFB

(2) between the flatband voltage and thethreshold voltage, VT, and

(3) larger than the threshold voltage.

These bias regimes are called the

accumulat ion , deplet ionand invers ion modeof operation.

St t d i i l f


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Structure and principle of

operation

Charges in a MOS structure under accumulation,

depletion and inversion conditions


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Schematic illustration of a generic field effect

transistor

This device can beviewed as a combinationof two orthogonal two-terminal devices

MOS it


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MOS capacitor

Two-terminalsemiconductor device

A metal contactseparated from thesemiconductor by adielectric insulator

Utilizes doped silicon asthe substrate and itsnative oxide, silicondioxide, as the insulator

Siliconsilicon dioxide system, the density of surface states at the oxide

semiconductor interface is very low compared to thetypical channel carrier density in a MOSFET.

Insulating quality of the oxide is quite good


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MOS capacitor

The thickness of the oxide

typically varies between 5

to 50 nm

The semiconductor

chosen for the example isP-type silicon, which

corresponds to the

substrate of an n-channel

device

Assume work functions

are same


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Accumulation

Negative bias is applied to the metalgate while the silicon substrate isgrounded Structure behaves like a parallel-plate

capacitor where the two electrodes are

the silicon and the metal, and the oxide isthe insulator between them.

The application of the bias gives riseto a negative charge on the gate This is a surface charge in the metal,

located at the metaloxide interface An equal charge of opposite sign

appears at the surface of the silicon, atthe silicon-oxide interface


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Accumulation layer

The charge in the

silicon can also be

considered a surface

charge Its thickness is

approximately 10

nanometers

This thin, hole-richlayer is called an

accumulation layer

Depletion


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Depletion

Small positive bias is applied

to the gate Holes near the silicon surface

are repelled by the gate.

Because the acceptor doping

atoms cannot move in thesilicon lattice a negativecharge appears underneaththe gate oxide Similarly a positive charge of

equal magnitude can be foundin the gate electrode, at themetal-oxide interface


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Depletion layer The gate charge is a surface

charge, but the charge in thesilicon is not

Depletion charge extends to a

non-negligible depth into thesilicon

The depth up to which holes

are repelled is called the

depletion depth (xd)

Inversion


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Inversion

If a larger positivevoltage is applied to

the gate the surfacepotential will continueto increase The hole concentration

near the surfacedecreases while theelectron concentrationincreases, accordingto the following

relationships:

Inversion layer


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Inversion layer

Electron surface concentration = Hole surface concentration

when Eicoincides with EF.This happens S= F=(KT/q) ln (Na/ni)

Regions of operation of the MOSFET:


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g p

Accumulation (p-substrate)

Holes + accumulate in

the p-type semiconductor

surface

0

0

GB FB

C

s

V V

Q

+ + + + + + + + + + + + + +VGB

G

B

- - - - - - - - - - -

+ + + +

Qo

QG

QC



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VGB

G

B

+ + + + + + + + +

+ + + +

Qo

QG

--- -

--

- -

-

QC- -- -

-

F = Fermi potential (defined in p-n

junction lecture i.e. Ei-EF)

0

0

GB FB

C

s F

V V

Q

Holes evacuate from the P

semiconductor surface and

acceptor ion charges

become uncovered

-

g p

Depletion (p-substrate)



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VGB

G

B

+ + + + + + + + +

+ + + +

Qo

QG

--- -

--- -

-

QC- -- -

--- - -

--

-

-

-

0

GB FB

C

s F

V VQ

electrons approach thesurface!

g p

Inversion (p-substrate)


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Band diagrams in semiconductor


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Weak inversion and strong inversion

weak inversion:

b< s< 2b

Strong inversion:

s=2b Flat band condition:

s=0

Accumulationcondition:

s < 0

Depletion:

0 < s < b T


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Charges in semiconductor

Charge ers s band bending/s rface


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Charge versus band bending/surface

potential in semiconductor


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Threshold voltage

Consider P type substrate

Suppose you want to invert a region in that

substrate (two step process)

Remove the holes in that region by puttingelectrons

No. of holes doping concentration (Ei-EF)

Put some more electrons in that region

How many more electrons doping concentration

(Ei-EF)


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Threshold voltage

Threshold voltage V = VT, corresponding to the

onset of the strong inversion

Strong inversion occurs when the surface

potential sbecomes equal to 2b


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In a MOS transistor thegate voltage is equal to

sum of the potential drops

in the semiconductor and

the oxide

Where F=(KT/q) ln (Na/ni)


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Poly gate

We have so far assumed that the Fermi level ofthe metal gate was equal to that of the silicon. In

practice this is not the case

In modern devices the gate material is not anactual metal, but heavily doped polycrystalline

silicon, also called poly silicon

The doping concentration used for that material

is so high (1020/cm3) that it can be considered asa metal, for all practical purposes.


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Work function difference

Energy which isnecessary to extract

an electron with an

energy from the

metal is called the

"work function M

Similarly, the work

function in thesemiconductor is

noted SC

Band diagram for p-n junction


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Band diagram for p-n junction

EcEfNEfi

Ev

Ec

EfPEfiEv

0 xnx

-xp-xpc xnc

qp < 0

qn > 0

qVbi= q(n -p)

*Na> N

d-> |

p|>

np-type for x0


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Electron affinity and work function

Eo

EcEf Ei

Ev

q (electronaffinity)

qF

q(work function)

Eo

Ec

EfEiEv

q (electronaffinity)

qF

q(work function)

P type semiconductor N type semiconductor


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MOS capacitorband diagram

If work functions are not same i.e. if metals

work function is smaller than substrate

S = XS + (EC - EF)

Flat band voltage (VFB)


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g ( FB)

At zero applied voltage, thebending of the energy bands isideally determined by thedifference in the work functionsof the metal and thesemiconductor

This band bending changeswith the applied bias and thebands become flat when weapply the so-called flat-bandvoltage (VFB)

VFB =(M - S)/q

=(M-XS - EC + EF)/q


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MOS-Accumulation region

Charge carriers same as that of substrate typegetting accumulated near Si-SIO2interface

A MOS structure with ap-type semiconductor

will enter the accumulation regime of operation

when the voltage applied between the metal andthe semiconductor is more negative than the flat-

band voltage

If VFBis +0.5 V then accumulation region is below

+0.5 V

If VFBis -0.25 V then accumulation region is below

-0.25 V

MOS depletion region


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MOS depletion region

Assume MOS structure with ap-type substrate

When V >VFB, the semiconductoroxide

interface first becomes depleted of holes and we

enter the so-called depletion regime


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MOSinversion region

For sufficiently larger voltages than VFB, wefinally arrive at a situation in which the electronvolume concentration at the interface exceedsthe doping density in the semiconductor

This is the strong inversion case in which wehave a significant conducting sheet of inversioncharge at the interface

Charges in the oxide


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g

Oxides grown on silicon contain positivecharges due to the presence of contaminatingmetallic ions or imperfect Si-O bonds

These charges can either be fixed or mobile inthe oxide

Mobile ions such as sodium and potassium canmove in the presence of an electric field if thetemperature is high enough


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The charge in the

silicon can be removedif an appropriate

negative voltage is

applied to the gate

If the charge is closer tothe semiconductor a

larger compensation

bias on the gate is

required to remove the

charge in the

semiconductor

Interface traps


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p

Presence of Si-SiO2 interface at the silicon surfaceintroduces perturbation to the periodic crystalstructure of the semiconductor Causes some Si-Si bonds to be unfulfilled or "dangling"

As a result there are energy states in the band gapat the silicon surface These states are called "interface states" or "interface

traps

They can be charged positively or negatively,depending on their nature and their energy withrespect to the Fermi level, and thus, will affect thesurface potential

To compensate for these charges, a bias must beapplied to the gate


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Flat band voltage-non idealities

Non idealities

Work function difference

Charge in the oxide

Interface states


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Depletion and enhancement devices


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Depletion and enhancement devices

Threshold voltage (VTH) can be either positive ornegative, depending on Doping concentration (Na)

Material used to form the gate electrode, etc

For a n-channel MOSFET if the thresholdvoltage is negative - depletion-mode device

positive, the device is an enhancement-mode device

C t lli V


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Controlling VTH

Depletion-mode devices will have an inversionlayer when the gate voltage is equal to zero These devices are sometimes referred to as "normally

on".

Enhancement-mode devices require an appliedpositive gate voltage to create the inversionlayer They are sometimes called "normally off"

VTHcan be adjusted by introducing a controlledamount of doping impurities in the channelregion during device fabrication

MOS it


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MOS capacitance

In a MOS capacitor, the metal contact and theneutral region in the doped semiconductor

substrate are separated by the insulator layer,the channel, and the depletion region

Capacitance Cmosof the MOS structure can be

represented as a series connection of the

insulator capacitance Ci= Si/di, where S is the

area of the MOS capacitor, and the capacitanceof the active semiconductor layer Cs

M i it


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Measuring capacitance

DC bias

low-frequencyac signal

C it i l ti


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Capacitance in accumulation

When the gate voltage

is negative an

accumulation layer is

present

As the gate voltagevaries a corresponding

variation of the

accumulation charge

occurs, and thecapacitance of the

structure is equal to Cox

areaFaradCt

C OXOX

OX /

Capacitance is

independent

of gate voltage

C it i d l ti


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Capacitance in depletion

When the gate voltage isincreased the siliconsurface becomesdepleted, and thevariations of gate voltageinduce variations of thedepletion charge

The value of thecapacitance is thengiven by the seriescombination of the gateand depletion regioncapacitances

Capacitance decreases

with gate voltage

C it i i i


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Capacitance in inversion

As the gate voltage is further increased aninversion layer is formed and variations of gate

voltage give rise to variations of inversion

charge and thus the measure capacitance is

again equal to COX

areaFaradCt

C OXOX

OX /

Capacitance is

independent

of gate voltage

MOS capacitorcapacitance as a functionof gate bias


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of gate bias

Small-signal equivalent circuit of the MOS


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g q

capacitor

Main approximation for compact MOS


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pp p

modeling: the charge-sheet model

Minority carriers occupy a zero-thicknesslayer at

the Si-SiO2interface

(EF-Ei) factor


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Positive for n type,

negative for p type

and zero for intrinsic

In other words,

if (EF-Ei) is positive

then in that region wehave more no. of

electrons

if (EF-Ei) is negative

then in that region we

have more no. of holes

If EF=Ei, then no, of

holes = no. of

electrons



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weak inversion:

b< s< 2b

Strong inversion:

s=2b

Flat band condition:s=0

Accumulationcondition:

s < 0

Depletion:

0 < s < b T


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Mos Mosfet Operation