More Digital circuits

Ripple Counter

• The most common counter• The problem is that,

because more than one output is changing at once, the signal is glichy

• To avoid this problem, use Gray or Johnson code

Johnson Counter

• The Johnson counter is type of shift counter

• Put an inverted MSB back to LSB

• Glitch output free

Johnson Counter with error recovery

Linear Feedback Shift Registers

• A small number of taps are recycled

• An LFSR can operate at high speed compared to a binary counter because the feedback logic is very simple

• Reduce clock noise

Many-to-One LFSR

Many-to-One LFSR

Maximal length LFSR

• With maximal length logic (taps selected to give

the maximal count),a small number

of register can create sequence up to 2n-1

Divide by N LFSR Counter

• An example of the use of a LFSR

• A terminal count is provided as an input to be compared to

Divide by N LFSR Counter

• Test fixture

4-Bit LFSR One-to-Many Code

• One-to-Many variant splits the XOR into 2-input gates and distributes them throughout the register array

Cyclic Redundancy Checksums

• Error detection• The data packet is

looked at as a huge binary number

• A polynomial divide this number in GF

• Reminder is checksum

Cyclic Redundancy Checksums

ROM

• ROM stands for Read-Only Memory• This memory is initialized when

the FPGA is configured and cannot be changed after configuration

ROM Version of LFSR

• We can implement four-bit LFSR counter with a ROM

RAM

• RAM stands for Random Access Memory

• A RAM is an array of cells, addressable in groups N element wide and M elements deep

RAM

RAM

• Unless the FPGA support embedded RAM blocks, it will consume a huge amount of logic

FPGA with embedded RAM

256x8 RAM Implemented in the 4000XL Device Family

Dual port RAM

• Jovan Popovic jocapc@panet.co.yu• Milos Milovanovic miloshm@yahoo.com• Veljko Milutinovic vm@galeb.etf.bg.ac.yu• Nobelovac?