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CS224: Computer Organization S.KHABET

CHAPTER1:

Digital Logic CircuitsCombination Circuits

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PRIMITIVE LOGIC GATES

• Each of our basic operations can be implemented in hardware using a primitive logic gate.

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Logic gate:

AND (product)of two inputs

OR (sum) of two inputs

NOT (complement)on one input

Operation:

xy, or xy x + y x’Expression:

x y xy

0 0 0

0 1 0

1 0 0

1 1 1

x y x + y

0 0 0

0 1 1

1 0 1

1 1 1

x x’

0 1

1 0

Truth table:

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ADDITIONAL LOGIC GATES

x y (xy)’

0 0 1

0 1 1

1 0 1

1 1 0

x y (x+y)’

0 0 1

0 1 0

1 0 0

1 1 0

NAND(NOT-AND)

NOR(NOT-OR)

XOR(eXclusive OR)

(xy)’ = x’ + y’ (x + y)’ = x’ y’ x y = x’y + xy’

Operation:

Expressions:

Truth table:

Logic gates:

x y xy

0 0 0

0 1 1

1 0 1

1 1 0

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(xy)’(x + y)’ x y

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ADDITIONAL LOGIC GATES

XNOR GATE

• Finally, the complement of the XOR function is the XNOR function.

• A two-input XNOR gate is true when its inputs are equal:

x y (xy)’

0 0 1

0 1 0

1 0 0

1 1 1

(x y)’ = x’y’ + xy

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Expression:

Truth table:

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LOGIC GATES PROPERTIES

• OR GATE– 0 + x = x– 1 + x = 1– x + x’ = 1

• AND GATE – 1 . x = x– 0 . x = 0– x . x’ = 0

• XOR GATE– x 0 = x – x x = 0 – x 1 = x’– x x’ = 1– x (y z) = (x y) z [ Associative ]

– x y = y x [ Commutative ]

The NAND and the NOR gates are universal: they can replace all other gates!

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THE FUNDAMENTAL THEOREMS 0FBOOLEAN ALGEBRA

1. x + 0 = x 2. x 1 = x Identity

3. x + 1 = 1 4. x 0 = 0 Domination

5. x + x = x 6. x x = x Idempotence

7. x + x’ = 1 8. x x’ = 0 Complement

9. (x’)’ = x Double complement

10. x + y = y + x 11. xy = yx Commutative 12. x + (y + z) = (x + y) + z 13. x(yz) = (xy)z Associative 14. x(y + z) = xy + xz 15. x + yz = (x + y)(x + z) Distributive 16. (x + y)’ = x’y’ 17. (xy)’ = x’ + y’ De Morgan’s

The left and right columns of theorems are duals

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SOME MORE LAWS

• Here are some more useful laws. Notice the duals again!

• We can prove these laws by either

– Making truth tables

– Using the axioms

1. x + xy = x 4. x(x + y) = x 2. xy + xy’ = x 5. (x + y)(x + y’) = x 3. x + x’y = x + y 6. x(x’ + y) = xy

xy + x’z + yz = xy + x’z (x + y)(x’ + z)(y + z) = (x + y)(x’ + z)

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FUNCTION SIMPLIFICATION

• We can do some simplifications to find an equivalent Boolean expression which is more simple than the original one by using two possible methods

– Algebraic Manipulation: By using Boolean algebra properties.

– Map Simplification : By using Karnaugh maps.

f(x,y,z) = x’y’ + xyz + x’y= x’(y’ + y) + xyz * Distributive; x’y’ + x’y = x’(y’ + y) += x’1 + xyz [ Axiom 7; y’ + y = 1 ]= x’ + xyz [ Axiom 2; x’1 = x’ += (x’ + x)(x’ + yz) [ Distributive ]= 1 (x’ + yz) [ Axiom 7; x’ + x = 1 ]= x’ + yz [ Axiom 2 ]

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STANDARD FORMS OF EXPRESSIONS

• We can write expressions in sum of products (SOP) or in product of sums (POS)

• A sum of products (SOP) expression contains:

– Only OR (sum) operations at the “outermost” level

– Each term that is summed must be a product of literals

– A SOP expression can be implemented with NAND gates

• A product of sums (POS) expression contains:

– Only AND (product) operations at the “outermost” level

– Each term must be a sum of literals

– A POS expression can be implemented with NOR gates

f(x,y,z) = y’ + x’yz’ + xz

f(x,y,z) = y’ (x’ + y + z’) (x + z)

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SUM OF MINTERMS FORM

• Every function can be written as a sum of minterms, which is a special kind of sum of products form

• The sum of minterms form for any function is unique

x y z f(x,y,z) f’(x,y,z)

0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 1 0 0 0 1 1 0 1 0 1 1 1 0 1 0 1 1 1 0 1

f = x’y’z’ + x’y’z + x’yz’ + x’yz + xyz’= m0 + m1 + m2 + m3 + m6

= m(0,1,2,3,6)

f’ = xy’z’ + xy’z + xyz= m4 + m5 + m7

= m(4,5,7)

f’ contains all the minterms not in f

•The symbol ∑ stands for sum of minterms that follow in parenthesis.

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PRODUCT OF MAXTERMS FORM• Every function can be written as a unique product of maxterms

• The product of maxterms form for any function is unique

x y z f(x,y,z) f’(x,y,z)

0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 1 0 0 0 1 1 0 1 0 1 1 1 0 1 0 1 1 1 0 1

f = (x’ + y + z)(x’ + y + z’)(x’ + y’ + z’)= M4 M5 M7

= M(4,5,7)

f’ = (x + y + z)(x + y + z’)(x + y’ + z)(x + y’ + z’)(x’ + y’ + z)

= M0 M1 M2 M3 M6

= M(0,1,2,3,6)

f’ contains all the maxterms not in f

• The symbol stands for product of maxterms that follow in parenthesis.

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MINTERMS AND MAXTERMS ARE RELATED

• Any minterm mi is the complement of the corresponding maxterm Mi

• For example, m4’ = M4 because (xy’z’)’ = x’ + y + z

Maxterm Shorthandx + y + z M0

x + y + z’ M1

x + y’ + z M2

x + y’ + z’ M3

x’ + y + z M4

x’ + y + z’ M5

x’ + y’ + z M6

x’ + y’ + z’ M7

Minterm Shorthandx’y’z’ m0

x’y’z m1

x’yz’ m2

x’yz m3

xy’z’ m4

xy’z m5

xyz’ m6

xyz m7

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CONVERTING BETWEEN STANDARD FORMS

• We can convert a sum of minterms to a product of maxterms

• In general, just replace the minterms with maxterms, using maxterm numbers that don’t appear in the sum of minterms:

• The same thing works for converting from a product of maxterms to a sum of minterms

From before f = m(0,1,2,3,6)and f’ = m(4,5,7)

= m4 + m5 + m7

complementing (f’)’ = (m4 + m5 + m7)’so f = m4’ m5’ m7’ * DeMorgan’s law +

= M4 M5 M7 [ By the previous page ]

= M(4,5,7)

f = m(0,1,2,3,6)

= M(4,5,7)

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COMBINATIONAL CIRCUITS

• Circuits made up of gates, that don’t have any feedback, are called combinatorial circuits (combinational)

• A combinational circuit is a connected arrangement of logic gates with a set of inputs and outputs.

• At any given time the binary values of the outputs are a function of the inputs.

• Combinational circuits are used in computers for

– generating binary control decisions

– and for providing digital components for data processing.

Combinational Circuit

n input variables m output variables

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COMBINATORIAL CIRCUITSCIRCUIT ANALYSIS

• Steps to analyze a combinational circuit1. Identify inputs and outputs2. Draw the truth table (the number of rows depends on the number of

inputs)3. Show how the outputs change for each set of inputs4. You may need intermediate results if the circuit is complicated5. Find its function if necessary

• Example : Analyze the following combinational circuit

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COMBINATORIAL CIRCUITSCIRCUIT DESIGN

• The goal of circuit design is to build hardware that computes some given function.

• The basic idea is to write the function as a Boolean expression, and then convert that to a circuit.

• Steps to design a combinational circuit

1. The problem is stated

2. The inputs and outputs are assigned letter symbols

3. The truth table that defines the relationships between inputs and outputs is derived

4. The simplified Boolean functions for each output are obtained

5. The diagram is drawn

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CIRCUIT DESIGNHalf Adder (HA)

• A Half Adder adds two bits and produces a two-bit result: a sum (the right bit) and a carry out (the left bit).

• Here are:

• But remember that it’s binary: for example, 1 + 1 = 10 .

X Y C S

0 0 0 0

0 1 0 1

1 0 0 1

1 1 1 0

C = XY

S = X’ Y + X Y’= X Y

truth table equations circuit block symbol

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CIRCUIT DESIGN

Full Adder (FA)

• A full adder circuit takes three bits of input, and produces a two-bit output consisting of a sum and a carry out.

• Using Boolean algebra (or K-maps), we get the equations shown here

(XOR operations simplify the equations a bit).

S = m(1,2,4,7)= X’ Y’ Cin + X’ Y Cin’ + X Y’ Cin’ + X Y Cin

= X’ (Y’ Cin + Y Cin’) + X (Y’ Cin’ + Y Cin)= X’ (Y Cin) + X (Y Cin)’= X Y Cin

Cout = m(3,5,6,7)= X’ Y Cin + X Y’ Cin + X Y Cin’ + X Y Cin

= (X’ Y + X Y’) Cin + XY(Cin’ + Cin)= (X Y) Cin + XY

X Y Cin Cout S

0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1

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CIRCUIT DESIGN

Full Adder Circuit

• It is called Full Adder because it can be builded by putting together two half adders!

S = X Y Cin

Cout = (X Y) Cin + XY

Hardware repetition simplifies hardware design

block symbol

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CIRCUIT DESIGNParallel Adders : A 4-BIT ADDER

• Used to add 2 numbers in the parallel form

• Produce the Sum bits as parallel outputs.

• Four full adders together make a 4-bit adder.

• Total inputs are : Two 4-bit numbers and initial carry in, CI

• Outputs are: A 4-bit sum, S3 S2 S1 S0 and a carry out, CO

block symbol

block diagram of a 4-bit Adder

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CIRCUIT DESIGN

A two’s complement Subtractor

• To find A - B with an adder, we’ll need to:– Complement each bit of B.– Set the adder’s carry in to 1.

• The net result is A + B’ + 1, where B’ + 1 is the two’s complement negation of B.

• Remember that A3, B3 and S3 here are actually sign bits.

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CIRCUIT DESIGNAn Adder-Subtractor circuit

• When Sub = 0, the XOR gates output B3 B2 B1 B0 and the carry in is 0. The adder output will be A + B + 0, or just A + B.

• When Sub = 1, the XOR gates output B3’ B2’ B1’ B0’ and the carry in is 1. Thus, the adder output will be a two’s complement subtraction, A - B.

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DECODER

• Combinational circuit that takes an n-bit input and produces 2n outputs.

The n inputs represent a binary number that determines which of the 2n

outputs is uniquely true

• A 2-to-4 decoder operates according to the following truth table.

– The 2-bit input is called S1S0, and the four outputs are A0-A3.

– If the input is the binary number i, then output Ai is uniquely true.

– This circuit “decodes” a binary number into a “one-of-four” code.

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A 2-TO-4 DECODER

Logic diagram

S1 S0 Q0 Q1 Q2 Q3

0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 0 1 0 1 1 0 0 0 1

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ENABLE INPUTS

• Many devices have an additional enable input, which is used to “activate” or “deactivate” the device.

• Decoder may include one or more enable inputs to control the circuit operation

• The enable input may be activated with a 0 or 1 signal.

• If it is activated with a 1 signal– E=1, decoder enabled (activated), so it behaves as specified earlier.

Exactly one of the outputs will be 1.– E=0, decoder disabled (deactivated), By convention, that means all of

the decoder’s outputs are 0.

• Decoders which contains more than one enable input satisfy a given logic condition in order to enable the circuit

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A 2 TO 4 LINES DECODERWITH ENABLE INPUT

•EN=1 decoder enabled.Exactly one of the outputswill be 1.

• EN=0 decoder disabled.All of the decoder’s outputs are 0 regardless of inputs A1 and A0.

Abbreviate truth table

Logic diagram

EN

A1

A0

D0

D1

D2

D3

Decoder Block Diagram

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DECODER BLOCK DIAGRAM

• A decoder block provides abstraction:

– You can use the decoder as long as you know its truth table or equations, without knowing exactly what’s inside.

– It makes diagrams simpler by hiding the internal circuitry.

– It simplifies hardware reuse. You don’t have to keep rebuilding the decoder from scratch every time you need it.

• These blocks are like functions in programming!

Q0 = S1’ S0’Q1 = S1’ S0Q2 = S1 S0’Q3 = S1 S0

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BLOCKS SYMBOLS AND APPLICATIONS

• Used to encapsulate common circuits like decoders.

• Treated as an individual entity.

• Block diagrams for 2-to-4 decoders.

• A decoder block provides abstraction:

– You can use the decoder as long as you know its truth table or equations, without knowing exactly what’s inside.

– It makes diagrams simpler by hiding the internal circuitry.

– It simplifies hardware reuse. You don’t have to keep rebuilding the decoder from scratch every time you need it.

• These blocks are like functions in programming!

• Decoders can be used to implement arbitrary functions

• A common decoder application is the decoding of address lines for memory chips. Decoders are largely used in memorization circuits

Q0 = S1’ S0’Q1 = S1’ S0Q2 = S1 S0’Q3 = S1 S0

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A 3-TO-8 DECODER

A2 A1 A0 D0 D1 D2 D3 D4 D5 D6 D7

0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 1

•Larger decoders are similar. Here is a 3-to-8 decoder.

•Again, only one output is true for any input combination.

A0 = S2’ S1’ S0’

A1 = S2’ S1’ S0

A2 = S2’ S1 S0’

A3 = S2’ S1 S0

A4 = S2 S1’ S0’

A5 = S2 S1’ S0

A6 = S2 S1 S0’

A7 = S2 S1 S0

Truth table without EN Output equations

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A 3-TO-8 DECODER

Block diagram

Logic diagram

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DECODER EXPANSION

• Usefulness of enable input in combinational logic components.

• Enable inputs are convenient feature for interconnecting two or more circuits for the purpose of expanding the digital components.

• Only one decoder is activated at a special moment.

• Here’s a 3-to-8 decoder constructed from two 2-to-4 decoders

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DECODER EXPANSION

Active Ouput

S0S1S2

QO000

Q1100

Q2010

Q3110

Q4001

Q5101

Q6011

Q7111

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A VARIATION OF THE STANDARD DECODER

• Active-high decoders.

• Active-high decoders generate minterms

• Active-low decoder (inverted EN input and inverted outputs).

• An active-low decoders generate maxterms.

EN’ S1 S0 Q0 Q1 Q2 Q3

0 0 0 0 1 1 1 0 0 1 1 0 1 1 0 1 0 1 1 0 1 0 1 1 1 1 1 0

1 x x 1 1 1 1

EN S1 S0 Q0 Q1 Q2 Q3

0 x x 0 0 0 0

1 0 0 1 0 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 0 1 1 1 0 0 0 1

Q3 = S1S0 = m3

Q2 = S1S0’ = m2

Q1 = S1’ S0 = m1

Q0 = S1’S0’ = m0

Q3’= S1’+S0’ = M3

Q2’= S1’+S0 = M2

Q1’= S1+S0’ = M1

Q0’= S1+S0 = M0

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ENCODER

• An encoder performs the opposite function of a decoder

• A binary encoder encodes information (data) from 2n inputs into an n-bit

code (output)

– Exactly one of the inputs should have a value of one

– The outputs represent the binary number that identifies which input is

equal to 1

• Encoders reduce the number of bits needed to represent given

information

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ENCODER TRUTH TABLE

The encoder can be implemented with OR gates whose inputs are determined directly from the truth table

D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0 Valeur

0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 1 0 0 0 1 0 2 0 0 0 0 1 0 0 0 0 1 1 3 0 0 0 1 0 0 0 0 1 0 0 4 0 0 1 0 0 1 0 0 1 0 1 5 0 1 0 0 0 0 1 0 1 1 0 6 1 0 0 0 0 0 0 1 1 1 1 7

Truth table for Octal to Binary Encoder

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MULTIPLEXER

• A 2n-to-1 multiplexer sends one of 2n input lines to a single output line. – A multiplexer has two sets of inputs:

• 2n data input lines• n select lines, to pick one of the 2n data inputs

– The mux output is a single bit, which is one of the 2n data inputs.

• Selection of a particular line is controlled by a set of selection variables or control lines.

• Selects binary information from one of many input lines.• The other input lines are cut off.• The multiplexer is also called a data selector.

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MULTIPLEXER

• The simplest example is a 2-to-1 mux:

• The select bit S controls which of the data bits D0-D1 is chosen:

– If S=0, then D0 is the output (Q=D0).

– If S=1, then D1 is the output (Q=D1).

Q = S’ D0 + S D1

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A 4-TO-1 MULTIPLEXER

EN S1 S0 Y

1 0 0 D0 1 0 1 D1 1 1 0 D2 1 1 1 D3

0 x x 1

block diagram and abbreviated truth table for a 4-to-1 mux

Y= S1’S0’D0 + S1’S0 D1 + S1S0’D2 + S1S0D3

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A 4-TO-1 MULTIPLEXER

Logic diagram

S0 and S1 are selection inputs.They are decoded to select a particular AND gate

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IMPLEMENTING FUNCTIONS WITH MULTIPLEXERS

• Muxes can be used to implement arbitrary functions.

• One way to implement a function of n variables is to use an n-to-1 mux:

– For each minterm mi of the function, connect 1 to mux data input Di. Each data input corresponds to one row of the truth table.

– Connect the function’s input variables to the mux select inputs. These are used to indicate a particular input combination.

• For example, let’s look at f(x,y,z) = m(1,2,6,7).

x y z f

0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 1 1 1 1 1

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EXPANSION AND APPLICATIONS

• Multiplexer may have one or more enable input.

• The enable input may also be used for multiplexers expansion.

• Time-sharing computers multiplex the input from users terminals

• Used to deserialize information