Texas Instruments Incorporated

ModulModul 8: 8: AnalognoAnalogno DigitalniDigitalni KonvertorKonvertor

Digital Signal ControllerTMS320F2833x

8 8 -- 11

Texas Instruments Incorporated

ADC ADC ModulModuluu 1212--bitna bitna rezolucijarezolucijauu Šesnaest ulaznih kanal sa naponskim opsegom Šesnaest ulaznih kanal sa naponskim opsegom 0…3V0…3Vuu RelacijaRelacija::

ww VVinin = Analog= Analognini ulazni naponulazni napon, , opsegopseg 0…3V0…3Vww VVref+ref+ = 3.0V V= 3.0V Vrefref-- = 0V n = 12 = 0V n = 12 ww D = digitalD = digitalnini rerezultatzultat, 12 Bit, 12 Bitnana rerezolucijazolucija

(1

)2

REF REFin REFn

D V VV V+ −−

∗ −= +

−

8 8 -- 22

ww D = digitalD = digitalnini rerezultatzultat, 12 Bit, 12 Bitnana rerezolucijazolucijauu MaMaksimalna brzina konverzijeksimalna brzina konverzije: 12.5 MSPS (80 ns): 12.5 MSPS (80 ns)uu DvaDva analoganalognana ulazna ulazna multiplemultiplekseraksera / / dva SH koladva SH kolauu SeSekvencijalno i simultano odmeravanjekvencijalno i simultano odmeravanjeuu Auto seAuto sekvenciranjekvenciranje –– do do 16 auto 16 auto konverzijakonverzijauu Šesnaest Šesnaest individualindividualnono adresabadresabilnihilnih registregistara za rezultatara za rezultatuu Izvori triger signala za Izvori triger signala za startstart--ofof--conversionconversion

ww External trigger, S/W or ePWM External trigger, S/W or ePWM -- ModulModulii

ADC reADC režimi radažimi rada

uu Režim rada sekvenceraRežim rada sekvencera::uu Redni (Kaskadni Redni (Kaskadni –– Cascaded) režimrežim (16 (16 stastanjanja))uu DualDualni rad sekvencerani rad sekvencera (2 x 8 (2 x 8 stastanjanja))

uu Režim odmeravanjaRežim odmeravanja::uu Sekvencijalno odmeravanje Sekvencijalno odmeravanje (1 (1 kanal u tenutkukanal u tenutku))

8 8 -- 33

uu Sekvencijalno odmeravanje Sekvencijalno odmeravanje (1 (1 kanal u tenutkukanal u tenutku))uu SimultanoSimultano odmeravanjeodmeravanje (2 (2 kanala istovremenokanala istovremeno))

uu Režim startovanjaRežim startovanja::uu Režim jedne sekvenceRežim jedne sekvence (stop (stop na kraju sekvencena kraju sekvence))uu Kontinualni radKontinualni rad ((wrapwrap na kraju sekvencena kraju sekvence) )

ADC SeADC Sekvencerkvencer CascadedCascaded režimurežimu

1212--bit A/Dbit A/DConverterConverter

SOCSOC EOCEOC

ADCINA0ADCINA0ADCINA1ADCINA1

ADCINA7ADCINA7

ADCINB0ADCINB0ADCINB1ADCINB1

ADCINB7ADCINB7

S/HS/HAA

S/HS/HBB

MU

XM

UX

MUXMUXAA

RESULT0RESULT0RESULT1RESULT1RESULT2RESULT2

RESULT15RESULT15

ResultResultMUXMUX

MUXMUXBB

AutosequencerAutosequencerSEQ1SEQ1

8 8 -- 44

SoftwareSoftwareePWM_SOC_AePWM_SOC_AePWM_SOC_BePWM_SOC_B

Ch Sel (CONV00)Ch Sel (CONV00)Ch Sel (CONV01)Ch Sel (CONV01)Ch Sel (CONV02)Ch Sel (CONV02)Ch Sel (CONV03)Ch Sel (CONV03)

Ch Sel (CONV15)Ch Sel (CONV15)

MAX_CONV1MAX_CONV1

AutosequencerAutosequencer

Start SequenceStart SequenceTriggerTrigger

ADC fullADC full--scale scale input range is 0 input range is 0

to 3V to 3V

External PinExternal Pin(GPIO/XINT2_ADCSOC)(GPIO/XINT2_ADCSOC)

SOC SOC -- Start Of ConversionStart Of ConversionEOC EOC -- End Of ConversionEnd Of Conversion

ADC SeADC Sekvencerkvencer uu dualnom radudualnom radu

RESULT8RESULT8RESULT9RESULT9

ResultResult

RESULT0RESULT0RESULT1RESULT1

RESULT7RESULT7

ResultResultMUXMUX1212--bit A/Dbit A/D

ConverterConverter

S/HS/HAA

S/HS/HBB

MU

XM

UX

SOC1/SOC1/EOC1EOC1

SequencerSequencerArbiterArbiter

SOC2/SOC2/EOC2EOC2

ADCINA0ADCINA0ADCINA1ADCINA1

ADCINA7ADCINA7

ADCINB0ADCINB0ADCINB1ADCINB1

ADCINB7ADCINB7

MUXMUXAA

MUXMUXBB

MU

XM

UX

Neprekidani reNeprekidani režimžimStart/Stop režimStart/Stop režimSimultani režimSimultani režim

8 8 -- 55

RESULT15RESULT15

ResultResultMUXMUX

SoftwareSoftwareePWM_SOC_AePWM_SOC_A

External PinExternal Pin

EOC1EOC1 EOC2EOC2

SoftwareSoftwareePWM_SOC_BePWM_SOC_B

MUXMUX

Ch Sel (CONV00)Ch Sel (CONV00)Ch Sel (CONV01)Ch Sel (CONV01)

Ch Sel (CONV07)Ch Sel (CONV07)

MAX_CONV1MAX_CONV1

AutosequencerAutosequencer

Start SequenceStart SequenceTriggerTrigger

SEQ1SEQ1

(GPIO/XINT2_ADCSOC)(GPIO/XINT2_ADCSOC)

Ch Sel (CONV08)Ch Sel (CONV08)Ch Sel (CONV09)Ch Sel (CONV09)

Ch Sel (CONV15)Ch Sel (CONV15)

MAX_CONV2MAX_CONV2

AutosequencerAutosequencer

Start SequenceStart SequenceTriggerTrigger

SEQ2SEQ2

Dijagram generisanja taktnog signalaDijagram generisanja taktnog signalaCLKINCLKIN

(30 MHz)(30 MHz)HSPCLKHSPCLK

(150 MHz)(150 MHz)

ADCTRL3ADCTRL3 FCLKFCLK ADCCLKADCCLKADCTRL1ADCTRL1

SYSCLKOUTSYSCLKOUT(150 MHz)(150 MHz)

PLLSTSPLLSTS

DIVSELbits

10b (/2)To CPUTo CPU

PCLKCR0.ADCENCLK = 1PCLKCR0.ADCENCLK = 1

HISPCPHISPCP

HSPCLKbits

000b (/1)000b (/1)

PLLCRPLLCR

DIVDIVbitsbits

1010b (x10)

8 8 -- 66

ADCCLKPS bits

ADCTRL3ADCTRL3

0110b0110b

FCLKFCLK(12.5 MHz)(12.5 MHz)

FCLK = HSPCLK/(2*ADCCLKPS)FCLK = HSPCLK/(2*ADCCLKPS) ADCCLK =ADCCLK =FCLK/(CPS+1)FCLK/(CPS+1)

ADCCLKADCCLK(12.5 MHz)(12.5 MHz)

CPS bit

ADCTRL1ADCTRL1

0b

To ADC To ADC pipelinepipeline

sampling sampling windowwindowACQ_PS

bits

ADCTRL1ADCTRL1

0111bsampling window = (ACQ_PS + 1)*(1/ADCCLK)sampling window = (ACQ_PS + 1)*(1/ADCCLK)

AnalogAnalog--toto--Digital Converter RegistersDigital Converter Registers

ADCTRL1ADCTRL1 ADC Control Register 1ADC Control Register 1ADCTRL2ADCTRL2 ADC Control Register 2ADC Control Register 2ADCTRL3ADCTRL3 ADC Control Register 3ADC Control Register 3ADCMAXCONVADCMAXCONV ADC Maximum Conversion Channels RegisterADC Maximum Conversion Channels RegisterADCCHSELSEQ1ADCCHSELSEQ1 ADC Channel Select Sequencing Control Register 1ADC Channel Select Sequencing Control Register 1ADCCHSELSEQ2ADCCHSELSEQ2 ADC Channel Select Sequencing Control Register 2ADC Channel Select Sequencing Control Register 2ADCCHSELSEQ3ADCCHSELSEQ3 ADC Channel Select Sequencing Control Register 3ADC Channel Select Sequencing Control Register 3ADCCHSELSEQ4ADCCHSELSEQ4 ADC Channel Select Sequencing Control Register 4ADC Channel Select Sequencing Control Register 4

RegisterRegister DescriptionDescription

8 8 -- 77

ADCCHSELSEQ4ADCCHSELSEQ4 ADC Channel Select Sequencing Control Register 4ADC Channel Select Sequencing Control Register 4ADCASEQSRADCASEQSR ADC Autosequence Status RegisterADC Autosequence Status RegisterADCRESULT0ADCRESULT0 ADC Conversion Result Buffer Register 0ADC Conversion Result Buffer Register 0ADCRESULT1ADCRESULT1 ADC Conversion Result Buffer Register 1ADC Conversion Result Buffer Register 1ADCRESULT2ADCRESULT2 ADC Conversion Result Buffer Register 2ADC Conversion Result Buffer Register 2

ADCRESULT14ADCRESULT14 ADC Conversion Result Buffer Register 14ADC Conversion Result Buffer Register 14ADCRESULT15ADCRESULT15 ADC Conversion Result Buffer Register 15ADC Conversion Result Buffer Register 15ADCREFSELADCREFSEL ADC Reference Select RegisterADC Reference Select RegisterADCOFFTRIMADCOFFTRIM ADC Offset Trim RegisterADC Offset Trim RegisterADCSTADCST ADC Status and Flag RegisterADC Status and Flag Register

ADC Control Register 1 ADC Control Register 1

ADC Module ResetADC Module Reset0 = no effect0 = no effect1 = reset (set back to 01 = reset (set back to 0

by ADC logic)by ADC logic)

Acquisition Time Prescale (S/H)Acquisition Time Prescale (S/H)ACQ Window = (ACQ_PS + 1)*(1/ADCCLK)ACQ Window = (ACQ_PS + 1)*(1/ADCCLK)

771515 11 11 -- 8813 13 -- 12121414

Viši deo registraViši deo registra::

8 8 -- 88

Emulation Suspend ModeEmulation Suspend Mode00 = free run (do not stop)00 = free run (do not stop)01 = stop after current sequence01 = stop after current sequence10 = stop after current conversion10 = stop after current conversion11 = stop immediately11 = stop immediately

SUSMODSUSMOD ACQ_PSACQ_PS CPSCPS

77

RESETRESET

1515

reserved

11 11 -- 8813 13 -- 12121414

Conversion PrescaleConversion Prescale0: ADCCLK = FCLK / 10: ADCCLK = FCLK / 11: ADCCLK = FCLK / 21: ADCCLK = FCLK / 2

Struktura promenljive u C: AdcRegs.ADCTRL1

ADC Control Register 1 ADC Control Register 1

Sequencer ModeSequencer Mode0 = dual mode0 = dual mode1 = cascaded mode1 = cascaded mode

Continuous RunContinuous Run0 = stops after reaching 0 = stops after reaching

end of sequence end of sequence 1 = continuous (starts all over1 = continuous (starts all over

again from “initial state”)again from “initial state”)

Niži deo registraNiži deo registra::

8 8 -- 99

Sequencer OverrideSequencer Override(functions only if CONT_RUN = 1)(functions only if CONT_RUN = 1)0 = sequencer pointer resets to “initial state” at end of MAX_CONVn0 = sequencer pointer resets to “initial state” at end of MAX_CONVn1 = sequencer pointer resets to “initial state” after “end 1 = sequencer pointer resets to “initial state” after “end state”state” (7 ili 15)(7 ili 15)

SEQ_OVRDSEQ_OVRD SEQ_CASCSEQ_CASC

3 3 -- 00

CONT_RUNCONT_RUN reserved

445566

Struktura promenljive u C : AdcRegs.ADCTRL1

ADC Control Register 2 ADC Control Register 2

ePWM SOC BePWM SOC B(cascaded mode only)(cascaded mode only)0 = no action0 = no action1 = start by ePWM 1 = start by ePWM

signalsignal

Start Conversion (SEQ1)Start Conversion (SEQ1)0 = clear pending SOC trigger0 = clear pending SOC trigger1 = software trigger1 = software trigger--start SEQ1start SEQ1

ePWM SOC AePWM SOC ASEQ1 Mask BitSEQ1 Mask Bit0 = cannot be started0 = cannot be started

by ePWM triggerby ePWM trigger1 = can be started 1 = can be started

by ePWM triggerby ePWM trigger

Viši deo registraViši deo registra::

8 8 -- 1010

Interrupt Enable (SEQ1)Interrupt Enable (SEQ1)0 = interrupt disable0 = interrupt disable1 = interrupt enable1 = interrupt enable

Reset SEQ1Reset SEQ10 = no action0 = no action1 = immediate reset1 = immediate reset

SEQ1 to “initial state”SEQ1 to “initial state”

Interrupt Mode (SEQ1)Interrupt Mode (SEQ1)0 = interrupt every EOS0 = interrupt every EOS1 = interrupt every other EOS1 = interrupt every other EOS

RST_SEQ1RST_SEQ1

99ePWM_SOCBePWM_SOCB

_SEQ_SEQ

1212reserved

11111515

SOC_SEQ1SOC_SEQ1INT_ENAINT_ENA_SEQ1_SEQ1

INT_MODINT_MOD_SEQ1_SEQ1 reserved

ePWM_SOCAePWM_SOCA_SEQ1_SEQ1

881414 1313 1010

Struktura promenljive u C: AdcRegs.ADCTRL2 EOS EOS –– End Of SequenceEnd Of Sequence

ADC Control Register 2ADC Control Register 2

External SOC (SEQ1)External SOC (SEQ1)0 = no action0 = no action1 = start by signal from1 = start by signal from

ADCSOC pinADCSOC pin

Start Conversion (SEQ2)Start Conversion (SEQ2)(dual(dual--sequencer mode only)sequencer mode only)0 = clear pending SOC trigger0 = clear pending SOC trigger1 = software trigger1 = software trigger--start SEQ2start SEQ2

ePWM SOC BePWM SOC BSEQ2 Mask BitSEQ2 Mask Bit0 = cannot be started0 = cannot be started

by ePWM triggerby ePWM trigger1 = can be started 1 = can be started

by ePWM triggerby ePWM trigger

Niži deo registraNiži deo registra::

8 8 -- 1111

Interrupt Enable (SEQ2)Interrupt Enable (SEQ2)0 = interrupt disable0 = interrupt disable1 = interrupt enable1 = interrupt enable

Interrupt Mode (SEQ2)Interrupt Mode (SEQ2)0 = interrupt every EOS0 = interrupt every EOS1 = interrupt every other EOS1 = interrupt every other EOS

RST_SEQ2RST_SEQ2

11EXT_SOCEXT_SOC

_SEQ1_SEQ1

44reserved

3377

SOC_SEQ2SOC_SEQ2INT_ENAINT_ENA_SEQ2_SEQ2

INT_MODINT_MOD_SEQ2_SEQ2 reserved

ePWM_SOCBePWM_SOCB_SEQ2_SEQ2

0066 55 22

Reset SEQ2Reset SEQ20 = no action0 = no action1 = immediate reset1 = immediate reset

SEQ2 to “initial state”SEQ2 to “initial state”

Struktura promenljive u C : AdcRegs.ADCTRL2

ADC Control Register 3ADC Control Register 3

ADC Bandgap and ADC Bandgap and Reference Power DownReference Power Down00 = powered down00 = powered down11 = powered up11 = powered up

ADC Power DownADC Power Down(except Bandgap & Ref.)(except Bandgap & Ref.)0 = powered down0 = powered down1 = powered up1 = powered up

8 8 -- 1212

Sampling Mode SelectSampling Mode Select0 = sequential sampling mode0 = sequential sampling mode1 = simultaneous sampling mode1 = simultaneous sampling mode

ADC Clock PrescaleADC Clock Prescale00 : FCLK = HSPCLK: FCLK = HSPCLK

1 to F1 to F : FCLK = HSPCLK / (2*ADCCLKPS): FCLK = HSPCLK / (2*ADCCLKPS)

ADCBGRFDNADCBGRFDN ADCCLKPSADCCLKPS SMODE_SELSMODE_SEL

0015 15 -- 88

reserved

4 4 -- 117 7 -- 66

ADCPWDNADCPWDN

55

Struktura promenljive u C : AdcRegs.ADCTRL3

Registar za broj maksimalnih konverzijaRegistar za broj maksimalnih konverzija♦♦ Bitska polja definišu broj konverzija po jednom triger signaluBitska polja definišu broj konverzija po jednom triger signalu (binary+1)(binary+1)

MAX_MAX_CONV 2_2CONV 2_2

MAX_MAX_CONV 2_1CONV 2_1

MAX_MAX_CONV 2_0CONV 2_0

MAX_MAX_CONV 1_3CONV 1_3

MAX_MAX_CONV 1_2CONV 1_2

MAX_MAX_CONV 1_1CONV 1_1

MAX_MAX_CONV 1_0CONV 1_0reserved

Cascaded ModeCascaded Mode

SEQ2SEQ2 SEQ1SEQ1

001122334455661515--77

8 8 -- 1313

♦♦ Svaki sekvencer počinenje sa Svaki sekvencer počinenje sa “Initial state” “Initial state” i uvećava ga sekvencijalnoi uvećava ga sekvencijalno♦♦ Svaki Svaki wrapwrap--uje sa uje sa “end state” “end state” ako ga pre toga nije softver resetovaoako ga pre toga nije softver resetovao

Dual ModeDual ModeSEQ2SEQ2 SEQ1SEQ1

SEQ1SEQ1 SEQ2SEQ2 CascadedCascadedInitial stateInitial state CONV00CONV00 CONV08CONV08 CONV00CONV00End stateEnd state CONV07CONV07 CONV15CONV15 CONV15CONV15

Struktura promenljive u C : AdcRegs.ADCMAXCONV

Regostar za selekciju ulaznih kanalaRegostar za selekciju ulaznih kanala

ADCCHSELSEQ1ADCCHSELSEQ1

15 15 -- 12 11 12 11 -- 8 7 8 7 -- 4 3 4 3 -- 00

CONV03 CONV02 CONV01 CONV00CONV03 CONV02 CONV01 CONV00

ADCCHSELSEQ2ADCCHSELSEQ2 CONV07 CONV06 CONV05 CONV04CONV07 CONV06 CONV05 CONV04

ADCCHSELSEQ3ADCCHSELSEQ3 CONV11 CONV10 CONV09 CONV08CONV11 CONV10 CONV09 CONV08

8 8 -- 1414

CONV11 CONV10 CONV09 CONV08CONV11 CONV10 CONV09 CONV08

ADCCHSELSEQ4ADCCHSELSEQ4 CONV15 CONV14 CONV13 CONV12CONV15 CONV14 CONV13 CONV12

Struktura promenljive u C : AdcRegs.ADCCHSELSEQ1 … AdcRegs.ADCCHSELSEQ4

Ulazni kanali Ulazni kanali ADC ADC broje se binarnobroje se binarno::ADCINA0 = 0000ADCINA0 = 0000 ADCINB0 = 1000ADCINB0 = 1000ADCINA1 = 0001ADCINA1 = 0001 ….….…… ADCINB7 = 1111ADCINB7 = 1111

PrimerPrimer –– SeSekvencer u kvencer u “Start/Stop” “Start/Stop” režimurežimu

ePWMePWMTime BaseTime BaseCounterCounter

ePWMePWMOutputOutput

8 8 -- 1515

Konfiguracioni zahteviKonfiguracioni zahtevi::uu ePWMePWM triggertriggerrujeruje ADCADC

ww TTriri auto auto konverzijekonverzije (V1, V2, V3) (V1, V2, V3) za za trigger 1trigger 1 (CTR = 0)(CTR = 0)ww TTriri auto auto konverzije konverzije (I1, I2, I3) (I1, I2, I3) za za trigger 2trigger 2 (CTR = PRD)(CTR = PRD)

uu Sekvencer u kaskadnom režimu a odmeravanje u Sekvencer u kaskadnom režimu a odmeravanje u sekvencijalnom režimusekvencijalnom režimu

VV11, V, V22, V, V33 II11, I, I22, I, I33 VV11, V, V22, V, V33 II11, I, I22, I, I33

ww MAX_CONV1 MAX_CONV1 postavljen napostavljen na 2 2 a registar za selekciju ulaznih kanala naa registar za selekciju ulaznih kanala na::

ww Nakon reseta i inicijalizacijeNakon reseta i inicijalizacije, SEQ1 , SEQ1 čeka na čeka na trigertrigerww Na prvi Na prvi trigertriger izvršavaju se izvršavaju se trtrii konverzijekonverzije: CONV00 (V1), CONV01 (V2), CONV02 (V3): CONV00 (V1), CONV01 (V2), CONV02 (V3)ww SEQ1 SEQ1 čeka na drugi trigerčeka na drugi trigerww Na drugi triger izvršavaju se konverzijeNa drugi triger izvršavaju se konverzije: CONV03 (I1), CONV04 (I2), CONV05 (I3): CONV03 (I1), CONV04 (I2), CONV05 (I3)

Bits Bits →→ 1515--12 1112 11--8 78 7--4 34 3--00II11 VV33 VV22 VV11 ADCCHSELSEQ1ADCCHSELSEQ1x x Ix x I33 II22 ADCCHSELSEQ2ADCCHSELSEQ2

PrimerPrimer –– SeSekvencer u kvencer u “Start/Stop” “Start/Stop” režimurežimu

8 8 -- 1616

ww Na kraju druge sekvenceNa kraju druge sekvence, , registri za rezultat imaju sledeće vrednostiregistri za rezultat imaju sledeće vrednosti::

ww SEQ1 SEQ1 čeka u tekućem stanju na drugi trigerčeka u tekućem stanju na drugi trigerww ISR ISR čita rezultat i resetuje čita rezultat i resetuje SEQ1SEQ1

RESULT0 VRESULT0 V11

RESULT1 VRESULT1 V22

RESULT2 VRESULT2 V33

RESULT3 IRESULT3 I11RESULT4 IRESULT4 I22RESULT5 IRESULT5 I33

Registri za rezultatRegistri za rezultat konverzijekonverzije

LSBLSBMSBMSB

1515 1414 1313 1212 1111 1010 99 88 77 66 55 44 33 22 11 00

LSBLSBMSBMSB

AdcRegs.ADCRESULTx, x = 0 AdcRegs.ADCRESULTx, x = 0 -- 1515 (2 wait(2 wait--state read)state read)

AdcMirror.ADCRESULTx, x = 0 AdcMirror.ADCRESULTx, x = 0 -- 1515 (0 wait(0 wait--state read)state read)

8 8 -- 1717

InputInput DigitalDigital AdcRegs. ADCRESULTx AdcMirror. ADCRESULTxAdcRegs. ADCRESULTx AdcMirror. ADCRESULTxVoltageVoltage ResultResult

3.03.0 0xFFF0xFFF 1111|1111|1111|00001111|1111|1111|0000 0000|1111|1111|11110000|1111|1111|1111

1.51.5 0x7FF0x7FF 0111|1111|1111|00000111|1111|1111|0000 0000|0111|1111|11110000|0111|1111|11110.000730.00073 11 0000|0000|0001|00000000|0000|0001|0000 0000|0000|0000|00010000|0000|0000|000100 00 0000|0000|0000|00000000|0000|0000|0000 0000|0000|0000|00000000|0000|0000|0000

LSBLSBMSBMSB

1515 1414 1313 1212 1111 1010 99 88 77 66 55 44 33 22 11 00

Odmeravanje bipolarnih signalOdmeravanje bipolarnih signalPrimerPrimer: : --1.5 V1.5 V ≤≤ VVinin ≤≤ +1.5 V+1.5 V

1) 1) Dodavanje Dodavanje 1.5 volt1.5 voltiianaloganalognom ulazunom ulazu

8 8 -- 1818

VV RR

RR RR C28xC28x

Odmeravanje bipolarnih signalOdmeravanje bipolarnih signalPrimerPrimer: : --1.5 V1.5 V ≤≤ VVinin ≤≤ +1.5 V+1.5 V

1) 1) Dodavanje Dodavanje 1.5 volt1.5 voltiianaloganalognom ulazunom ulazu

8 8 -- 1919

VVinin

1.5V1.5V ADCINxADCINx

GNDGND

ADCLOADCLO

--++

RR

RR--++

RRC28xC28x

Odmeravanje bipolarnih signalOdmeravanje bipolarnih signal

#include “DSP2833x_Device.h”#include “DSP2833x_Device.h”#define offset 0x07FF#define offset 0x07FFvoid main(void)void main(void){{

int16int16 value;value; // signed// signed

2) Subtract “1.5” from the digital result2) Subtract “1.5” from the digital result

8 8 -- 2020

value = AdcMirror.ADCRESULT0 value = AdcMirror.ADCRESULT0 –– offset;offset;}}

Izbor referentnog signala Izbor referentnog signala ADCADCuu ADC ADC F28335 F28335 poseduje ugrađeni referentni signal sa poseduje ugrađeni referentni signal sa

temperaturnom stabilnosti temperaturnom stabilnosti ~50 PPM/~50 PPM/°°C *C *uu Mogućnost korišćenja spoljašnje referenceMogućnost korišćenja spoljašnje reference

ww Izbor spoljašnje referenceIzbor spoljašnje reference: 2.048 V, 1.5 V, 1.024 V: 2.048 V, 1.5 V, 1.024 Vww Referenca NE MENJA ulazni opseg pune skaleReferenca NE MENJA ulazni opseg pune skale 0 0 -- 3 V3 V

uu Registar za izbor referentnog signalaRegistar za izbor referentnog signala ADCREFSELADCREFSEL

8 8 -- 2121

13 13 -- 00

reserved15 15 -- 1414

REF_SELREF_SEL

ADC Reference SelectionADC Reference Selection00 = internal (default)00 = internal (default)01 = external 2.048 V01 = external 2.048 V10 = external 1.5 V10 = external 1.5 V11 = external 1.024 V11 = external 1.024 V

Struktura promenljive u C : AdcRegs.ADCREFSEL

Korekcija ofsetaKorekcija ofsetauu Registar ADCOFFTRIM (9Registar ADCOFFTRIM (9--bitno polje bitno polje --256/255) 256/255)

Vrednost sa kojem se rezultat konverzije Vrednost sa kojem se rezultat konverzije sabira/oduzima pre smeštanja u registre za rezultatsabira/oduzima pre smeštanja u registre za rezultat

uu Tajming nije poremećenTajming nije poremećenuu Održanje punog dinamičkog opsegaOdržanje punog dinamičkog opsegauu Sadržaj ADCOFFTRIM registra definiše se u ADC_cal Sadržaj ADCOFFTRIM registra definiše se u ADC_cal

rutini boot ROMrutini boot ROM--aa

8 8 -- 2222

rutini boot ROMrutini boot ROM--aa

Korekcija ofsetaKorekcija ofsetaKonverzija ADCLO

reference~20 konverzija

Neki od rezultata = 0

?

Dodati 40 registruOFFTRIM

8 8 -- 2323

?

Izračunati srednu vrednost svih konv.

Oduzteti srednju vrednost od OFFTRIM

Idealna raspodelaRezultata konverzije