Measurement-Based Extraction of MOSFET Small …...Measurement-Based Extraction of MOSFET Small-Signal Parameters Ragnar Víðir Reynisson Troels Emil Kolding E-mail: {rvr,tek}@kom.auc.dk

Technical Report R2000-1004ISSN 0908-1224

Measurement-Based Extraction ofMOSFET Small-Signal Parameters

August 2000

Ragnar Víðir ReynissonTroels Emil KoldingE-mail: rvr,[email protected]

RF Integrated Systems & Circuits (RISC) group,Institute of Electronic Systems,Aalborg University,Niels Jernes Vej 12-A6,DK-9220 Aalborg,Denmark.

Measurement-Based Extraction ofMOSFET Small-Signal Parameters

Ragnar Víðir ReynissonTroels Emil Kolding

E-mail: rvr,[email protected]

Abstract

In this report, a parameter extraction procedure and a model presented in [4] are testedusing a 280×0.25µm transistor manufactured in a 0.25 µmCMOS process. The extractionprocedure is based on two sets of S-parameter measurements. The first transistor mea-surement is in the linear region, to obtain the extrinsic terminal resistances which are bias-independent . The intrinsic parameters of the transistor are found using measurements ofthe transistor in saturation. The gate-drain and gate-source capacitances, along with thegate/ back-gate transconductances and output conductance are extracted directly. Theseare subsequently deembedded from the measurements to obtain the bulk admittance. Fi-nally, the source-bulk and drain-bulk capacitances and the bulk resistance network are op-timized to fit the measurements. The method compares favourably with measurements,apart from the estimate of the gate-resistance, which is too high. By replacing this withthe gate-resistance estimate in [5], the fit improves significantly. The channel delay factorincluded in the model is necessary to model forward transmission accurately at higher fre-quencies.

THE extraction of small-signal parameters of MOSFETs is of great interest to RF circuit de-signers. However, as the MOSFET is influenced by bulk effects at gigahertz frequencies,

direct measuring-based extraction is quite complicated. In a recent paper [4], an approach wassuggested which links common-source MOSFET measurements to a small-signal RF modelwhich is valid up to the cutoff frequency. While a quasi-static assumption does not hold tofrequencies above fT/3 [9], the proposed method increases the the scope of applicability byintroducing a delay in conjunction with the transconductance. For recent submicron CMOSprocesses (sub-0.25µm) this should give a valid frequency range up to around 8-12GHz whichis sufficient in many situations. In this report, the proposed extraction procedure is describedand it’s applicability is demonstrated by use of MOSFETs fabricated in a 0.25µm CMOS tech-nology.

1 BASIC MODEL DESCRIPTION

The employed small-signal RF MOSFET model is shown in Figure 1. Note that the non-quasi-static effects have been partially incorporated in the three generators by the channel delayfactor τ . These generators represent the operation dependencies of gate-source, source-bulk,and drain-source voltages. Note, that all equations refer to the intrinsic gate, source, bulk, and

Technical Report R2000-1004 , August 2000.RF Integrated Systems & Circuits (RISC) group, Aalborg University, Denmark.

drain nodes. Hence, Vgsi is the voltage from intrinsic gate to intrinsic source (marked as “gi”and “si” in Figure 1) and Vgs denotes the voltage from the extrinsic gate and source nodeswhich are accessible by the designer.

si di

bi

gi

Cgb

Rg

Rs Rd

RdbRsb

Rdsb

gds

Cgs Cgd

CdbCsb

G

B B

DS

FIGURE 1: Small-signal MOSFET equivalent circuit valid in all regions of operation [4].

A general assumption of the model is that resistances Rg, Rd, and Rs do not depend on eitherbias or frequency. Hence, these can be extracted in the most convenient bias operating points.Other parameters depend on the current bias point and must be extracted here. Note that thebulk network is represented by three resistors named Rdb, Rsb, and Rdsb. Generally speaking,Rdsb Rsb, Rdb [1].

REYNISSON/KOLDING: MOSFET SMALL-SIGNAL EXTRACTION PAGE 2


2 STEP 1: MEASUREMENTS

The extraction method is based on two basic measurements on the device to be characterized.These measurements are described as [4]:

1. S-parameter measurement from low frequency (<100MHz) up to the cutoff frequency.The device is mounted in common-source configuration and the drain-source voltageis zero. The gate voltage is increased until the transistor is in strong inversion (linearregion). The gate voltage must be high enough that so that the intrinsic gate-bulk capac-itance can be neglected. Conversely, the gate voltage must be so low enough to preventthe drain-source conductance, gds, from affecting the extraction of the drain and sourceresistances. For a 0.5µm process used in [4], 3V is used. For a 0.25µm process, 0.8Vappears to be sufficient.

2. S-parameter measurement from low frequency (<100MHz) up to the cutoff frequency.The device is mounted in common-source configuration and the drain-source voltage iszero. The transistor is biased in saturation which makes the depletion charge indepen-dent of any drain voltage change.

The measurements are conveniently performed with a network analyzer.

2-1 Experimental Results

To illustrate the extraction methods of [4], an NMOSFET has been fabricated in a 0.25µm epi-taxial CMOS process and RF measurements have been conducted with a network analyzer anda probe station. A shield-based method has been applied to give consistent bulk effects [7] anda full-scale de-embedding method has been used to avoid measuring offsets [6]. The NMOS-FET layout is shown in Figure 2. It’s width is 280µm and it’s length is 0.25µm correspondingto the minimum length of the process.

The S-parameters of the device have been shown for two different bias conditions in Figures3 and 4. These two measurements form the basis for the extraction procedure discussed inthis report. One measurement has been conducted in the linear region and the other in thesaturation region at the bias point of interest (common-source).

STEP 2: EXTRACTION OF EXTRINSIC RESISTANCES

The extraction of extrinsic resistance is based on the measurement in the linear region. Themeasured S-parameters are converted into Y-parameters [8], Y. First, the actual zero-bias ca-



FIGURE 2: Layout of the 280µm wide, 0.25µm long NMOSFET configured with 56 fingers.

pacitances are extracted as [4]

Cg = Cgs + Cgd + Cgb '∣∣∣∣=y11

ω

∣∣∣∣ (1)

Cgd '∣∣∣∣=y12

ω

∣∣∣∣ (2)

Cgs ' Cgd (3)

Cgb ' Cg − Cgd − Cgs (4)

With these extracted capacitances, the resistances may now be extracted as [4]

Rg '∣∣∣∣ <y12=y12=y11

∣∣∣∣ (5)

Rd '∣∣∣∣∣<y21−<y12

=y122

∣∣∣∣∣ (6)

Rs '∣∣∣∣∣<y11=y112 − Rg −

RdC2gd

C2g

∣∣∣∣∣ ·C2

g

C2gs

(7)

The latter equation may sometimes lead to inaccuracy errors and in such cases it may be betterto simply assume that Rs = Rd [4].


In the linear measurement (Vds=0V) the gate-source value has been swept from 0V to the max-imum nominal process voltage of 2.5V. From this sweep it has been observed that the setting



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(s22)

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]A

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(s1

2)

[deg

]A

NG

LE

(s21)

[deg

]A

NG

LE

(s22)

[deg

]

Frequency [GHz Frequency [GHz

FIGURE 3: Measured S-parameters for linear region, Vgs = 0.8V, Vds = 0V (common-source).



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]A

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]

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]A

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]A

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[deg

]A

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[deg

]

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FIGURE 4: Measured S-parameters for saturation region, Vgs = 0.6V, Vds = 1.0V (common-source).



of Vgs is critical to a stable extraction. To rate the different settings, the extracted capacitancevalues Cgd, Cgd, and Cgd have been observed versus frequency. The three components resemblea fairly constant value for Vgs ∈ 0.4 − 1.2V. The setting with most constant capacitance ver-sus frequency was Vgs = 0.8V. Compared to the older 0.5µm technology in [4] where Vgs = 3V,the best setting for the current 0.25µm technology is somewhat lower. Due to reduced chan-nel length and reduced threshold voltage, this appears reasonable. The extracted capacitancevalues for the NMOSFET are shown in Figure 5.

FIGURE 5: Extracted values for Vds = 0V, Vgs = 0.8V, and Vsb = 0V.

The gate and drain resistance values have been extracted from the measurements. The sourceresistance value has been extracted using measurements and the extracted capacitances. Notethat the convergence of the extraction generally improves with increasing frequency.

Comparing the extracted results for Rd and Rs idicates that the extracted values for the sourceresistance are inaccurate. The amount of resistance indicated by the extraction cannot be justi-fied by the NMOSFET layout which is highly symmetrical. Further, the NMOSFET is mountedin a test-fixture with only very small ground lead resistance and proper compensation hasbeen made. As this has also been indicated to be a concern in [4], we shall assume that Rs = Rdand use the extraction method specified for Rd. This is necessary since no FET is available incommon-drain configuration and also reasonable, since the layout is almost symmetrical.

The extracted value for Rd is taken as an average from 8-15GHz, the area where the curve hasflattened out. For the extraction of the gate resistance, an average from 5-15GHz has been used.The extracted values are shown in Table 1. The extracted value of Rg is 2.2Ω while the estimate



made from transistor geometry and process properties is 0.54Ω using the method proposedin [5]. This difference is high, but as the purpose of this report is to evaluate the proposedextraction method, the value used for the gate resistance is 2.2Ω .

TABLE 1: Extrinsic Resistance values extracted from linear measurements

Parameter ValueRd 0.2ΩRs 0.2ΩRg 2.2Ω

3 STEP 3: EXTRACTION OF PROCESS DATA

To continue the parameter extraction, the slope factor, n for the technology must be obtained.The slope factor is defined in [2] and for long-channel devices several extraction methods exist;e.g. [3]. However, for short-channel devices the measuring-based extraction is more compli-cated and in this report we shall utilize the information supplied by the manufacturer. Fromthe MOS9 model card, the values PHIBR and KR give:

n = 1 +KR

2√PHIBR

(8)

where KR and PHIBR are respectively the high-backbias body factor and strong-inversion surfacepotential for the reference transistor. If the BSIM3v3 model card is available, the slope factor isgiven directly.


From the manufacturer-supplied MOS9 model card, the slope factor is extracted to

n = 1.36 (9)

This value is used in the following.

4 STEP 4: EXTRACTION OF PARASITICS IN SATURATION

Finally, the measurements performed in the saturation region are used to extract the bias-dependent model components. Note that the procedure assumes common-source operation.In order to simplify the expressions, the parameters which have already been extracted are re-moved by de-embedding. The measured device S-parameters in saturation are converted intoZ-parameters and de-embedded as

Z = Zm −[

Rg 00 Rd

](10)



These Z-parameters are then converted into Y-parameters (Y = Z−1) and the extraction of thefollowing parameters is performed as:

gds =1

1<y22 − Rs

at low frequency (11)

Cgg =1ω=y11 (12)

Cgd = − 1ω=y12 (13)

gm = <y21 at low frequency (14)

gmb = (n − 1)gm (15)

Ysub = y22 − jωCgd − gds (16)

τ = − 1gmω

(=y21−=y12) (17)

The channel delay parameter τ can be extracted in two ways. If first order effects are to beaccurately modeled at lower frequencies, the delay should be taken as an average of the mea-surements from 45MHz to 5GHz. This causes the fit of =y21 to be rather poor at higherfrequencies. The overall fit of the model is improved if τ is extracted at mid-frequencies (fromaround 7.25GHz to 12.5GHz), at the expense of low-frequency accuracy.

The admittance Ysub contains the bulk network which shall be extracted during the followingstep.


The NMOSFET has been measured in saturation with Vgs = 0.6V and Vds = 1.0V. It has beenconfigured with source grounded to bulk. The S-parameter measurements were shown earlier.Values for the extracted parameters versus frequency are shown in Figure 6.

TABLE 2: Extracted parameter values for measurements in saturation. The first value of τ is for low-frequencyfit, the second for a better overall fit.

Parameter Valuegm 21.9mSgmb 7.8mSgds 583.4µSCgg 462fFCgd 124.1fFCgs 124.1fFCgb 79.4fFτ 0.42ps/0.82ps



FIGURE 6: Extracted parameters for Vgs = 0.6V and Vds = 1.0V.

The transconductance values are extracted by averaging the extracted values from 45MHz toaround 1GHz. The capacitances were obtained by averaging the extracted value over all mea-sured frequency points.

5 STEP 5: EXTRACTION OF BULK EFFECTS

In the previous, the substrate admittance Ysub was extracted. The equivalent model for thesubstrate admittance is shown in Figure 7.

di

RdbRsb

Rdsb

Ysub

Cdb

CsbC +gb

FIGURE 7: Admittance model for the substrate network.

The bulk network in Figure 7 was optimized to fit the extracted bulk measurements. The opti-mization gave a very low estimate for RSB, which effectively shorts CSB. The low source-bulk



resistance means that the bulk effect current generator delivers next to no current at all. Thecomplexity of the bulk network might therefore be reduced by removing Csb, Rsb and the back-gate effect current, although this has not been investigated.


The simulation results versus the extracted results are shown in Figure 8. Visually, the fit ofthe real part is good. The real part of the bulk admittance is very small, and the measurementis noisy, so the fit is as good as expected. The imaginary part fits very well up to 16GHz. Theoptimized bulk network parameters are shown in Table 3

FIGURE 8: A comparison between the extracted and optimized Ysub.

TABLE 3: Optimization results for the Bulk network.

Parameter ValueRdb 5.7ΩRsb 96.6mΩRdsb 5.7ΩCdb 229.7fFCsb 162.3fF



6 SUMMARY OF MODEL PARAMETERS

All the extracted and optimized parameters for the model are shown in Table 4. The equivalentmodel in Figure 1 has been simulated using the parameters in Table 4 and compared with theactual measurements. This is covered in the next section.

TABLE 4: Summary of extracted/optimized parameters.

Parameter ValueRd 0.2ΩRs 0.2ΩRg 2.2Ωgm 21.9mSgmb 7.8mSgds 583.4µSCgg 462fFCgd 124.1fFCgs 124.1fFCgb 79.4fFτ 0.42ps/0.82psRdb 5.7ΩRsb 96.6mΩRdsb 5.7ΩCdb 229.7fFCsb 162.3fF

7 COMPARISON OF MODEL WITH MEASUREMENTS

The model has been simulated using the extracted measurements and the two results are shownin Figure 9. As Y-parameters give better insight into the MOS mode of operation, the measuredand simulated S-parameters are converted to Y-parameters and shown in Figure 10.

From Figure 10, the following is deduced: As the real part of y11 is overestimated, Rg is mostlikely set too high. By replacing the gate resistance estimate for this method by the estimateobtained by [5], re-calculating τ and keeping all the original parameters, the S- and Y- param-eters in Figures 11 and 12 are obtained. Note that s11 now fits more closely with this estimateof Rg than with the original estimate, indicating that this estimate is more accurate. The newestimates are shown in Table 5.

8 CONCLUSIONS

Based on the comparison between the simulations and measurements, the following is con-cluded:



FIGURE 9: Measured S-parameters versus simulations of the proposed model using the extracted parameters. Thesolid line represents the measured S-parameters, and the dotted line denotes the simulated.

TABLE 5: New estimates for Rg and τ .

Parameter New ValueRg 0.54Ωτ 1.24ps/1.62ps



FIGURE 10: Measured Y-parameters versus simulations of the proposed model using the extracted parameters.The solid line represents the measured Y-parameters, and the dotted line denotes the simulated.

• The proposed method fits capacitances well up to 16GHz.

• The bulk network topology seems to fit the extracted Ysub measurements well, althoughthe effect of using a more simple bulk-network should be investigated.

• The estimate for gate-resistance is too high, and should be replaced with the estimate in[5], which gives more accurate results.

• The fit for <y11 and <y12 are poor. This is not unexpected, as they are very smallcompared to the remaining Y-parameters.

• The fit for <y21 and <y22 are within 5% and 27%, respectively. The fit for y22 couldbe improved by re-optimizing the bulk parameters using the new estimate for Rg

• The channel delay, τ should be estimated and included to improve the fit of =y21. Thismay readily be seen from Figure 12. There are some second-order effects evident in y21,which is why τ may be extracted at several frequencies depending on where the modelis supposed to have the best fit.

• The other three =yi j

fit the measured data almost perfectly up to 16GHz.

This method therefore appears applicable when modeling an NMOS in common-source con-figuration, when the gate resistance is estimated using the gate-impedance calculated geomet-rically, and not the by estimate in [4].



FIGURE 11: Measured S-parameters versus simulations of the proposed model topology with an alternate estimatefor Rg. The solid line represents measurements, and the dashed denotes the simulated curve.



FIGURE 12: Measured Y-parameters versus simulations of the proposed model topology with an alternate estimatefor Rg. The solid line represents measurements, and the dashed denotes the simulated curve.



Apart from these model-specific conclusions, the following conclusions are also drawn:

• The method appears only applicable in modeling NMOS devices in common-source con-figuration.

• The bulk-network may be overly complicated for modeling the bulk effects, at least forthe measured transistor. Some effort should be devoted to investigating this matter morethoroughly.

• It is still necessary to optimize five parameters. While this is not as daunting a task as op-timizing the entire model, a method based solely on measurements would be preferable.

• Second order effects are noticeable in y21, indicating that a first-order model is not entirelyadequate for modeling this parameter up to 16 GHz.

A possible improvement on this extraction procedure would be a parameter extraction pro-cedure which wouldn’t need any optimization. However, the number of components in themodel make it impossible to extract all parameters using just one two-port measurement. Thiscould be remedied by manufacturing the prototype to be characterized in several configura-tions, and using several of these two-port measurements to characterize the entire transistor. Athree-port configuration could possibly be utilized as well.

REFERENCES

[1] C. Enz and Y. Cheng. MOS Transistor Modeling Issues for RF Circuit Design. In Proceedings of Workshop onAdvances in Analog Circuit Design (AACD), pages IV.1–IV.26, Nice, France, March 1999.

[2] C. C. Enz, F. Krummenacher, and E. A. Vittoz. An Analytical MOS Transistor Model Valid in All Regios ofOperation and Dedicated to Low-Voltage and Low-Current Applications. Analog Integrated Circuits and SignalProcessing, 9(8):83–114, 1995.

[3] C. Galup-Montoro, M. C. Schneider, A. L. Koerich, and R. L. O. Pinto. MOSFET Threshold Extraction fromVoltage-Only Measurements. Electronics Letters, 30(17):1458–1459, August 1994.

[4] S. H.-M. Jen, C. C. Enz, D. R. Pehlke, M. Schröter, and B. J. Sheu. Accurate Modeling and Parameter Extractionfor MOS Transistors Valid up to 10GHz. IEEE Transactions on Electron Devices, 46(11):2217–2227, November 1999.

[5] T. E. Kolding. Calculation of MOSFET Gate Impedance. Technical Report R98-1009, RISC group, Instituteof Electronic Systems, Division of Telecommunications, Aalborg University, Fredrik Bajers Vej 7A, DK-9220Aalborg, Denmark, August 1998.

[6] T. E. Kolding. A Four-Step Method for De-Embedding Gigahertz On-Wafer CMOS Measurements. IEEE Trans-actions on Electron Devices, 47(4):734–740, April 2000.

[7] T. E. Kolding, O. K. Jensen, and T. Larsen. Ground-Shielded Measuring Technique for Accurate On-WaferCharacterization of RF CMOS Devices. In Proceedings of IEEE International Conference on Microelectronic TestStructures (ICMTS), pages 106–111, Monterey, California, USA, March 2000.

[8] D. M. Pozar. Microwave Engineering. Addison-Wesley, ISBN 0-201-50418-9, 1990.[9] Y. Tsividis. Operation and Modeling of the MOS Transistor. McGraw-Hill, Inc., ISBN 0-07-065523-5, 2nd edition,

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Documents

Measurement-Based Extraction of MOSFET Small …...Measurement-Based Extraction of MOSFET Small-Signal Parameters Ragnar Víðir Reynisson Troels Emil Kolding E-mail: {rvr,tek}@kom.auc.dk