ME 6405: Mechatronics Analog to Digital Convertersume.gatech.edu/mechatronics_course/ME4447_6405/Analog to Digital... · ME 6405: Mechatronics Analog to Digital Converters ... Types

George W. Woodruff School of Mechanical EngineeringGeorgia Institute of Technology

ME 6405: Mechatronics

Analog to Digital Converters

Erik LeeGabriel RamirezSiddharth Doshi

February 13, 2008


Analog to Digital Converter Overview

•Signals•ADC•ADC Properties


What is an Analog Signal•Continuous in nature•Has a value at every instant in time


What is a Discrete Signal•Non-continuous•No knowledge of values between samples


What is an ADC?•Converts an analog signal to discrete values•Most cases it’s a voltage signal to some physical parameter (temp,pressure,etc.)


ADC Properties•Quantization

–Saturation•Sampling

–Aliasing


Quantization•The process of converting a voltage value to a binary word.•Dependent on resolution of Analog to Digital converter•Can range from 6 to 18 bits

0

0.2

0.4

0.6

0.8

1

1.2


Quantization


Quantization ResolutionVR

nfs

V

VR

2∆

=fsV∆

n

= Voltage Resolution

= Full-Scale Voltage Range

= Number of Bits of ADC

⇒Increase Resolution


Resolution and Saturation•To increase resolution always use a input voltage range that is equal to ADC voltage range•Can amplify signal to increase resolution•Saturation Example

–ADC full-scale range is 0V to 10V–What if our analog signal is oscillation between 10V and 11V?


Sampling Frequency

ss T

F 1=

sT = Sampling Period

sT


Sampling•At each sampling period the voltage value at that time will be quantized•The sampling frequency is limited by the ADC•Can vary from 1000 Hz to the MHz range


Aliasing•Must satisfy Nyquist Criterion if we are going to try to reconstruct the signal

signalsample ff 2>


Aliasing•Frequencies will show up as a lower frequency


Filtering•No matter how fast one samples, can’t guarantee there is no aliasing•Low-pass filters can be used to prevent aliasing

–Butterworth•Better attenuation•Larger phase shift

–Bessel


Filtering/Sampling•Cutoff at 0.5•1st order Butterworth filter

Example:Hzsamp 1000=ωHzcutoff 500=ω

Frequencies down to 200Hz will still be attenuated.


Types of ADC• Flash ADC• Delta-Sigma ADC• Dual Slope (integrating) ADC• Successive Approximation ADC


Types of ADC• Comparison


Types of ADC• Flash

–Most high-speed oscilloscopes


Types of ADC• Flash

Advantages• Simplest in terms of

operational theory• Most efficient in terms

of speed, very fast • limited only in terms of

comparator and gate propagation delays

Disadvantages• Lower resolution• Expensive• For each additional

output bit, the number of comparators is doubled

• i.e. for 8 bits, 256 comparators needed


Types of ADC• Sigma Delta ADC

– resolution as fine as 24 bits–Audio frequency signals


Types of ADC• Sigma Delta ADC

Advantages• High resolution• No precision external

components needed

Disadvantages• Slow due to oversampling


Types of ADC• Dual Slope (integrating) ADC

–Superior noise rejection–DMMs


Types of ADC• Dual Slope ADC

Advantages• Input signal is

averaged• Greater noise

immunity than other ADC types

• High accuracy

Disadvantages• Slow• High precision

external components required to achieve accuracy


Successive Approximation ADC

•Binary search through all quantization levels.•From MSB to LSB.•MSB initialized as 1.•Closed-Loop.



•Circuit



•Example• 10 bit resolution or

0.0009765625V of Vref

• Vin= .6 volts• Vref=1volts• Find the digital value

of Vin



• MSB (bit 9)Divided Vref by 2Compare Vref /2 with Vin

If Vin is greater than Vref /2 , turn MSB on (1)If Vin is less than Vref /2 , turn MSB off (0)Vin =0.6V and V=0.5Since Vin>V, MSB = 1 (on)



• Next Calculate MSB-1 (bit 8)Compare Vin=0.6 V to V=Vref/2 + Vref/4= 0.5+0.25 =0.75VSince 0.6<0.75, MSB is turned off

Calculate MSB-2 (bit 7)Go back to the last voltage that caused it to be turned on

(Bit 9) and add it to Vref/8, and compare with Vin

Compare Vin with (0.5+Vref/8)=0.625Since 0.6<0.625, MSB is turned off



•This process continues for all the remaining bits.



Advantages

• Capable of high speed and reliable

• Medium accuracy compared to other ADC types

• Good tradeoff between speed and cost

• Capable of outputting the binary number in serial (one bit at a time) format.

Disadvantages

• Higher resolution successive approximation ADC’s will be slower

• Speed limited to ~5Msps


A/D on HC11

• Components (Block Diagram)• Features• Options Register• A/D Control Register• A/D Results Registers• Conversion Timing• Example Program


A/D Converter on HC11

INTERNAL DATA BUSPE6

AN6

PE7AN7

PE5AN5

ANALOG MUX

8-BIT CAPACITIVE DAC WITH SAMPLE AND HOLD

SUCCESSIVE APPROXIMATION REGISTER AND CONTROL

VRH

RESULT REGISTER INTERFACE

ADR 1 ADR 2 ADR 3 ADR 4

ADCTL A/D CONTROL

CC

F

SC

AN

MU

LTC

DC

CC

BC

A

PE2AN2

PE3AN3

PE4AN4

PE0AN0

PE1AN1 VRL

RESULT


Simplified Diagram01234567

Port E (analog input)

Pin:

Analog Multiplexer

A/D ConverterResult Register Interface

ADR1 - result 1

ADR2 - result 2

ADR3 - result 3

ADR4 - result 4

ADCTL


Features

• Charge Redistribution SAR ADC• 8 input channels, can convert 4 in one

procedure, +/-0.5LSB Accuracy• Analog Input between 0-5V• Resolution = 8 bits = 256 Discrete Values

= Steps of (VRH-VRL)/256• VRL #$00, VRH #$FF


Analog Input translation Table

0.01290.02580.05160.10310.20630.41250.8251.65VRH= 3.3V VRL= 0V

0.01950.03910.07810.15620.31250.6251.2502.500VRH= 5V VRL= 0V

0.39%0.78%1.56%3.12%6.25%12.5%25%50%%

(VRH-VRL)

Bit 0123456Bit 7

Page 41, Programming Reference guide


Option Control RegisterOPTION Register ($1039)

ADPU CSEL IRQE DLY CME CR1 CR0

014 3 267 5

Reset: 001 0 000 0

ADC concerned with :

ADPU – A/D power up

CSEL – A/D Charge Pump Clock select

DLY – Oscillator Startup Delay (4000 clock cycles)


Option Control Register

ADPU - A/D Charge Pump Power Up0: Turn off the A/D1: Turn on the A/D (by enabling the charge pump)

Note: Wait 100 microseconds before using the ADC to allow chargepump and comparator circuits to stabilize.

CSEL - A/D Charge Pump Clock select0: Use the E-clock for the A/D1: Use internal RC oscillator that runs at around 2MHz

Note: If the E-clock is 750KHz or higher, CSEL should be 0. Otherwise CSEL should be 1.


A/D Control RegisterADCTL Register ($1030)

CCF SCAN MULT CD CB CACC

MULT - Single or multiple channel0: Sample a single channel (four times)1: Sample four channels

CD,CC,CB,CA - Channel selectionIf MULT is 0, then CC-CA bits specify the channelIf MULT is 1, then CC specifies the group:

0: Sample AN0-AN3, 1: Sample AN4-AN7CD is reserved for factory test use

CCF - Conversion Complete FlagSet when all four conversions are completeCleared by writing to ADCTL - starts the next conversion

SCAN - Continuous scan mode0: Take one set of four conversions and stop1: Continually perform new conversions

014 3 267 5

Reset: 00 Indeterminate after Reset


A/D Control Register

4 channels.Converted continuously. ADR1-4 overwritten

1 channel.Converted continuously. ADR1-4 overwritten

Continuous Conversion(SCAN = 1)

4 channels. Converted once. Results in ADR1-4.

1 channel.Converted 4 times. Results in ADR1-4.

Single Conversion(SCAN = 0)

Multiple Channel (MULT = 1)

Single Channel(MULT = 0)

Conversion Combinations


A/D Control RegisterChannel Selection

CD CC CB CA Channel Signal If Mult =1, ADR0 0 0 0 PE0 ADR10 0 0 1 PE1 ADR20 0 1 0 PE2 ADR30 0 1 1 PE3 ADR40 1 0 0 PE4 ADR10 1 0 1 PE5 ADR20 1 1 0 PE6 ADR30 1 1 1 PE7 ADR41 0 0 0 Reserved ADR11 0 0 1 Reserved ADR21 0 1 0 Reserved ADR31 0 1 1 Reserved ADR41 1 0 0 VH ADR11 1 0 1 VL ADR21 1 1 0 1/2 VH ADR31 1 1 1 Reserved ADR4


A/D Results RegistersADR1-ADR4 Registers

014 3 267 5

Reset: Indeterminate after Reset

Write:

Read:

ADR1 = $1031

ADR2 = $1032

ADR3 = $1033

ADR4 = $1034

Read Only.

Writes to these register have no effect.


Conversion Sequence/Timing

E Clock cycles:

ADCTL write (1)

Sample (12) Bit 7 (4) 6 (2) _ (2) 0 (2) End (2)

Successive approximation

0 32 64 96 128 total1st, ADR1 2nd, ADR2 3rd, ADR3 4th, ADR4

CC

F


Stop & Wait Modes

Enter wait/stop mode – conversion sequence suspended

Exit wait/stop mode – channel re-sampled / conversion resumed– For stop mode, A/D circuitry requires time

to stabilize (10 ms or DLY bit in OPTION)


Program ExampleORG $1040LDAA #$80 STAA $1039LDY #$30

LOOP DEYBNE LOOP

LDAA #$00STAA $1030

LDX #$1030WAIT BRCLR 0,X #$80 WAIT

LDAA $1031PSHASWIEND

Delay for charge pump to stabilize 100µs

Read and store result

Wait until CCF or bit 7=“1”

OPTIONADPU=1,CSEL=0

ADCTLSCAN=0,MULT=0,CHAN=000


ADC Examples•ADC0808/ADC0809

– 8-Bit µP Compatible A/D Converters with 8-Channel Multiplexer


ADC Examples


ADC Examples•Vehicles

–ECU•Temp Sensor•Oxygen Sensor•RPM

•TV Tuner Card


ADC Examples•Oscilloscope

•Music Recording


ADC Examples•Analog signal needs to be processed, stored or transported in digital form.

Documents

ME 6405: Mechatronics Analog to Digital Convertersume.gatech.edu/mechatronics_course/ME4447_6405/Analog to Digital... · ME 6405: Mechatronics Analog to Digital Converters ... Types