May 17, 20002 USB2.0 Host Controller John S. Howard Staff Engineer Intel Architecture Labs Intel Corporation

May 17, 2000 2

USB2.0 Host Controller

USB2.0 Host ControllerJohn S. HowardJohn S. Howard

Staff EngineerStaff EngineerIntel Architecture LabsIntel Architecture Labs

Intel CorporationIntel Corporation

May 17, 2000 3

AgendaAgenda

Project OverviewProject Overview Key Features OverviewKey Features Overview

– USB 2.0 Host Controller ArchitectureUSB 2.0 Host Controller Architecture– High-Speed Host ControllerHigh-Speed Host Controller

Interface ArchitectureInterface Architecture Interface Data Structure Overview/BenefitsInterface Data Structure Overview/Benefits

– Power ManagementPower Management Host Controller Compliance ProgramHost Controller Compliance Program SummarySummary

May 17, 2000 4

Project OverviewProject Overview

Enhanced Host Controller Specification for USBEnhanced Host Controller Specification for USB– Defines the register (hardware/software) interfaceDefines the register (hardware/software) interface

for a USB 2.0 capable host controller for a USB 2.0 capable host controller Revision 0.95 will be the first public releaseRevision 0.95 will be the first public release

– License agreement provides reciprocal royalty free License agreement provides reciprocal royalty free license to manufacture compliant discrete USB 2.0 license to manufacture compliant discrete USB 2.0 host controllers based on this specificationhost controllers based on this specification

May 17, 2000 5


Revision 1.0 is the final specificationRevision 1.0 is the final specification– License agreement provides reciprocal royalty free License agreement provides reciprocal royalty free

license to manufacture compliant USB 2.0 host license to manufacture compliant USB 2.0 host controllers based on this specification controllers based on this specification

Intel developed specification with contributionsIntel developed specification with contributionsso far from so far from – NEC, Lucent, Philips, Compaq and Microsoft NEC, Lucent, Philips, Compaq and Microsoft – Licensees can also contribute to specificationLicensees can also contribute to specification

ContinuedContinued

May 17, 2000 6


Specification Development methodologySpecification Development methodology– Developed in parallel with USB 2.0 core specificationDeveloped in parallel with USB 2.0 core specification– Low-risk approachLow-risk approach

Leverage existing USB 1.1 HC implementations and knowledge baseLeverage existing USB 1.1 HC implementations and knowledge base

– Provide solutions to well-known USB host controller problemsProvide solutions to well-known USB host controller problems– Focus on reasonable hardware/software complexity tradeoffsFocus on reasonable hardware/software complexity tradeoffs– Validate features whenever possibleValidate features whenever possible

Built prototype driver and host controller in parallel with specificationBuilt prototype driver and host controller in parallel with specification

Host Controller Compliance ProgramHost Controller Compliance Program– Ensures host controllers are compliant to the specificationEnsures host controllers are compliant to the specification

May 17, 2000 7

USB 2.0 Host Controller ArchitectureUSB 2.0 Host Controller Architecture

Multi-function Controller delivers 3 port speedsMulti-function Controller delivers 3 port speeds– Simplifies High-speed Host Controller Simplifies High-speed Host Controller

Optimize for high-speed functionalityOptimize for high-speed functionality– Reuses USB 1.1 Host Controller Designs (drop-in)Reuses USB 1.1 Host Controller Designs (drop-in)– Allows port availability independent of presence ofAllows port availability independent of presence of

high-speed capable softwarehigh-speed capable software

USB 2.0 Host Controller (HC)USB 2.0 Host Controller (HC)

Port 1Port 1

Companion USB HCs for FS/LS Companion USB HCs for FS/LS

Port 1Port 1 Port 2Port 2

Port OwnerPort Owner Control(s) Control(s)

Port 1Port 1 PortPort 22

Port Routing LogicPort Routing Logic

Port NPort N

HC Control Logic/DataHC Control Logic/DataBufferingBuffering

Enhanced HC Control LogicEnhanced HC Control Logic Enhanced Data Buffering Enhanced Data Buffering

Port 2Port 2 Port NPort N

Port NPort N

High-SpeedHigh-Speed(Enhanced Interface) USB HC(Enhanced Interface) USB HC

May 17, 2000 8

USB 2.0 Host Controller Architecture: Port Routing RulesUSB 2.0 Host Controller Architecture: Port Routing Rules

Ports owned by Companion controllers when HS HC software is absentPorts owned by Companion controllers when HS HC software is absent When HS HC Software is present, it “configures” High-Speed HC then:When HS HC Software is present, it “configures” High-Speed HC then:

– Retains ownership for high-speed devicesRetains ownership for high-speed devices– Releases individual port ownership if attached device is not high speedReleases individual port ownership if attached device is not high speed

Routing Logic signals a disconnect on HS HC and a connect on Companion HCRouting Logic signals a disconnect on HS HC and a connect on Companion HC– Ownership returns to HS HC on a disconnect eventOwnership returns to HS HC on a disconnect event

Companion Companion USB 1.1 HCUSB 1.1 HCXX

Companion Companion USB 1.1 HCUSB 1.1 HCXX

Port RegisterPort RegisterPort RegisterPort Register

High Speed HCHigh Speed HCHigh Speed HCHigh Speed HC

TransceiverTransceiverTransceiverTransceiver

Port Routing LogicPort Routing LogicPort Routing LogicPort Routing LogicPort Owner ControlPort Owner ControlPort Owner ControlPort Owner Control

HC HC ConfiguredConfigured

HC HC ConfiguredConfigured

Port RegisterPort RegisterPort RegisterPort Register

May 17, 2000 9

High-Speed Host Controller Interface ArchitectureHigh-Speed Host Controller Interface Architecture

Three-part InterfaceThree-part Interface– PCI SpacePCI Space– Register SpaceRegister Space– Shared Memory Work InterfaceShared Memory Work Interface

PCI Configuration RegistersPCI Configuration Registers– PCI Class CodesPCI Class Codes– Memory space base addressMemory space base address

for register spacefor register space– Power Management InterfacePower Management Interface

PCI ClassPCI ClassCode, etc.Code, etc.PCI ClassPCI ClassCode, etc.Code, etc.

USB Base USB Base AddressAddress


PCI PowerPCI PowerManagementManagement

InterfaceInterface


InterfaceInterface

PCI ConfigurationPCI ConfigurationRegisterRegister


May 17, 2000 10


Memory-based I/O RegistersMemory-based I/O Registers– Capability RegistersCapability Registers

Implementation-specific,Implementation-specific,read-only parametersread-only parametersfor driverfor driver

– Operational RegistersOperational Registers Host controller managementHost controller management List ManagementList Management Port control registersPort control registers

CapabilityCapabilityRegistersRegisters


OperationalOperationalRegistersRegisters


Memory-BasedMemory-BasedI/O RegistersI/O Registers


May 17, 2000 11


Shared Memory Work ListsShared Memory Work Lists– Two schedule Lists Two schedule Lists

(periodic, asynchronous)(periodic, asynchronous)– Queuing data structures Queuing data structures

Used for transfer types Used for transfer types guarantee delivery guarantee delivery

– Different data structures Different data structures used for isochronousused for isochronous Different data structures for Different data structures for

high- and full-speedhigh- and full-speed Optimized for streaming Optimized for streaming

isochronous dataisochronous data No support for retriesNo support for retries

Shared Memory Work ListsShared Memory Work ListsShared Memory Work ListsShared Memory Work Lists

Periodic ListPeriodic ListPeriodic ListPeriodic List

Asynchronous ListAsynchronous ListAsynchronous ListAsynchronous List

May 17, 2000 12

High-Speed Host Controller Interface Architecture (Overview)High-Speed Host Controller Interface Architecture (Overview)







PCI ClassPCI ClassCode, etc.Code, etc.PCI ClassPCI ClassCode, etc.Code, etc.




InterfaceInterface


InterfaceInterface


PCI ConfigurationPCI ConfigurationRegisterRegister Shared Memory Work ListsShared Memory Work ListsShared Memory Work ListsShared Memory Work Lists

Periodic ListPeriodic ListPeriodic ListPeriodic List

Asynchronous ListAsynchronous ListAsynchronous ListAsynchronous List

May 17, 2000 13

Shared Memory Work ListsQueuing Data StructureShared Memory Work ListsQueuing Data Structure

Queues are used for ALL Non-Isochronous transfersQueues are used for ALL Non-Isochronous transfers 1 queue per endpoint1 queue per endpoint Each queue element (transaction descriptor)Each queue element (transaction descriptor)

describes a buffer describes a buffer – I.e. 1 to many transactionsI.e. 1 to many transactions– Up to 20 Kbytes per transaction descriptorUp to 20 Kbytes per transaction descriptor

16Kbytes with worst-case buffer alignment16Kbytes with worst-case buffer alignment No Hardware/software sync required to addNo Hardware/software sync required to add

work to a queuework to a queue Architecture optimized to provide efficientArchitecture optimized to provide efficient

memory accessesmemory accesses– Block, burst accessesBlock, burst accesses– Reduced average number of memory accessesReduced average number of memory accesses

to start transactionto start transaction

May 17, 2000 14

Shared Memory Work ListsQueuing Data Structure (Ex.)Shared Memory Work ListsQueuing Data Structure (Ex.)

Transfer DescriptorsTransfer Descriptors

Linked to queue head Linked to queue head by software driverby software driver

Transfer DescriptorsTransfer Descriptors

Linked to queue head Linked to queue head by software driverby software driver

qTDqTD00qTDqTD00

qTDqTD22qTDqTD22

Data Data BufferBuffer00




qTDqTD11qTDqTD11

DataDataBufferBuffer22

DataDataBufferBuffer22

Queue Head:Queue Head:Static queue head informationStatic queue head informationDynamic transfer execution areaDynamic transfer execution area

Queue Head:Queue Head:Static queue head informationStatic queue head informationDynamic transfer execution areaDynamic transfer execution area

SetupSetupSetupSetup

StatusStatusStatusStatus

Setup Setup DataData

Setup Setup DataData

Receive Receive DataData

BufferBuffer

Receive Receive DataData

BufferBuffer

DataDataDataData

Example: Control TransferExample: Control Transfer

Initial Condition: QHD emptyInitial Condition: QHD empty


Initial Condition: QHD emptyInitial Condition: QHD empty


Software attaches list to QHDSoftware attaches list to QHD


Software attaches list to QHDSoftware attaches list to QHDCurrentCurrent

(A)(A)

(A) HC Finds an active qTD via a QHD (A) HC Finds an active qTD via a QHD Next pointer and copies to overlay Next pointer and copies to overlay area (Setup Stage)area (Setup Stage)

Copy results in QHD Next pointer Copy results in QHD Next pointer inheriting from overlay’d qTDinheriting from overlay’d qTD

HC executes from QHD for 1 HC executes from QHD for 1 transactiontransaction

NextNextNext

(B)(B)(B)(B)

(B) HC Finds an active qTD via a QHD (B) HC Finds an active qTD via a QHD Next pointer and copies to overlay Next pointer and copies to overlay area (Data Stage)area (Data Stage)


HC executes from QHD until doneHC executes from QHD until done

(B) HC Finds an active qTD via a QHD (B) HC Finds an active qTD via a QHD Next pointer and copies to overlay Next pointer and copies to overlay area (Data Stage)area (Data Stage)


HC executes from QHD until doneHC executes from QHD until doneCurrentCurrentCurrentCurrentCurrentCurrentCurrentCurrent

NextNextNextNext

(C) HC Finds an active qTD via a QHD (C) HC Finds an active qTD via a QHD Next pointer and copies to overlay Next pointer and copies to overlay area (Status Stage)area (Status Stage)



(C) HC Finds an active qTD via a QHD (C) HC Finds an active qTD via a QHD Next pointer and copies to overlay Next pointer and copies to overlay area (Status Stage)area (Status Stage)



(C)(C)(C)(C)

May 17, 2000 15

Shared Memory Work ListsIsochronous Data StructuresShared Memory Work ListsIsochronous Data Structures

Used only in periodic listUsed only in periodic list– Time-oriented data structureTime-oriented data structure– ““Frame number” encoded in topology of listFrame number” encoded in topology of list

Position of work item in periodic list determines whenPosition of work item in periodic list determines whenit will be “seen” and executed by the host controllerit will be “seen” and executed by the host controller

– No hardware (micro)-frame arithmetic requiredNo hardware (micro)-frame arithmetic required Different data structures for high-speedDifferent data structures for high-speed

and low-speedand low-speed– High-speed data structure optimized for large transfersHigh-speed data structure optimized for large transfers– Full-speed data structure optimized forFull-speed data structure optimized for

split-transaction supportsplit-transaction support

May 17, 2000 16

Shared Memory Work ListsHardware Scatter/GatherShared Memory Work ListsHardware Scatter/Gather

All transfer data structures areAll transfer data structures arescatter/gather capablescatter/gather capable

Simple hardware implementationSimple hardware implementation– No pointer arithmetic requiredNo pointer arithmetic required– Simple concatenation of page pointerSimple concatenation of page pointer

to page offset to generate buffer addressto page offset to generate buffer address– Software initializes page offset, hardwareSoftware initializes page offset, hardware

manages page pointers and page offsetmanages page pointers and page offsetbased on transfer progressbased on transfer progress

May 17, 2000 17

Power ManagementPower Management

High-speed controller power managementHigh-speed controller power management– USB port power managementUSB port power management– PCI Bus Power Management InterfacePCI Bus Power Management Interface

Provides per/port capabilities for managing bus Provides per/port capabilities for managing bus power as defined in USB specificationpower as defined in USB specification

Support defined for PCI Advanced Power Support defined for PCI Advanced Power management interfacemanagement interface– Compliant with PCI Bus Power Management Interface Compliant with PCI Bus Power Management Interface

Specification, Revision 1.1Specification, Revision 1.1

May 17, 2000 18

USB 2.0 Host Controller Compliance ProgramUSB 2.0 Host Controller Compliance Program

Compliance testing includesCompliance testing includes– Standard USB 2.0 Compliance testsStandard USB 2.0 Compliance tests– Standard USB 2.0 Electrical testsStandard USB 2.0 Electrical tests– Host controller-specific Interface Functional TestingHost controller-specific Interface Functional Testing

AvailabilityAvailability– HC compliance test will be available from IntelHC compliance test will be available from Intel

Method of distribution (to be defined)Method of distribution (to be defined)– Alpha-level tools available in Q3 2000Alpha-level tools available in Q3 2000– Beta-level tools available in Q1 2001Beta-level tools available in Q1 2001– Production release available with release of 1.0 hostProduction release available with release of 1.0 host

controller specificationcontroller specification

May 17, 2000 19

USB 2.0 Host Controller Compliance ProgramUSB 2.0 Host Controller Compliance Program

HC-specific compliance software HC-specific compliance software under development at Intelunder development at Intel

Special compliance devicesSpecial compliance devices(high-speed and full/low speed)(high-speed and full/low speed)

Special-purpose application and Special-purpose application and driver for controlled testingdriver for controlled testingand analysisand analysis

Interface Functional TestingInterface Functional Testing– Device InteroperabilityDevice Interoperability– USB 2.0 protocol andUSB 2.0 protocol and

transfer extensionstransfer extensions– System InteractionSystem Interaction– Etcetera, …Etcetera, …

HC Compliance HC Compliance ApplicationApplication

HC Compliance HC Compliance ApplicationApplication

HC Compliance Test HC Compliance Test DriverDriver

HC Compliance Test HC Compliance Test DriverDriver

EHCI Unit EHCI Unit Under TestUnder TestEHCI Unit EHCI Unit Under TestUnder Test

USB 2.0 USB 2.0 Hub (s)Hub (s)

USB 2.0 USB 2.0 Hub (s)Hub (s)

HS HS Compliance Compliance

Device(s)Device(s)

HS HS Compliance Compliance

Device(s)Device(s)FS/LS FS/LS

Compliance Compliance Device (s)Device (s)

FS/LS FS/LS Compliance Compliance Device (s)Device (s)

May 17, 2000 20

SummarySummary

Low-risk IntroductionLow-risk Introduction– All ports are HS/FS/LS CapableAll ports are HS/FS/LS Capable– Legacy (non-high-speed aware) software just worksLegacy (non-high-speed aware) software just works– Re-use of 1.1 controllers simplifies high-speed controllerRe-use of 1.1 controllers simplifies high-speed controller

Interface optimized for good memoryInterface optimized for good memoryaccesses efficiencyaccesses efficiency

Reasonable tradeoff of hardware/software Reasonable tradeoff of hardware/software complexitycomplexity

May 17, 2000 21

SummarySummary

PCI power management compliantPCI power management compliant Host controller compliance programHost controller compliance program Revision 0.95 for discrete HC Q3 2000Revision 0.95 for discrete HC Q3 2000

– Gating item is validation of 2 discrete host controllersGating item is validation of 2 discrete host controllers Revision 1.0 in 2001Revision 1.0 in 2001

– Gating item is validation of integrated host controllerGating item is validation of integrated host controller

ContinuedContinued

Documents

May 17, 20002 USB2.0 Host Controller John S. Howard Staff Engineer Intel Architecture Labs Intel Corporation