S16438EJ4V0IF00 - USB2.0 Board Layout Guideline

Information

2002

USB2.0 Board Layout Guideline

Document No. S16438EJ4V0IF00 (4th edition) Date Published May 2006 NS CP (N)

Printed in Japan

Information S16438EJ4V0IF 2

[MEMO]


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VOLTAGE APPLICATION WAVEFORM AT INPUT PIN

Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the

CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may

malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,

and also in the transition period when the input level passes through the area between VIL (MAX) and

VIH (MIN).

HANDLING OF UNUSED INPUT PINS

Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is

possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS

devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed

high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND

via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must

be judged separately for each device and according to related specifications governing the device.

PRECAUTION AGAINST ESD

A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as

much as possible, and quickly dissipate it when it has occurred. Environmental control must be

adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that

easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static

container, static shielding bag or conductive material. All test and measurement tools including work

benches and floors should be grounded. The operator should be grounded using a wrist strap.

Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for

PW boards with mounted semiconductor devices.

STATUS BEFORE INITIALIZATION

Power-on does not necessarily define the initial status of a MOS device. Immediately after the power

source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does

not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the

reset signal is received. A reset operation must be executed immediately after power-on for devices

with reset functions.

POWER ON/OFF SEQUENCE

In the case of a device that uses different power supplies for the internal operation and external

interface, as a rule, switch on the external power supply after switching on the internal power supply.

When switching the power supply off, as a rule, switch off the external power supply and then the

internal power supply. Use of the reverse power on/off sequences may result in the application of an

overvoltage to the internal elements of the device, causing malfunction and degradation of internal

elements due to the passage of an abnormal current.

The correct power on/off sequence must be judged separately for each device and according to related

specifications governing the device.

INPUT OF SIGNAL DURING POWER OFF STATE

Do not input signals or an I/O pull-up power supply while the device is not powered. The current

injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and

the abnormal current that passes in the device at this time may cause degradation of internal elements.

Input of signals during the power off state must be judged separately for each device and according to

related specifications governing the device.

NOTES FOR CMOS DEVICES

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The information in this document is current as of May, 2006. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information.No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document.NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information.While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features.NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application.

The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application.

(Note)

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M8E 02. 11-1

(1)

(2)

"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries."NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above).

Computers, office equipment, communications equipment, test and measurement equipment, audioand visual equipment, home electronic appliances, machine tools, personal electronic equipmentand industrial robots.Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disastersystems, anti-crime systems, safety equipment and medical equipment (not specifically designedfor life support).Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, lifesupport systems and medical equipment for life support, etc.

"Standard":

"Special":

"Specific":


Major Revisions in this Edition

Page Description

Overall Addition of μPD720102 and μPD720114

p. 9 Addition of (c) In case of 2 signal pins for 1 USB port (RS and Rpu

Resistors Built-in) to Figure 1. RS for Upstream Port

p. 9 Modification of Table 1. RS and Rpu Resistor Values for Upstream Port

p. 11 Addition of (c) In case of 2 signal pins for 1 USB port (RS and Rpd

Resistors Built-in) to Figure 2. RS for Downstream Port

p. 11 Modification of Table 2. RS and Rpu Resistor Values for Downstream Port

p. 17 Addition of description in 10. ESD Protection

The mark "<R>" shows major revised points.

The revised points can be easily searched by copying an "<R>" in the PDF file and specifying it in the "Find what:" field.


CONTENTS

1. Introduction.............................................................................................................................................. 7

2. USB Logo, Package Design and Location of Pins ............................................................................... 7

3. USB2.0 Signal Integrity Guidelines........................................................................................................ 7

4. Power Supply ......................................................................................................................................... 12

5. Analog VDD.............................................................................................................................................. 12

6. RREF Resistor........................................................................................................................................ 12

7. Analog VSS.............................................................................................................................................. 15

8. Decoupling Capacitor ........................................................................................................................... 16

9. EMI Protection........................................................................................................................................ 16

10. ESD Protection..................................................................................................................................... 17

11. USB Cable and Receptacle................................................................................................................. 17


1. Introduction

This document describes guidelines for designing boards using NEC Electronics USB2.0 devices. These

guidelines offer NEC Electronics’ recommendations with no guarantee.

2. USB Logo, Package Design and Location of Pins

To certify that a product is fully compliant with the USB2.0 specification, the developer must obtain the USB

Implementers Forum (USB-IF) logo for the product. The logo requirements include interoperability testing and tests

for signal quality such as an eye-pattern test. Signal quality is very sensitive to package design, location of pins, and

layout of the board. Designers of USB ASICs and circuit boards must carefully consider these issues.

NEC Electronics checks for signal quality using Spice models before designing USB ASICs, but please remember

that we may need to restrict pin locations and use new packages requiring long-term development in some cases.

3. USB2.0 Signal Integrity Guidelines

a. Limit the trace length of USB D+ and D− from USB2.0 chip to USB receptacles. USB-IF expects that the delay

of functions and hubs on their upstream-facing ports will be less than 1 ns (roughly 75 mm of circuit trace,

depending on PCB and trace material). The delay for hosts and hubs on downstream-facing ports should be

less than 3 ns (roughly 225 mm of circuit trace, depending on PCB and trace material). It is recommended for

the trace of function and hub's upstream-facing ports to be about 20 to 30 mm, and the trace of host and hub's

downstream-facing ports to be about 200 mm from D+/D− of the chip to the receptacles.

b. Keep traces of USB bus D+ and D− the same length. The difference in length between D+ and D− should be

less than 0.5 mm, with the priority that DP/DM (DN) > RSDP/RSDM (RSDN).

c. Consider the distance between each layer, trace width of D+ /D−, and trace pitch between D+ and D−, to

achieve the differential characteristic impedance 90 Ω. d. Common mode trace impedance for D+ and D− should be kept at 45 Ω.

e. Maintain parallelism between D+ and D− throughout the route from USB2.0 chip to receptacles.

f. Avoid right-angle bent traces. If it is necessary to turn 90 degrees, two 45-degree turns or arcs should be

used instead.

g. For hosts and hubs, maximize the distance between each trace pair of D+ and D− to avoid crosstalk between

pairs.

h. Minimize the trace length for the bold lines shown in Figures 1, 2 and 3. Especially, trace length must be as

short as possible between RSDP and DP via Rs, and between DM (DN) and RSDM (RSDN) via Rs.

Unnecessary trace length makes over/under-shoot of signals worse.

i. Do not route USB2.0 D+ and D− over any splits in the power or ground planes.

j. It is preferred to route USB2.0 D+ and D− on the same layer as the chip, to avoid vias on USB2.0 D+ and D−

traces between the USB2.0 chip and receptacles.

k. If vias cannot be avoided on USB2.0 D+ and D−, keep the number of vias and corners to a minimum. This

reduces signal reflections and impedance changes.

l. Do not put copper pour close to USB2.0 D+ and D− signal since it may affect their impedance. But it is

preferred to put copper pour along all edges of the board for FCC compliance.

m. Put the ground layer under the USB D+ and D− to reduce signal reflections and impedance changes. I.e., use

the ground layer rather than the power layer for the return reference plane for USB D+ and D−.

n. Make sure that other signal traces do not cross USB differential signal wiring.

o. Route the USB D+/D− lines as far as possible from other signal lines, especially high frequency signals such

as clocks or data buses.


p. The preferred layer stack of the PCB board is:

For USB2.0 D+/D−, route on signal layer 1 For USB2.0 D+/D−, route on signal layer 2 Signal layer 1 Signal layer 1

Ground Power

Power Ground

Signal layer 2 Signal layer 2

Figure 1. RS for Upstream Port (1/2)

(a) In case of 4 signal pins for 1 USB port

DP

DM

VBUSD−D+GND

1 4

2 3

Upstream portUSB B receptacle connector

LSI

RSDM

RSDP

RPU

Rs

Rs1.5 kΩ ±1% Note

Rs + Ron (Resistance for internal driver which is active) = 45Ω±10%

Note USB specification requires 1.5 kΩ ± 5% (including internal resistance in LSI).

(b) In case of 2 signal pins for 1 USB port

(RS Resistors Built-in)

1.5 kΩ ±1% Note

DP

DM

VBUSD−D+GND


LSI

RPU

1 4

2 3

Note USB specification requires 1.5 kΩ ± 5% (including internal resistance in LSI).


Figure 1. RS for Upstream Port (2/2)

(c) In case of 2 signal pins for 1 USB port (RS and Rpu Resistors Built-in)

DP

DM

VBUSD−D+GND


LSI

1 4

2 3

Table 1. RS and Rpu Resistor Values for Upstream Port

Products Type RS (Ω) Precision Rpu (Ω) Precision Figure

μPD720110A Hub controller 36 ±1% 1.5 ±1% 1(a)

μPD720112/μPD720113 Hub controller - - 1.5 ±1% 1(b)

μPD720114 Hub controller - - - - 1(c)

μPD720121 IDE bridge 36 ±1% 1.5 ±1% 1(a)

μPD720130/μPD720133 IDE bridge 39 ±1% 1.5 ±1% 1(a)

μPD720122 Device controller 36 ±1% 1.5 ±1% 1(a)

4 USB signals version ASCP CB-9VX 36 ±1% 1.5 ±1% 1(a)

4 USB signals version ASCP CB-10VX 39 ±1% 1.5 ±1% 1(a)

4 USB signals version ASCP CB-12 39 ±1% 1.5 ±1% 1(a)

4 USB signals version ASCP CB-130 39 ±1% 1.5 ±1% 1(a)

<R>

<R>


Figure 2. RS for Downstream Port (1/2)

(a) In case of 4 signal pins for 1 USB port

DMnDPn

Downstream portUSB A receptacle connector

from Power switch output

1

2

3

4

VBUS

D−D+

GND

LSI

15 kΩ ±5%

RSDM

RSDPRs

Rs

Rs + Ron (Resistance for internal driver which is active) = 45Ω±10%

(b) In case of 2 signal pins for 1 USB port

(RS Resistors Built-in)

DMnDPn


1

2

3

4

VBUS

D−D+

GND

LSI

15 kΩ ±5%


Figure 2. RS for Downstream Port (2/2)

(c) In case of 2 signal pins for 1 USB port

(RS and Rpd Resistors Built-in)

DMnDPn


1

2

3

4

VBUS

D−D+

GND

LSI

Table 2. RS and Rpd Resistor Values for Downstream Port

Products Type RS (Ω) Precision Rpd (Ω) Precision Figure

μPD720100A/μPD720101 Host controller 36 ±1% 15 ±5% 2(a)

μPD720102 Host controller - - - - 2(c)

μPD720110A Hub controller 36 ±1% 15 ±5% 2(a)

μPD720112/μPD720113 Hub controller - - 15 ±5% 2(b)

μPD720114 Hub controller - - - - 2(c)

<R>

<R>


4. Power Supply

a. Traces that supply USB 5 V bus power should be designed wide and thick enough to supply the current for

ports which are implemented on the board. Otherwise, due to the voltage drop in the traces, a controller may

detect an over-current condition when the ports are drawing maximum current (up to 500 mA per port).

b. Add a ferrite bead to Vbus power to reduce noise supplied to the bus.

c. Keep the power and ground layers adjacent to each other in order to prevent big current loops and noise.

d. Place a 100 μ F or greater bulk capacitor for USB 5 V bus power decoupling. Place a 1 μ F capacitor for spike

filtering.

5. Analog VDD

a. Filter analog VDD which is used for USB2.0 analog logic, to prevent noise from digital VDD. It recommended to

separate digital and analog VDD on the same layer. This Analog VDD must be used only for the Analog circuit

of the USB device, not for other devices. Route analog VDD for other devices separately.

b. AVDD and PVDD pins of NEC Electronics’ USB LSI must be connected to analog VDD. Use wide traces between

the Analog VDD power source and PVDD/AVDD to minimize noise and to reduce the L parameter of the line. It is

recommended to use 3 or more times the width of a normal trace.

c. Make sure to minimize the noise on the analog power source or analog VDD from digital signals or digital VDD.

For preventing crosstalk, high frequency signals such as clock or data bus should not cross above the

AVDD/PVDD.

d. Digital VDD should be provided with solid connection for good voltage stability. And separately, analog AVDD

should be provided with good connection as well. If multiple layers of digital power or ground are needed,

more via connections should be provided. This allows solid connection between layers of power or ground, in

reducing the potential difference between.

e. Connect digital VDD and analog VDD via the inductor, ferrite bead, or the resistor as shown in Figure 6. When

inductors or ferrite bead are used in analog filtering for analog power of USB2.0 chip, they should be placed

away from one another. Also prevent resonance due to the influence of the L parameter of the line and

inductor with the board capacitance. If you use a resistor to connect digital and analog VDD, less than 3 Ω

resistance should be used to avoid a large voltage difference between digital VDD and analog VDD.

f. Analog VDD should be derived from digital VDD in a closeby voltage regulator through an inductor, ferrite bead

or resistor. The same voltage regulator can be used for supplying digital VDD.

6. RREF Resistor

a. The steady-state current of the analog PLL is regulated by the external resistor connected on the line between

RREF/AVSS(R). Therefore, the instability of voltage on RREF/AVSS(R) may influence the characteristics of the

transfer waveform including its amplitude, current, voltage, jitter, and stability of analog PLL. Thus, the signal

at the RREF pin should be measured for noise.

b. Minimize the total trace length from the RREF pin and AVSS(R) through the RREF resistor as shown in Fig. 3.

(Use an RREF resistor having a tolerance of 1% or less.) The trace which is indicated with a bold line should

route with a wide trace to achieve as small an L parameter as possible. To prevent crosstalk, high frequency

signals such as DP/DM (DN), clock or data bus should not cross above the AVSS(R). (Only steady mode

signals, i.e., fixed level signals when the USB bus is active, should be allowed to cross above AVss(R).)

c. Connect the AVSS(R) to analog VSS at the AVss(R) pin, so as to be independent of the RREF current path.


Figure 3. Resistor used between RREF and AVSS(R)

LSI

RREF

AVSS(R)

RREF

AVSS

Table 3. RREF Resistor Values

Products Type RREF (kΩ) Precision

μPD720100A/μPD720101 Host controller 9.1 ±1%

μPD720102 Host controller 1.6 ±1%

μPD720110A Hub controller 9.1 ±1%

μPD720112/μPD720113 Hub controller 2.43 ±1%

μPD720114 Hub controller 2.43 ±1%

μPD720121 IDE bridge 9.1 ±1%

μPD720130/μPD720133 IDE bridge 2.43 ±1%

μPD720122 Device controller 9.1 ±1%

4 USB signals version ASCP CB-9VX 9.1 ±1%

4 USB signals version ASCP CB-10VX 2.43 ±1%

4 USB signals version ASCP CB-12 1.6 ±1%

4 USB signals version ASCP CB-130 1.6 ±1%

<R>

<R>


Figure 4. Example of Good Connecting to RREF and AVSS(R)

RREF

AVSS(R)

RREF resistor

Analog VSS field

Figure 5. Examples of Worse Connecting to RREF and AVSS(R)

(a) (b)

RREF

AVSS(R)

RREF resistor

Analog VSS field

RREF

AVSS(R)

RREF resistor

Analog VSS field

Remark Example (a) shows that the LSI may be influenced by noise from analog VSS.

Example (b) shows that the signal may be influenced by cross talk of lines which are close to

next line or crossing over line, and LSI may operate wrong functionally.


7. Analog VSS

a. Filter analog VSS which are used for USB2.0 analog logic, to prevent noise from digital VSS. It is recommended

to separate digital and analog VSS on the same layer. This Analog VSS must be used only for the Analog circuit

of the USB device, not for other devices. It should be better to design AVDD plane widely enough for stability.

b. The AVSS and PVSS pins pf NEC Electronics’ USB LSI must be connected to analog VSS. Use a wide trace

between Analog VSS ground plane and PVSS/AVSS to prevent noise and to reduce the L parameter of the line.

It is recommended to use 3 times or more the width of a normal trace.

c. Make sure to minimize the noise on the analog ground plane or analog VSS coming from the digital ground

plane or digital signals or digital VSS. To prevent crosstalk, high frequency signals such as DP/DM (DN), clock

or data bus should not cross above the AVSS/PVSS.

d. Digital VSS should be provided with solid connection for good voltage stability. And separately, analog AVSS

should be provided with good connection as well. If multiple layers of digital power or ground are needed,

more via connections should be provided. This allows solid connection between layers of power or ground, in

reducing the potential difference between.

e. If it is not feasible to separate analog VSS from digital VSS, connect AVSS/PVSS pin to digital VSS with careful

attention to minimizing noise coupling.

f. Connect digital VSS and analog VSS via an inductor, ferrite bead or the resistor as shown in Figure 6. If

inductors are used in analog filtering for analog power of the USB2.0 chip, they should be placed away from

one another. And also care must be used to prevent resonance due to the influence of the L parameter of the

line and inductor with the board capacitance. The effect of a ferrite bead depends on the noise on digital VSS

and on the voltage difference between digital and analog VSS. Using a ferrite bead with some ICs and PCBs

may aggravate noise on analog VSS. If you use a resistor to connect between digital and analog VSS, less

than 3 Ω resistance should be used to avoid a large voltage difference between digital VSS and analog VSS.

g. Analog VSS should be derived from digital VSS in a closeby voltage regulator through an inductor, ferrite bead

or resistor. A regulator with same voltage can be used for supplying digital VSS.

Remark The integrated PLL in the LSI may lose frequency lock momentarily because of noise from the

AVSS/PVSS/AVDD/PVDD pins. As the result, the chip may operate wrong functionally. Transaction

errors on the USB bus may often be caused by the PLL temporarily losing frequency lock. Hence, it is important to minimize noise.


Figure 6. Analog and Digital Power Line

Analog VDD

Analog VSS

Less than 3 Ω

Less than 3 Ω

10 μF 0.1 μF 0.1 μF 0.01 μF 0.01 μF

or

Digital VDD

Decoupling capacitors fordigital VDD and VSS

Digital VSS

Analog VDD

Analog VSS

10 μF 0.1 μF 0.1 μF 0.01 μF 0.01 μF

Digital VDD

Decoupling capacitors fordigital VDD and VSS

Digital VSS

Remark Define the value of inductors to prevent the resonance problem between board capacitance and

inductance.

8. Decoupling Capacitor

Decoupling Capacitors are utilized to flatten the fluctuations of voltage and to filter noise. Individual PCB

development should be consider the numbers, specifications and layout of Decoupling Capacitors.

a. Mount at least one decoupling capacitor per each pair of digital VDD and VSS. These should be located close

to USB2.0 devices. It is effective to mount these capacitors on the opposite side of the PCB board.

b. Use surface-mount components with wide and square mounting pads with vias located immediately adjacent

without going through traces. Vias should have large diameter and be plated through.

c. Mount at least one 0.1 μF or 0.01 μF capacitor per pair of analog VDD and VSS. Mount at least one 10 μF bulk

capacitor for all analog VDD and VSS. These should be located close to USB2.0 devices.

d. Do not use electrolytic capacitors as decoupling capacitors, but use tantalum or ceramic capacitors, which

have good performance under high frequency.

9. EMI Protection

NEC Electronics’ EMI test results for host controller and hub show that common mode choke coils should not be

needed for EMI compliance. If common mode choke are used, USB signaling may be degraded in some case.

There are chokes that have been tested with USB2.0 signals; work with common mode choke vendors for careful

selection.


10. ESD Protection

If an ESD suppressor is implemented, USB signaling may be degraded in some case. There are parts that have

been tested with USB2.0 signals; work with ESD suppressor vendors for careful selection. It is recommended to use

the following products.

http://www.necel.com/discrete/english/products/diode/nsad.html

11. USB Cable and Receptacle

Use USB2.0 compliant components such as USB receptacles on the PCB and USB cables. Products with non-

certified USB components may not be compliant with USB logo.

Figure 7. Example of QFP Package Layout

(a) 1st Layer (Trace Layer) (b) 4th Layer (Trace Layer)

USB Connector

USBConnector

LSI LSI

1.2V VDD

1.2V AVDD

AVSS

RS

RS Rpu

RREF

VSS

(c) 2nd Layer (GND Layer) (d) 3rd Layer (VDD Layer)

LSI

USBConnector

LSI

1.2V VDD

3.3V AVDD

1.2V AVDD

USB Connector

LSI

AVSS

<R>


[MEMO]


[MEMO]

NEC Electronics Corporation1753, Shimonumabe, Nakahara-ku,Kawasaki, Kanagawa 211-8668, JapanTel: 044-435-5111http://www.necel.com/

[America]

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For further information, please contact:

G05.12A

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S16438EJ4V0IF00 - USB2.0 Board Layout Guideline