LSST Electronics Review BNL January 25-26, 20121 LSST Electronics Review BNL January 25-26, 2012 Electronics Development Plan and Vertical Slice Test (VST)

LSST Electronics Review • BNL • January 25-26, 2012 1LSST Electronics Review • BNL • January 25-26, 2012

Electronics Development Plan and Vertical Slice Test (VST)

R. Van Berg

Electronics Mini-ReviewJanuary 26th, 2012

LSST Electronics Review • BNL • January 25-26, 2012 2

Outline – Development Plan

• Chips– ASPIC– CABAC

• Boards– FEB (Front End Board)– Video and Bias Cables– BEB (Back End Board)– Backplane– RCM (Raft Control Module)

• Firmware• Software• Testing

– Bench testing [………..ongoing………………………………………………………..]– VST Phase I [now to end of 2012]– VST Phase II [late 2012 through 2013]– VST Phase III [late 2013 – mid 2014]

Raft Control Crate (RCC)

On FEB


Chip Development Plans

• ASPIC– Now at ASPIC2 – bench testing very advanced, satisfies essentially all

requirements but some small tweaks to go– ASPIC3 with slightly modified bias scheme, more gain options, a bypass

option and serial configuration (SPI) to be submitted May 2012 – expect this to be the final object but bench tests and VST to verify that conjecture.

• CABAC– Initial submission of process test chip in November 2011, expect submission

of a full, nominally complete, chip in April/May 2012 – followed by extensive bench tests (including thermal lifetime tests) and VST

– Second submission (if needed) early 2013

• Bottom Line – packaged ASPIC3 and CABAC1 chips should be available to test by about September 2012 so FEB4 to take them needs to be ready ~ Oct. and RCC system should be ready for the FEB4 by the same time


Board Development Plans

• FEB – driven by chip schedule – present FEB3 uses ASPIC2 and SCC, FEB will use ASPIC3 + CABAC1 (also needs to be in tune with contamination testing – might want FEB4 in several different materials). Intent is to be as “final” as possible (e.g. include connections for RSA heaters and sensors).– FEB4 ready for assembly + test ~ Sept 2012 when chips are ready– Video and Bias cables same as present version except somewhat longer (45

cm) and with mesh GND plane – pin counts stay unchanged, pin assignments largely unchanged

• BEB + Backplane + RCM + Firmware + Software – unified design driven by VST and FEB4– Working system needed by ~ Sept. 2012 to allow testing of FEB4 (VST Phase

II)• Need to freeze overall design ~ May-June to allow time for board layout and

firmware/software development• Firmware and Software development can advance significantly, if not completely,

prior to availability of FEB4– Design input from requirements/desiderata lists plus findings of VST


Testing – Multiple Facets

• Electrical bench testing to verify individual elements. We need to know that sub-elements of the design work properly (or well enough) before we assemble them into larger structures– Custom chips extensively tested before they are put on “final” boards– COTS devices tested as appropriate (e.g. low voltage regulators for use on

the FEB must work properly at -100C)• Contamination testing

– Devices and elements must satisfy contamination constraints in a fully independent program so far looking at small samples, but some phase II boards are planned to be part of larger scale contamination testing)

• Environmental testing– In addition to operating at reduced temperatures, need to know that there is

no significant long term degradation of devices at the expected operating conditions either through electronic effects (e.g. “hot carriers”) or mechanical effects (e.g. cracks in solder joints from differential CTE stress)

• Full scale system tests – the Vertical Slice Test (VST)


Vertical Slice Test

• A “complete” front to back test of the focal plane electronics chain.– Phased to build from center out

• FEB-BEB-RCM now in Phase I• SDS enters in Phase I (March 2012)• CCD emulator in March 2012• CCS-like control enters soon after SDS• CCD readout in March-May 2012 time frame• TCM (or TCM mockup) enters at Phase II • Power system enters at Phase II or Phase III

– Phases defined by hardware generations• Phase I is present hardware (FEB3, BEB-RCM 1)• Phase II is next generation hardware (FEB4, BEB-RCM 2)• Phase III is “final” generation hardware – pre-production versions

• Overall goal is to verify that we have met (or exceeded) the design requirements or, via this process, improve the design until we can meet those requirements

• Actual list of “tests” in each phase or sub-phase is quite extensive and, in general, must be repeated in each later phase – see detail in talks to follow


VST – Phase I

• Data from single ASPIC, multiple channels• Multiple copies of boards, evolving

firmware and software• Three parallel efforts:

– Harvard– Penn– Paris


VST – Phase I - Harvard

• Initial focus on firmware development and digital testing– Firmware to cover all basic functions

• ASPIC timing• CCD clock timing• Voltage setting• Data readout• Firmware to facilitate other testing• Firmware to integrate CDS • Documentation

– Temporary software to use USB readout (until CDS is integrated)– Digital testing

• Data integrity• Full speed data transfers (50 MHz DDR on 18 bit backplane bus)

• Secondary focus on preparation for CCD readout in concert with BNL– Dewar preparation

• Initially cold CCD, warm electronics• Eventually cold CCD, cold FEB, warm back end


VST – Phase I - Penn

• Focus on analog performance tests and preparation for CCD readout– Noise

• Channel by channel• Power supply feedthrough• Current source feedthrough

– Dynamic range• Matching input to ADC, use all (well, almost all) 17 available bits

– Crosstalk – spatial (e.g. left – right)– Crosstalk – temporal (e.g. large pulse memory)– Timing variations

• Reset and clamp timings• Placement of ramp up/down wrt input pulse• Settling time at ADC

– Assemble pieces for CCD readout• Cables• Adapters• ????

– Operate with CCD emulator


VST – Phase I - Paris

• Primary focus on ASPIC and CABAC bench tests– Mostly dedicated chip test fixtures and software tools– Cold ASPIC test boards– Dedicated ADC board (same ADCs, different form factor)

• Secondary focus on VST hardware comparison with bench test system(s)– One RCM, full pair of BEBs, one FEB (more possible)– Extensive collection of CCD characterization tools available for use either with

bench or VST hardware


VST – Phase 1.5

• CCD Emulator being developed by BNL– Image pattern stored on emulator– 16 bit DAC resolution– Extracted via proper clock pattern from

Geary 4 channel controller – A good way to get ready for the real

challenge


VST – Phase I.7

• Attach to CCD and read an image– Either at Harvard or BNL – TBD– Initially all warm electronics– Secondarily, cold FEB (to get to expected noise performance by avoiding extra

cabling from CCD through cryostat wall)• Needs significant mechanical effort• Needs some level of image software – maybe Phase 1.5 level sufficient


VST Phase II

• New chip set (ASPIC3, CABAC1)• New FEB• New backend (BEB, backplane, RCM)• At some point in phase II add in a TCM mockup• Repeat all Phase I analog tests and digital tests

– Need appropriate firmware– Need CCS compliant software

• Repeat emulator tests– Need image software

• Repeat CCD tests– Expand from simple schemes in 1.7 to LSST like schemes (e.g. full cold RTM

assemblies even if only two FEBs are populated)• Test monitoring and diagnostic modes• Test full raft operation (look for any system issues) albeit with only a few CCDs into CDS• Verify temperature cycling and temperature stress survival• Test temperature measurement and control system• Possibly bring in prototype power distribution system• Produce one or more RTM assemblies for contamination testing


VST – Phase III

• Based on pre-production boards (presumably very similar to VST Phase II boards)• Full electrical and CCD tests• Near final (but still simplified) CCS code• Multiple full RTMs• Cold RTM and cold RCC• Additional contamination studies• Final temperature cycling and stress tests• Test with pre-production TCM and PDS (Power Distribution System)• Verify assembly and test procedures

End of Presentation

Documents

LSST Electronics Review BNL January 25-26, 20121 LSST Electronics Review BNL January 25-26, 2012 Electronics Development Plan and Vertical Slice Test (VST)