LSST electronic workshop BNL January 25-26, 2012 Measurements & Near Terms Plan in Paris Pierre Antilogus BNL, Raft Electronic Workshop January 26 th 2012

LSST electronic workshop • BNL • January 25-26, 2012

Measurements & Near Terms Plan in Paris

Pierre Antilogus

BNL, Raft Electronic Workshop January 26th 2012

Plan

• Test activities in Paris• ASPIC II tests

• ASPIC II final measurements / input for ASPIC III design• ASPIC II long cold run

• Clocking ASICs tests• Test of the TEST_0 ASIC• Test of the SCC• CABAC characterization bench construction

• CCD readout with (part of) LSST electronic

• Paris Working plan in 2012 • ASPIC • CABAC• Contribution to the version II LSST electronic design

ASPIC II test benches & characterisation

Vanessa Tocu & Hervé Lebbolo

First CD1 rehersall 17th Oct 2011 : ASPIC (on the left) & CABAC (on the right )

Fall 2011 – spring 2012 : second round of ASPIC II cryogenic tests to prepare ASPIC III design

, J.Jeglot , C.Juramy + H.Lebbolo , D.Martin , Ph.Repain , V.Tocut

ASPIC II : final measurements

Since December 2011 we are working on our “IR cryostat” to prepare the “ASPIC long cold run” at the same time the left over ASPIC II measurements are performed in our other cryostats at LAL and LPNHE.For this purpose we :-re-filled our cryo-cooling system for ~ -120 C ( N2 circulation deactivated) -Had the vacuum pump associated to this setup revised -Ordered a new vacuum gauge in replacement of a “tired” one Right now a few updates in our Labview software associated to the ASPIC test BE board is underway for an automatic run , and regular file status archive (xtalk , linearity , gain , noise will be monitored ) .Goal : start the run as early as possible in February.

ASPIC II long cold Run

Clocking & Bias ASICs tests

TEST_0 tests

TEST_0 setup in preparation :-We should be able to start the chip characterization byend of February-Schedule for the long test run in the cold not “frozen” yet, but the aim is to start it ASAP ( March-April )-The TEST_0 should have been characterized at # T , and run for 2-3 weeks in cold before the CABAC is submitted in April 2012

9

TEST_0 test bench

TEST_0 PCIDIO 96

HostProgrammablePower Supply

RelayBoard

prog

usb

Scope

Vds, Vgs

AmmeterKeithley

Id, Ib

Vbias,..

SCC setups & CABAC test bench preparation

2 remarks : - We have in hand the SCC , the previous generation of Clock ASIC

for LSST ( 3 chips are in Paris ) - The CABAC clocks are implemented in a scheme close to the SCC

one.From there we have implemented a few tests plan :

- Even if the SCC has default ( DAQ issue), to run it during CABAC design has been instructive. (SCC test version 0 , fall 2011)

- As we prepare the setup to qualify the CABAC chips , the SCC can be used to qualify this test bench, which will allow us to be more reactive when the CABAC_0 will return from production (SCC test version 1, spring 2012 )

- We plan to try to use the SCC to clock CCD before the summer

11

SCC Tests (version 0 , fall 2011)

SCCTest FE

Capacitors

Logical Analyser

&Pattern

Generator(=RCM Test

Board)

Host

hot

Scopes

Fall 2011 : RTB + SSC testC.Juramy , M.Dhellot (SCC board) ,S.Russo( RTB)

RCM Test Board

SCC Test Board

4 phases // clock test

SCC : Preliminary results 0

13

Frequency : 500kHzNo loadAmplitude 10VRise time : 6.8ns fall time : 14nsRoom temperature

14


Load : 68pFTr : 26nsTf : 25ns10V500kHzRoom tempI = 26mA

15


Period 80µs (12.5kHz) amplitude : 10VLoad : 40nFRise : 2.75µs fall : 2.7µs i = 145mA

16


C = 20nf (*4)Rise : 5.4µs fall : 4.7µsA : 10V F = 12.5kHzI = 148mARipple : ~1.5Vcc

CABAC characterization bench

Since fall 2011 we are implementing a dedicated set of boards & FPGA software to serve for the characterization of the CABAC _0 . Like for the equivalent setup for the ASPIC , this setup :

- Will allow a precise characterization of the CABAC - Should be the basis for the future full production test

This setup should be operational before the spring 2012 and part of it will be qualified , through a characterization of the SCC.

18

CABAC test bench ( & SCC test version 1)

CABACTest FE

Capacitors

AnalogDigital

DaughterBoard

FPGAEvaluation

Board

Ethernet/usb

Host

hot

Hot/cold

hot

Scopes

CABAC Tests ( & SCC Test version 1 )

19

• Programmation (& read back):– Clocks rise time (8*8 bits DAC)– OD level ( 2*8 bits DAC)*2 (exposure & readout)– Biases level : 5*8 bits DAC (RD, GD, OG, spare*2)– Muxout : 2*(1 from 16 input)– Mux enable

• Send Clock timing (8 LVDS signals) + RO mode

• Readout : – CK : 2*4 channels waveform digitizer– OD & Biases : 8*18 bits 1Ms/s ADC – Mux out : 2*16 bit 6Ms/s ADC

20

ADC série 18b 1MS AD7982 (x13)

CABAC Tests Bench

AlteraEP3C120

Ethernet GEDEK

SMA in

OD

Mux Out<1..0>

OD<7..0>

Spare<1..0>GD OG RD

13*SDO

Cabac Prog

HSMCBank2 CMOS32/40

Analog daughter board FPGA cyclone III dev board

2 SCOPES 4 channels + external trigger (WaveAce224)

Trigger (SMA out)

18 pins lvds

CNVSCK

Trigger_in/out

ADC série 16b 6MS AD7625 (x2)

2*SDO2*CNVSCK*2

HSMCBank3LVDS

18/20 pairs

2

15

12

6

DAC 0

LDAC SCLK CLR SYNC

SDINDAC nDAC 6SDO

BIAS

6

MUX

TIMING CKEXP/RO

8p 4p

TIMING ASPIC

CK

Dual DAC AD5429

8

CABAC output

CABAC input ASPIC

LVDSCMOSAspic

Prog

1

6

6

4

CABAC Tests

• OD : – Impedance– Xtalk– Exposure / Readout modes level, linearity, noise– Clocks immunity

• Biases :– Level, linearity, noise– Impedance– Clocks & OD immunity

• Clocks : – Rise & fall times, Current linearity– Xtalk– Frequency

• Power consumption21

CCD readout with LSST electronic

Back End withLSST ADC-18 bits-AD7982Designed for ASPIC test

Back End Control GUI& image file production

SDSU is used to provide the clocks/bias to the CCD

Spring 2011 : CCD readout with ASPIC II warm (1/2) C.Juramy , D.Martin (Back End / synchro), P.Bailly (Control GUI) spring 2011 :readout of pre-proto e2v 217 with warm ASPIC II

Black box with light sources

e2v 217-10

CCD+ASPIC : Bias Frame

CCD+ASPIC : Flat field Frame

Readout of CCD with ASPIC II operational ,next step underway includes noise/xtalk optimization/studies with ASPIC II inside the cryostat

Spring 2011 : CCD readout with ASPIC II warm (2/2) C.Juramy , D.Martin (Back End / synchro), P.Bailly (Control GUI)

Fall 2011: Cryostat upgrade for CCD proto readout with LSST like electronic in the cold

C.Juramy , H.Lebbolo, Ph.Repain,D.Vincent

Pre-proto e2v 217 in a mount compatible to a spare physical CCD250 mounting fixture

ASPIC II Small cold board

Fall 2011-Jan 2012 : Cryostat upgrade for CCD proto readout with LSST like electronic in the cold

C.Juramy , H.Lebbolo, Ph.Repain,D.Vincent

ASPIC Test BE

Extended cryostat qualified In december 2011 : - CCD temperature can go down to -120 C-With the current ASPIC board cold connection , with the CCD at -100 C , the ASPIC is at -85 C

CCD bias CCD clock

Bias and Clock plug in the cryostat , will move to one of the SUB-D for the ev250

ASPIC output

First images of the « bad side » of the 217 with and without our Fe55 source ( First images last Friday)

Noise optimization under way

ASPIC II Configuration :-2 channels connected to the ccd e2v 217 ( CCD with 2 outputs) -1 channel , connected to the outside ( signal injection , “system noise” study …) -All other channels grounded ( for ASPIC noise study / complementary studies )

Hervé Lebbolo CCD test bench 28

CCD 217 test bench n°0CC

D

San Diego

Aspic cold FE (LAL)

BEB(LPNHE)

cold

SynchroClocks + bias

Host

17/01/2012


CCD 217 test bench n°1CC

D Aspic cold FE (LAL)

BEB(LPNHE)

cold

SCC Hot test board

SCC Hot test board

RTB

Xilinx eval board

Power Supply

Host

Synchro

17/01/2012


CCD250 test bench n°0CC

D

SCC Hot test board

SCC Hot test board

Custom Aspic2 FE LSSTBEB

RTB

cold

Xilinx eval board

Power Supply

Host

17/01/2012



D

Custom aspic2 FE

LSSTBEB

RTB

cold

Xilinx eval board

CABAC 0Cold board

Host

17/01/2012



D CABAC 0 / ASPIC 3

Cold board

LSST or CustomBEB

RTB

cold

Xilinx eval board

Host

17/01/2012

2012 working plan in Paris

IN2P3 Manpower on CCD & CCD readout

ASPIC in 2012 (1 / 2 )

- ASPIC II : end of test :- conclude on a few open questions (noise vs. T , memory effect,..) done by end of

February in the upgraded CCD cryostat in // of CCD readout in LPNHE and also in LAL cryostat if needed.

- long run cryotest : get ready in 2011 to launch it (end) January 2012, run up to summer- CCD readout with ASPIC II with minimal noise setup ( in cryostat, CCD 217 , compatible

CCD 250 ) setup operational with CCD217 , system noise reduction underway (January) , setup should be qualified before end February for CCD250 (prior Claire “disappears” for ~2-3 months) .

This is a top priority test to validate ASPIC III requirement/design ( Noise issue , Noise versus readout speed / RC value / RC tuning request …) and the easiest/fastest proof of concept we can do for the LSST Sensor + ASPIC (=core of the readout system).

ASPIC in 2012 (2 /2 )

-ASPIC III :

- the Version 1 document of the ASPIC III requirements will be ready end of January 2012- the implementation will start end of February 2012- in the second quarter of March a face to face meeting of the electronic group should sold

out all the left over questions on the requirements & requested improvement , but the goal is to have the remaining issues sold out by end of February ( complementary ASPIC II measurements , gain requirement from CCD R&D output ).

- independently of the VST, in Paris CCD + ASPIC II + Test BE + SDSU , could provide the first noise measurement of CCD250 with an ASPIC II : such measurement is mandatory prior to the ASPIC III submission.

- submission before the summer (May 2012) , test can start early fall.

CABAC in 2012

CABAC-Test_0 :

- Reception in February , test setup should be ready by then .- First test in our old circulation cryostat - May start a long run test in the same cryostat than ASPIC II before June … to be studied

-CABAC 0 : - complete implementation and submit it :

- The goal is to submit it in February- tests can start this summer ( qualification setup should be ready ~ spring)

- ASICs risks : - Design issue : need to do highly controlled tests , including with CCD- Aging issue , in particular due to running in the cold : a worry … and not easy to fully

guaranty ( aging may takes time … but LSST = ~ 10-15 years ) So this is and will be our main priority : get the best and safest ASICs as possible

- Vertical Slice test : - We are not on the first front with it at the moment ( we are not running it /

contributing to its debugging right now ) , still our CCD test bench could run it , with 2 FE board in the cold connected to a CCD when needed.

- S.Russo is investigating it in detail , including at the FPGA code level, on top of preparing us to run it if needed, this is needed to :

- prepare/contribute to the next version of the LSST raft electronic RCM - use part of its hardware (BE/ADC ) in our CCD test bench , with our “flexible”

setup.

And what else ? (1/3)Contribution to the LSST electronic Version II


- Due to our work on the ASICs and on the CCD we are developing an expertise on “running the thing” , this work on “diagnostic” should be passed to the Vertical Slice/raft developments and tests.

-Characterization of our ASICs , and even of our full LSST chain , request more flexibility , than what will be needed in our final working system : We have dedicated boards / FPGA/ simulation work in Paris . For the ASICs characterizations we need a test readout system , able to diagnose the chip including reading a CCD. This system needs to be highly flexible to merge ASICs generations , boards , clocking source …. Up to now we used for this the Back End Test board for the ASPIC I & II . Now with the RTB and associated board(s) , we go one step further to be able to use SCC , ASPIC x , CABAC x , with the goal to have a test system with a high compatibility with the final system ( FPGA code…) .

-For both reasons , and the associated expertise , we are willing to be involved in the design , construction and test of the version II of the RCM.


For a direct contribution inside the Electronic team to the version II of the LSST electronic we have identified the following people on the French side :

- Claire : Diagnostic ( ASICs , CCD ) - Hervé : global electronic design & CABAC coordination- Pierre: Scientific contribution ( = worries & requirements)- Stefano: RCM Version II design ( including FPGA development )- Vanessa : ASPIC coordination

Documents

LSST electronic workshop BNL January 25-26, 2012 Measurements & Near Terms Plan in Paris Pierre Antilogus BNL, Raft Electronic Workshop January 26 th 2012