Lecture 18: VLSI Design Styles - University Of Illinois–Gate Arrays and Sea of Gates –Cell-based Design –Full Custom Design ... SOG and Gate Array Cell Layouts ECE 425 Slide

CMOS VLSI DesignCMOS VLSI Design 4th Ed.

Lecture 18:

VLSI Design Styles

Slides courtesy of Deming Chen


Outline Overview

– Microprocessor/DSP

– Programmable Logic

– Gate Arrays and Sea of Gates

– Cell-based Design

– Full Custom Design

– System on a Chip

– Intellectual Property (IP)

Reading

– Part of the lecture is coming from Text 14.3

ECE 425 Slide 2


Where are we?

Throughout the course, we’ve been increasing the

scope of the modules

– Transistors and gates

– ALUs, multipliers, memories

– Now, on to discussions of full-scale chip design

Today’s lecture is intended as a bridge between

what we’ve covered and where we’re going

– Different design styles for chips

Later, we’ll start talking about design flow, CAD tools,

synthesis and high-level modeling, etc.

ECE 425 Slide 3


Design Methodologies

Different design methodologies provide varying

degrees of freedom, cost and performance:

– Microprocessor/DSP

– Programmable Logic (FPGA and CPLD)

– Gate array, sea of gates, and structured ASIC

– Standard Cell

– Custom

– System-on-chip (core-based)

ECE 425 Slide 4


Microprocessor/DSP

Standard microprocessor or digital signal processor

(DSP) are very practical and usually offer great

flexibility

Systems can be upgraded in the field through

software patches

Off-the-shelf processors with wide range of clock

speeds, memory sizes, and analog I/O capability

Embedded processors are available for system-on-

chip design methodology

May not be most efficient in terms of cost, speed and

power dissipation

ECE 425 Slide 5


Benefit of Hardware SpecializationHardware Specialization: Efficiency vs. Flexibility"

10

© 2012 Altera Corporation—Public

The Dilemma: Flexibility vs. Efficiency

16

Source: “High-performance Energy-Efficient Reconfigurable Accelerator Circuits for the Sub-45nm Era” July 2011

by Ram K. Krishnamurthy, Circuits Research Labs, Intel Corp.

MO

PS

/mW

Programmable Processing

Source: Ram K. Krishnamurthy, Intel Corp.


Gaps Are Widening Design Productivity Gap

• Increasing complexity of designs

• Reduced time-to-market

Verification/Predictability Gap

• Delayed final tapeout

Quality Gap

• RTL design focusing on limited

architecture alternativesTechnology Scaling

Pro

du

ctiv

ity/C

om

ple

xit

y

Design

Gap

Design

Productivity (20-25%*)

Gates/cm2

Moore’s Law (59%*)

* Compound Annual Growth Rate

Source: Semico Research Corp.

Source: EETimes.comSource: Pittsburgh Digital Greenhouse


One Case Study

Comparative study on Monte Carlo option pricing

Data for a single option pricing, using 524,288 simulation paths

Source: “Reconfigurable Computing in the Multi-Core Era,” Khaled Benkrid, HEART’2010.


Logic Synthesis

Place & Route

High-level Synthesis

datapathcontroller

Behavior level

RT level(VHDL, Verilog)

Gate level

(netlist)

C, C++, SystemC

System level Design spec. in high-level languages

SW/HW Co-design

Levels of

Abstraction

Chips

The Trend: High-level Synthesis (HLS)

• 10X code reduction

• 1000X simulation

time reduction

[Source: NEC]


Two Major Types of Programmable

Logic

FPGA (field programmable gate array)

– fine-grained logic cells

– high logic density

– good design flexibility

CPLD (complex programmable logic device)

– coarse-grained two-level AND-OR programmable

logic arrays (PLAs)

– fast and more predictable delay

– simpler interconnect structures

Low or no nonrecurring engineering cost (NRE)

ECE 425 Slide 10


A Generic FPGA

Architecture

ECE 425 Slide 11

Programmable

IO

KLUTInputs D FF

Clock

Out

BLE# 1

BLE# N

NOutputs

I

Inputs

Clock

I

N

Programmable

Logic (CLB)

Programmable

Routing


An Implementation of a 4-input Look-

up Table (4-LUT)

ECE 425 Slide 12

Out = f (in0, in1, in2, in3)

In0 In1 In2 In3

Out

…

16

SRAMs


One Commercial FPGA, Altera Stratix II

ECE 425 Slide 13


Building Blocks of CPLD: PLA

Structure

ECE 425 Slide 14

(k, m, p)-

PLA


One Commercial CPLD, Altera MAX7000

ECE 425 Slide 15Each LAB can be treated as a special (36,80,16)-PLA


Gate Array and Sea of Gates

Another way of lowering NRE

Construct a common base array of transistors

Personalize the chip by altering the metallization (metal and via masks)

Newer and modern versions are called Structured ASIC

Vendors stock master or base wafers that have been processed up to the polysilicon gate layer

Contacts and metallization are then specified on a per-design basis

Wafer cost reduced by producing many base wafers for a variety of different chips

Packaging cost reduced by using standard packages and pinouts

Test and production costs are reduced by reusing common test fixtures

ECE 425 Slide 16


Sea of Gates (SOG) Floorplan

ECE 425 Slide 17


SOG and Gate Array Cell Layouts

ECE 425 Slide 18

(a) SOG (b) Gate Array

Gate array: array of transistors not continuous, can be grouped and

perhaps individually sized


SOG Programming Example

ECE 425 Slide 19

3-input NAND gateCustom design


Cell-Based Design

Design composed out of a set of pre-designed

blocks, called standard cells

– Cells often simple gates/latches, can be more

complex

– Cells pre-tested and pre-characterized

– Companies offer standard cell libraries for use

with their fabrication and CAD technologies

• Amortize the effort of designing the cell library

over all the designs that use it

ECE 425 Slide 20


Standard-Cell Design

Organize cells into rows to make placement easier

– Require that all cells have the same height

ECE 425 Slide 21


Full-Custom Design

What we’ve been doing so far

Designer specifies size, position, connections of every device in

a circuit, down to the mask level

Gives highest performance and device density

Disadvantages:

– Very tedious and complex

– Long design times

– Higher design cost

– Error prone

Nowadays, this design style is used only for parts of state-of-

the-art designs where performance and area are pushed to the

limits (to achieve an A grade).

ECE 425 Slide 22


System-on-a-Chip (Platform-Based)

Motivation: Even with synthesis from VHDL/Verilog, design effort

for modern chips is very large.

Observation: Many VLSI systems incorporate similar

components

– ALUs

– Memory Interfaces

– RAM blocks

– DSP modules

Idea: Provide a set of cores (Intellectual Properties) that perform

common functions, let designers use them

– Eliminate the need to re-design

– Becomes worth the effort to heavily optimize cores

ECE 425 Slide 23


Intellectual Property (IP)

Building block components (roughly equivalent terms)– Macros, cores, IPs, virtual components (VCs)

Examples– Microprocessor core, A/D converter, Digital filter, Audio

compression algorithm

Three types of IP blocks– Hard (least flexible)

– Firm

– Soft (most flexible)


IPs

SoC

System

Hardware Software

OS ApplicationProcessors Memories

IOs

Consumer

Wireless

Set-top box

Smart devices

……

ASICs


Hard IP

Delivered in physical form (e.g., GDSII file)

Fully– Designed

– Placed and routed

– Characterized for timing, power, etc.

Tied to a manufacturing process– Actual physical layout

– Fixed shape

Complete characterization– Guaranteed performance

– Known area, power, speed, etc.

No flexibility


Fixed Schematics and Layout

A

B

C

Ground

Power

A-Input

B-InputData Out

Hard

Macros

Schematic of a NAND gate Layout of a NOR gate


Hard IP Examples and

Constraints

A microprocessor core – PowerPC, ARM

AMS (analog/mixed-signal) blocks– ADC, DAC, filter

A phase-locked loop (PLL)

A memory block design

Features– Deeply process dependent

– Stricter performance requirements

– Electrical constraints, such as capacitance, resistance, and inductance ranges

– Geometric constraints, such as symmetry, dimension, pin location, etc.

– Need to provide interface for functional and timing verification


Soft IP

Delivered as synthesizable RTL HDL code (e.g., VHDL or Verilog) – can be SystemC/C/C++ code now.

Performance is synthesis and process dependent

Synthesizable Verilog/VHDL/SystemC/C/C++

Synthesis scripts, timing constraints

Scripts for testing issues

– Scan insertion, ATPG (automatic test pattern generation), etc.


ENTITY example IS

PORT(clock, a, b, sel:IN BIT; d:OUT BIT);

END example;

ARCHITECTURE behavior OF example IS

BEGIN

PROCESS (clock)

IF (clock’EVENT AND clock=‘1’) THEN

IF (sel=‘1’) THEN d<=a OR b;

ELSE d<=a AND b;

END IF;

END IF;

END PROCESS;

END behavior;

Soft IP Example in VHDL


Firm IP Blocks

Intermediate form between hard and soft IP

– Some physical design info to supplement RTL

– RTL or netlist or mixture of both

– More (or less) detailed placement

– Limited use beyond specified foundry


Understand IPs

The quality of IPs and support will be the key to the

success of the IP business

Need to pay much attention on software IP issues

Need application and system design expertise

Core-based design is effective on IP/core integration

Need to develop a combining platform- and core-

based design methodology/environment for system

designs


Issues with IPs

Intellectual Property: How do you keep someone from stealing

all the work you put into a core design?

– More of a problem with the soft and firm core methods

– Many solutions rely on encryption of source code

Interfaces: If cores don’t work well together, may take more

effort to connect them than you save by using them

– Standards (busses, etc.)

– Clever design

Testing:

– Can’t get to IP I/O pins from chip I/O’s

– Different cores may use different DFT strategies

ECE 425 Slide 33


Designers’ Technical

Concerns on IP Reuse

Is the IP source (provider) reliable?

How can I make sure the functional correctness of the IP?

How much effort do I have to invest in test-bench development

for design verification with reused IP?

What if I need to modify part of IP design?

What if the final timing is not satisfied due to the IP?

What’s the risk of the design project due to any possible defect

caused by the IP?

What’s the worst scenario when reusing the IP and what are the

damage control plan?


Case Study: Portfolio of ARM IPs


Memory IP from ARM


System IP from ARM


Standard Cell Logic IP from ARM (1)


Standard Cell Logic IP from ARM (2)


Processor IP from ARM


Comparison of CMOS Design Methods

ECE 425 Slide 41


Design Decision Tradeoffs

ECE 425 Slide 42


Summary

Different design styles with tradeoff among

– Time to market, cost, performance, area, power…

Picking the right style depends on

– Market, volume, form factor, cost, performance…

IP-based design is dominating

SoC becomes the leading design technology

Next lecture

– VLSI CAD Tools

ECE 425 43

Documents

Lecture 18: VLSI Design Styles - University Of Illinois–Gate Arrays and Sea of Gates –Cell-based Design –Full Custom Design ... SOG and Gate Array Cell Layouts ECE 425 Slide