Click here to load reader

Lecture 11: Sequential Circuit Design - Harvey Mudd · PDF fileLecture 11: Sequential Circuit Design. 11: Sequential Circuits 2CMOS VLSI DesignCMOS VLSI Design 4th Ed. ... lect11-seq.ppt

  • View
    217

  • Download
    2

Embed Size (px)

Text of Lecture 11: Sequential Circuit Design - Harvey Mudd · PDF fileLecture 11: Sequential Circuit...

  • Lecture 11: Sequential Circuit Design

  • 11: Sequential Circuits 2CMOS VLSI DesignCMOS VLSI Design 4th Ed.

    OutlineSequencingSequencing Element DesignMax and Min-DelayClock SkewTime BorrowingTwo-Phase Clocking

  • 11: Sequential Circuits 3CMOS VLSI DesignCMOS VLSI Design 4th Ed.

    SequencingCombinational logic output depends on current inputs

    Sequential logic output depends on current and previous inputs Requires separating previous, current, future Called state or tokens Ex: FSM, pipeline

    CL

    clk

    in out

    clk clk clk

    CL CL

    PipelineFinite State Machine

  • 11: Sequential Circuits 4CMOS VLSI DesignCMOS VLSI Design 4th Ed.

    Sequencing Cont.If tokens moved through pipeline at constant speed, no sequencing elements would be necessaryEx: fiber-optic cable Light pulses (tokens) are sent down cable Next pulse sent before first reaches end of cable No need for hardware to separate pulses But dispersion sets min time between pulses

    This is called wave pipelining in circuitsIn most circuits, dispersion is high Delay fast tokens so they dont catch slow ones.

  • 11: Sequential Circuits 5CMOS VLSI DesignCMOS VLSI Design 4th Ed.

    Sequencing OverheadUse flip-flops to delay fast tokens so they move through exactly one stage each cycle.Inevitably adds some delay to the slow tokensMakes circuit slower than just the logic delay Called sequencing overhead

    Some people call this clocking overhead But it applies to asynchronous circuits too Inevitable side effect of maintaining sequence

  • 11: Sequential Circuits 6CMOS VLSI DesignCMOS VLSI Design 4th Ed.

    Sequencing ElementsLatch: Level sensitive a.k.a. transparent latch, D latch

    Flip-flop: edge triggered A.k.a. master-slave flip-flop, D flip-flop, D register

    Timing Diagrams Transparent Opaque Edge-trigger

    D

    Flop

    Latc

    h

    Q

    clk clk

    D Q

    clk

    D

    Q (latch)

    Q (flop)

    D

    Flop

    Latc

    h

    Q

    clk clk

    D Q

    clk

    D

    Q (latch)

    Q (flop)

  • 11: Sequential Circuits 7CMOS VLSI DesignCMOS VLSI Design 4th Ed.

    Latch DesignPass Transistor LatchPros+ Tiny+ Low clock load

    Cons Vt drop nonrestoring backdriving output noise sensitivity dynamic diffusion input

    D Q

    Used in 1970s

  • 11: Sequential Circuits 8CMOS VLSI DesignCMOS VLSI Design 4th Ed.

    Latch DesignTransmission gate+ No Vt drop- Requires inverted clock D Q

  • 11: Sequential Circuits 9CMOS VLSI DesignCMOS VLSI Design 4th Ed.

    Latch DesignInverting buffer+ Restoring+ No backdriving+ Fixes either

    Output noise sensitivity Or diffusion input

    Inverted output

    D

    X Q

    D Q

  • 11: Sequential Circuits 10CMOS VLSI DesignCMOS VLSI Design 4th Ed.

    Latch DesignTristate feedback+ Static Backdriving risk

    Static latches are now essentialbecause of leakage

    QD X

  • 11: Sequential Circuits 11CMOS VLSI DesignCMOS VLSI Design 4th Ed.

    Latch DesignBuffered input+ Fixes diffusion input+ Noninverting

    QD X

  • 11: Sequential Circuits 12CMOS VLSI DesignCMOS VLSI Design 4th Ed.

    Latch DesignBuffered output+ No backdriving

    Widely used in standard cells+ Very robust (most important)- Rather large- Rather slow (1.5 2 FO4 delays)- High clock loading

    Q

    D X

  • 11: Sequential Circuits 13CMOS VLSI DesignCMOS VLSI Design 4th Ed.

    Latch DesignDatapath latch+ smaller+ faster- unbuffered input

    Q

    D X

  • 11: Sequential Circuits 14CMOS VLSI DesignCMOS VLSI Design 4th Ed.

    Flip-Flop DesignFlip-flop is built as pair of back-to-back latches

    D Q

    X

    D

    X

    Q

    Q

  • 11: Sequential Circuits 15CMOS VLSI DesignCMOS VLSI Design 4th Ed.

    EnableEnable: ignore clock when en = 0 Mux: increase latch D-Q delay Clock Gating: increase en setup time, skew

    D Q

    Latc

    h

    D Q

    en

    en

    Latc

    hDQ

    0

    1

    en

    Latc

    h

    D Q

    en

    DQ

    0

    1

    enD Q

    en

    Flop

    Flop

    Flop

    Symbol Multiplexer Design Clock Gating Design

  • 11: Sequential Circuits 16CMOS VLSI DesignCMOS VLSI Design 4th Ed.

    ResetForce output low when reset assertedSynchronous vs. asynchronous

    D

    Q

    Q

    reset

    D

    Q

    Dreset

    Q

    Dreset

    reset

    reset

    Synchronous Reset

    Asynchronous R

    esetS

    ymbol F

    lop

    D Q

    Latc

    h

    D Q

    reset reset

    Q

    reset

  • 11: Sequential Circuits 17CMOS VLSI DesignCMOS VLSI Design 4th Ed.

    Set / ResetSet forces output high when enabled

    Flip-flop with asynchronous set and reset

    D

    Q

    reset

    set reset

    set

  • 11: Sequential Circuits 18CMOS VLSI DesignCMOS VLSI Design 4th Ed.

    Sequencing MethodsFlip-flops2-Phase LatchesPulsed Latches

    Flip-FlopsFl

    opLa

    tch

    Flop

    clk

    1

    2

    p

    clk clk

    Latc

    h

    Latc

    h

    p p

    1 12

    2-Phase Transparent Latches

    Pulsed Latches

    Combinational Logic

    CombinationalLogic

    CombinationalLogic

    Combinational Logic

    Latc

    h

    Latc

    h

    Tc

    Tc/2

    tnonoverlap tnonoverlap

    tpw

    Half-Cycle 1 Half-Cycle 1

  • 11: Sequential Circuits 19CMOS VLSI DesignCMOS VLSI Design 4th Ed.

    Timing Diagrams

    Flop

    A

    Y

    tpdCombinational

    LogicA Y

    D Q

    clk clk

    D

    Q

    Latc

    h

    D Q

    clk clk

    D

    Q

    tcd

    tsetup thold

    tccq

    tpcq

    tccq

    tsetup tholdtpcq

    tpdqtcdqLatch/Flop Hold Timethold

    Latch/Flop Setup Timetsetup

    Latch D->Q Cont. Delaytcdq

    Latch D->Q Prop. Delaytpdq

    Latch/Flop Clk->Q Cont. Delaytccq

    Latch/Flop Clk->Q Prop. Delaytpcq

    Logic Cont. Delaytcd

    Logic Prop. Delaytpd

    Contamination and Propagation Delays

  • 11: Sequential Circuits 20CMOS VLSI DesignCMOS VLSI Design 4th Ed.

    Max-Delay: Flip-Flops

    F1 F2

    clk

    clk clk

    Combinational Logic

    Tc

    Q1 D2

    Q1

    D2

    tpd

    tsetuptpcq

    ( )setupsequencing overhead

    pd c pcqt T t t +

  • 11: Sequential Circuits 21CMOS VLSI DesignCMOS VLSI Design 4th Ed.

    Max Delay: 2-Phase Latches

    Tc

    Q1

    L1

    1

    2

    L2 L3

    1 12

    CombinationalLogic 1

    CombinationalLogic 2

    Q2 Q3D1 D2 D3

    Q1

    D2

    Q2

    D3

    D1

    tpd1

    tpdq1

    tpd2

    tpdq2

    ( )1 2sequencing overhead

    2pd pd pd c pdqt t t T t= +

  • 11: Sequential Circuits 22CMOS VLSI DesignCMOS VLSI Design 4th Ed.

    Max Delay: Pulsed Latches

    Tc

    Q1 Q2D1 D2

    Q1

    D2

    D1

    p

    p p

    Combinational LogicL1 L2

    tpw

    (a) tpw > tsetup

    Q1

    D2

    (b) tpw < tsetup

    Tc

    tpd

    tpdq

    tpcqtpd tsetup

    ( )setupsequencing overhead

    max ,pd c pdq pcq pwt T t t t t +

  • 11: Sequential Circuits 23CMOS VLSI DesignCMOS VLSI Design 4th Ed.

    Min-Delay: Flip-Flops

    holdcd ccqt t t CL

    clk

    Q1

    D2

    F1

    clk

    Q1

    F2

    clk

    D2

    tcd

    thold

    tccq

  • 11: Sequential Circuits 24CMOS VLSI DesignCMOS VLSI Design 4th Ed.

    Min-Delay: 2-Phase Latches

    1, 2 hold nonoverlapcd cd ccqt t t t t CL

    Q1

    D2

    D2

    Q1

    1

    L1

    2

    L2

    1

    2

    tnonoverlap

    tcd

    thold

    tccq

    Hold time reduced by nonoverlap

    Paradox: hold applies twice each cycle, vs. only once for flops.

    But a flop is made of two latches!

  • 11: Sequential Circuits 25CMOS VLSI DesignCMOS VLSI Design 4th Ed.

    Min-Delay: Pulsed Latches

    holdcd ccq pwt t t t + CL

    Q1

    D2

    Q1

    D2

    p tpw

    p

    L1

    p

    L2tcd

    thold

    tccq

    Hold time increased by pulse width

  • 11: Sequential Circuits 26CMOS VLSI DesignCMOS VLSI Design 4th Ed.

    Time BorrowingIn a flop-based system: Data launches on one rising edge Must setup before next rising edge If it arrives late, system fails If it arrives early, time is wasted Flops have hard edges

    In a latch-based system Data can pass through latch while transparent Long cycle of logic can borrow time into next As long as each loop completes in one cycle

  • 11: Sequential Circuits 27CMOS VLSI DesignCMOS VLSI Design 4th Ed.

    Time Borrowing Example

    Latc

    h

    Latc

    h

    Latc

    h

    Combinational Logic CombinationalLogic

    Borrowing time acrosshalf-cycle boundary

    Borrowing time acrosspipeline stage boundary

    (a)

    (b) Latc

    h

    Latc

    hCombinational Logic CombinationalLogic

    Loops may borrow time internally but must complete within the cycle

    1

    2

    1 1

    1

    2

    2

  • 11: Sequential Circuits 28CMOS VLSI DesignCMOS VLSI Design 4th Ed.

    How Much Borrowing?

    Q1

    L1

    1

    2

    L2

    1 2

    Combinational Logic 1Q2D1 D2

    D2

    Tc

    Tc/2 Nominal Half-Cycle 1 Delay

    tborrow

    tnonoverlap

    tsetup

    ( )borrow setup nonoverlap2cTt t t +

    2-Phase Latches

    borrow setuppwt t t

    Pulsed Latches

  • 11: Sequential Circuits 29CMOS VLSI DesignCMOS VLSI Design 4th Ed.

    Clock SkewWe have assumed zero clock skewClocks really have uncertainty in arrival time Decreases maximum

Search related