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3/2/2016 SREEHARI RAO PATRICHIP DESIGN CENTER NITW

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MOSFET CURRENT-VOLTAGECHARACTERISTICS

& SS MODEL

Dr Sreehari Rao PatriECE Department, N.I.T.Warangal

[email protected]


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MOS Device Structure


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NMOS and PMOS with Well


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MOS Symbols


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Etymology

The 'metal' in the name is now often amisnomer because the previously metalgate material is now a layer of polysilicon

Previously aluminium was used as the gatematerial until the 1980s when polysiliconbecame dominant, owing to its capability to form self-aligned gates.

IGFET is a related, more general termmeaning insulated-gate field-effecttransistor, and is almost synonymous with

MOSFET, though it can refer to FETs with agate insulator that is not oxide.


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Composition

Usually the semiconductor of choice is silicon

But some chip manufacturers, most notably IBM, havebegun to use a mixture of silicon and germanium (SiGe) inMOSFET channels.

Unfortunately, many semiconductors with better electricalproperties than silicon, such as gallium arsenide, do notform good semiconductor-to-insulator interfaces and thusare not suitable for MOSFETs.

However there continues to be research on how to createinsulators with acceptable electrical characteristics onother semiconductor material.

http://en.wikipedia.org/wiki/Aluminiumhttp://en.wikipedia.org/wiki/Silicon_germaniumhttp://en.wikipedia.org/wiki/Silicon_germaniumhttp://en.wikipedia.org/wiki/Aluminium


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Composition Contd..

To overcome power consumption increasedue to gate current leakage, high-κ dielectric is replacing silicon dioxide as

the gate insulator, and metal gates aremaking a comeback by replacing polysilicon

The gate is separated from the channel by athin insulating layer of what wastraditionally silicon dioxide, but moreadvanced technologies used siliconoxynitride.

Some companies have started to introduce ahigh-κ dielectric + metal gate combination inthe 45 nanometer node


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The primacy of MOSFETs In 1960, Dawon Kahng and Martin M. (John)

Atalla at Bell Labs invented the metal oxidesemiconductor field-effect transistor (MOSFET).

Operationally and structurally different fromShockley's bipolar junction transistor, theMOSFET was made by putting an insulatinglayer on the surface of the semiconductor andthen placing a metallic gate electrode on that.

It used crystalline silicon for the semiconductorand a thermally oxidized layer of silicon dioxidefor the insulator.

The silicon MOSFET did not generatelocalized electron traps at the interface

between the silicon and its native oxide layer,and thus was inherently free from the trappingand scattering of carriers that had impeded theperformance of earlier field-effect transistors.


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Primacy contd..

Following the (expensive) development of i) clean rooms to reduce contaminationii) photolithography and the planarprocess to allow circuits to be made in veryfew steps,

the Si − SiO2 system possessed technicalattractions such as low cost of production (on a per circuit basis) and ease of integration.

Largely because of these two factors, theMOSFET has become the most widely usedtype of integrated circuit.

http://en.wikipedia.org/wiki/Polysiliconhttp://en.wikipedia.org/wiki/Polysilicon


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CMOS circuits The principal reason for the success of the MOSFET was the

development of digital CMOS logic, which uses p- and n-channel MOSFETs as building blocks.

Overheating is a major concern in integrated circuits sinceever more transistors are packed into ever smaller chips.

CMOS logic reduces power consumption because no current

flows (ideally), and thus no power is consumed, exceptwhen the inputs to logic gates are being switched.

CMOS accomplishes this current reduction bycomplementing every nMOSFET with a pMOSFET andconnecting both gates and both drains together.

A high voltage on the gates will cause the nMOSFET toconduct and the pMOSFET not to conduct and a low voltageon the gates causes the reverse.

During the switching time as the voltage goes from onestate to another, both MOSFETs will conduct briefly. Thisarrangement greatly reduces power consumption and heatgeneration.


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Digital

The growth of digital technologies like themicroprocessor has provided the motivation toadvance MOSFET technology faster than anyother type of silicon-based transistor.

A big advantage of MOSFETs for digitalswitching is that the oxide layer between thegate and the channel prevents DC current fromflowing through the gate, further reducingpower consumption and giving a very largeinput impedance.

The insulating oxide between the gate andchannel effectively isolates a MOSFET in onelogic stage from earlier and later stages, which

allows a single MOSFET output to drive aconsiderable number of MOSFET inputs.


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Digital…contd..

Bipolar transistor-based logic (such as TTL)does not have such a high fanout capacity.

This isolation also makes it easier for thedesigners to ignore to some extent loadingeffects between logic stages independently.

That extent is defined by the operatingfrequency: as frequencies increase, the inputimpedance of the MOSFETs decreases


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Analog

The MOSFET's advantages in most digital circuits donot translate into supremacy in all analog circuits.

The two types of circuit draw upon different featuresof transistor behavior.

Digital circuits switch, spending most of their timeoutside the switching region, while analog circuitsdepend on MOSFET behavior held precisely in theswitching region of operation.

The bipolar junction transistor (BJT) has traditionallybeen the analog designer's transistor of choice, duelargely to its higher transconductance and its higheroutput impedance (drain-voltage independence) in theswitching region.


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MOSFETS—SUITABILITY—ANALOGCKTS OVER BJTS

Nevertheless, MOSFETs are widely used in manytypes of analog circuits because of certainadvantages.

The characteristics and performance of many analogcircuits can be designed by changing the sizes (lengthand width) of the MOSFETs used.

By comparison, in most bipolar transistors the size ofthe device does not significantly affect theperformance.

MOSFETs' ideal characteristics regarding gate current(zero) and drain-source offset voltage (zero) also

make them nearly ideal switch elements, and alsomake switched capacitor analog circuits practical.


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In their linear region, MOSFETs can be used as

precision resistors, which can have a much highercontrolled resistance than BJTs.

In high power circuits, MOSFETs sometimes have theadvantage of not suffering from thermal runaway asBJTs do.

Also, they can be formed into capacitors and gyratorcircuits which allow op-amps made from them toappear as inductors, thereby allowing all of thenormal analog devices, except for diodes (which canbe made smaller than a MOSFET anyway), to be builtentirely out of MOSFETs.

This allows for complete analog circuits to bemade on a silicon chip in a much smaller space

http://en.wikipedia.org/wiki/Transconductancehttp://en.wikipedia.org/wiki/Transconductance


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Some ICs combine analog and digital MOSFET circuitry on asingle mixed-signal integrated circuit, making the neededboard space even smaller.

This creates a need to isolate the analog circuits from thedigital circuits on a chip level, leading to the use of isolationrings and Silicon-On-Insulator (SOI).

The main advantage of BJTs versus MOSFETs in the analogdesign process is the ability of BJTs to handle a largercurrent in a smaller space.

Fabrication processes exist that incorporate BJTs andMOSFETs into a single device.

Mixed-transistor devices are called Bi-FETs (Bipolar-FETs)if they contain just one BJT-FET and BiCMOS (bipolar-CMOS) if they contain complementary BJT-FETs.

Such devices have the advantages of both insulated gatesand higher current density.


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BJT’S BOLD FACE

BJTs have some advantages over MOSFETs for atleast two digital applications.

Firstly, in high speed switching, they do not have the"larger" capacitance from the gate, which whenmultiplied by the resistance of the channel gives theintrinsic time constant of the process.

The intrinsic time constant places a limit on thespeed a MOSFET can operate at because higherfrequency signals are filtered out.

Widening the channel reduces the resistance of thechannel, but increases the capacitance by the exact

same amount.


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Reducing the width of the channel increasesthe resistance, but reduces the capacitanceby the same amount. R*C=Tc1,0.5R*2C=Tc1, 2R*0.5C=Tc1.

There is no way to minimize the intrinsictime constant for a certain process.

Different processes using different channellengths, channel heights, gate thicknessesand materials will have different intrinsictime constants.

This problem is mostly avoided with a BJTbecause it does not have a gate.

http://en.wikipedia.org/wiki/BiCMOShttp://en.wikipedia.org/wiki/BiCMOS


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The second application where BJTs have an advantage overMOSFETs stems from the first.

When driving many other gates, called fanout, the resistance of theMOSFET is in series with the gate capacitances of the other FETs,creating a secondary time constant.

Delay circuits use this fact to create a fixed signal delay by using asmall CMOS device to send a signal to many other, many timeslarger CMOS devices.

The secondary time constant can be minimized by increasing thedriving FET's channel width to decrease its resistance anddecreasing the channel widths of the FETs being driven,decreasing their capacitance.

The drawback is that it increases the capacitance of the drivingFET and increases the resistance of the FETs being driven, butusually these drawbacks are a minimal problem when compared tothe timing problem.

BJTs are better able to drive the other gates because they canoutput more current than MOSFETs, allowing for the FETs beingdriven to charge faster.

Many chips use MOSFET inputs and BiCMOS outputs.


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MOS FET driven by gate voltage

What happenswhen gate voltageincreases fromzero?


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Formation of depletion region

As VG becomes more

positive, the holes inthe p-substrate arerepelled from the gatearea

This leaves negativeions behind so as tomirror the charge onthe gate

DEPLETION region iscreated

NO current flows, sinceNO charge carriers areavailable.

http://en.wikipedia.org/wiki/Fanouthttp://en.wikipedia.org/wiki/Fanout


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On set of Inversion

As VG increaseswidth of dep regn

increases Potential at the oxide

silicon interfaceincreases

The structureresembles twocapacitors in series:gate oxide capacitorand depletion regioncapacitor


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Interface is “INVERTED”

When the interfacepotential reachsufficiently positivevalue, electrons flowfrom the source tosurface and eventuallyto drain

Thus the channel of the charge carriers isformed under the gateoxide between S and

D. the tst is turned ON


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Threshold voltage

The value of VG for which this INVERSIONtakes place is called THRESHOLDVOLTAGE

If VG raises further, the charge in thedepletion region remains relativelyconstant, while the channel chargedensity continues to increase

Provides a greater current from S to D


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Quantification of VTH

The TURN ON phenomenon is aGRADUAL function of gate voltage

How to define VTH UNAMBIGUOUSLY?

VTH of NFET is defined as the gatevoltage for which the interface is “Asmuch n-type as the substrate isP-type”


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Nsub is the doping concentration of thesubstrate


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In practice, the “native”

threshold value obtainedfrom the equation maynot be suited to thecircuit design.

E.g. VTH=0 and thedevice may not TURNOFF for VG0

The threshold voltage istypically adjusted byimplantation of dopantsinto the channel areaduring fabrication

This alters the dopinglevel of the substratenear oxide interface.


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Consider a semiconductor bar carrying current I.

The charge density along the direction of current

is Qd coulombs per meter.

Velocity of the charge is ν m/sec


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I/V characterization

Measure the total charge that passes

through a cross section of the bar in unittime.

With velocity ν, all of the chargeenclosed in “ν” meters of the bar mustflow through the cross section in one

second. .

d Q I


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MOS I/V CH

Consider an NFET whose S & D are connected to ground.

Refer fig shows channel charge with equal drain and source voltages.

What is the charge density in the INVERSION layer? Since onset of the INVERSION occurs at VGS = Vth, the INVERSION charge

density produced by the gate oxide capacitance proportional to VGS -Vth. For VGS > VTH, any charge placed on the gate must be mirrored by the charge in

the channel

This yields a uniform channel charge density.


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Charge density (charge / unit length) is

Qd = WCox(VGS -Vth). where Cox is capacitance per unit area.

Cox.W = Ctotal /L = capacitance per unitlength


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CASE 2: Drain Voltage VD > 0

Fig: Channel charge with unequal drain and source voltages.

Since channel potential varies from zero at the source to VD at the drain.

Local voltage difference between gate and channel varies from V G to VG - VD Thus the charge density at point x along the channel is Q d= W Cox[VGS - V(x) -

Vth].where V(x) is the channel potential at x.

Current density ID = -WCox[VGS - V(x) - Vth].ν

Note: Negative sign is due to the charge carriers (i.e. electrons).ν is the velocity of electrons in the channel.


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ν = µE ,

where µ is the mobility of charge carriers,

E is the electric field.

Qd (x) = WCox[VGS - V(x) - Vth].

where V(x) is channel potential at x.

Current ID = -WCox[VGS - V(x) - Vth] ν

ID = -WCox[VGS - V(x) - Vth] µE

ID = WCox[VGS - V(x) - Vth] µ(dV/dx)

V(0) = 0; V(L) =VDS ;

Integrating both sides w.r.t dx


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Evaluation of ID

Since ID is constant along the length of thechannel,

L is effective channel length.


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Fig: Drain currentverses Drain- sourcevoltage in the trioderegion.

Observations:

Current capability of the device INCREASESwith V

GS

.


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Q) What is the peak current and for which value ofVDS it occurs?

Calculate ∂Id / ∂VDS and equate it to 0

It yields VDS = (VGS – VTH)

Corresponding ID,max = ½. μn COX (W/L) (VGS –VTH)

2

Where W/L aspect ratio, (VGS – VTH) is over

drive voltage.

If VDS< “VGS - Vth” , then the device operates inthe TRIODE region.


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For VDS


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Q) When VDS > VGS - Vth whathappens?

Will ID follow

parabolic path?

NO!

Indeed ID becomesrelatively constant.

Implies transistor isin saturation region.

How?


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Density of INVERSIONlayer charge isproportional to [VGS -V(x) – VTH].

If Vx [VGS – VTH], then

Qd(x) drops to zero.


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Channel pinch off

In the other words;from the Figure if VDS is slightly greaterthan VGS –VTH, thenINVERSION layerSTOPS at x≤ L.

Implies the channelis PINCHED OFF.

As VDS increasesmore, a point atwhich Qd=0 MOVEStowards the source.


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Thus at some point along the channel, local potentialdifference between the gate and oxide silicon interface isNOT SUFFICIENT to support an INVERSION layer.

Recall the equation for ID ID = WCox[VGS - V(x) - Vth] µ(dV/dx)

Integration now is to be taken from ? X=0 to x=L’

Where L’ is the point at which qd drops to zero. This corresponds to RHS limits V(x)=0 to V(x)= VGS-VTH This gives I D = ½ µn C ox (W/ L

’ ) (V GS-V TH )2

Observation:

I D is IND of V DS if L’ remains close to L. For PMOS

I D = ½ µ p C ox (W/ L’ ) (V GS-V TH )

2

It is assumed that ID f lows from D to S whereas holes fromS to D Since µp = ½ µn; PMOS suffers from lower current driving capability.


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Saturated mosfet as current source?

With approximate L=L’, a saturatedMOSFET can be used as a currentsource connected between D and S.

Observations:

Current sources INJECT currentinto ground or draw currentfrom VDD.

Only ONE terminal of eachcurrent source is FLOATING.

Since MOSFET (saturated) producesa current in response to its G-S ODvoltage, a figure of merit can bedefined that indicates how well aDEVICE converts a voltage tocurrent.


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Figure of merit gm

gm represents SENSITIVITYof the device.

For high gm, a SMALL change

in VGS results in a LARGEchange in ID.

Observations:

gm in saturation = 1/Ron indeep triode region.

Alternatively, Substitute(VGS-VTH) in gm expression


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gm variation as a function of V,I

Observations: Eq. (1) indicates that gm increases with OD if W/L is

constant.

Eq. (2) indicates that gm increases with ID if W/L isconstant.

Eq. (2) indicates that gm decreases with OD if ID isconstant. biasing style


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gm in triode region


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Example

For the arrangementshown, plot the gm as afunction of VDS

Let VDS is decreasingfrom infinite

So long as VDS > Vgs-Vth,tst is in sat

gm is constant

When VDS < Vgs-Vth, tst isin triode region

gm ? with VDS


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Water analogy of MOSFET

• Source: water reservoir • Drain: water reservoir • Gate: gate between source and drain reservoirs Want to understand MOSFET operation as a function of: •

gate-to-source voltage (gate height over source water level) • drain-to-source voltage (water level difference between reservoirs) Initially consider source tied upto body (substrate or back).


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Cut off regn

MOSFET: VGS < VT , VGD < VT with VDS > 0.

•Water analogy: gate closed; no water can flowregardless of relative height of source and drainreservoirs.

Id=0


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Triode regn

MOSFET: VGS > VT , VGD > VT , with VDS > 0.

• Water analogy: gate open but small difference in height

between source and drain; water flows.

Electrons drift from source to drain ⇒ electrical current!

• VGS ↑ → |Qn| ↑→ ID ↑

• VDS ↑ → Ey ↑ → ID ↑


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Saturation

• MOSFET: VGS > VT , VGD < VT (VDS > 0). • Water analogy: gate open;

water flows from source to drain, but free-drop ondrain side total flow independent of relative reservoir height! ID independent of VDS: ID = IDsat


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Sat contd..

At pinch-off: • charge control equation inaccurate

around VT • electron concentration small but not

zero • electrons move fast because electric

field is very high • dominant electrostatic feature: acceptor

charge •

there is no barrier to electron flow (on thecontrary!)


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Clarification on notation

As VG-V

Dof an NFET

drops below VTH pinchoff occurs

If VG-VD of a PFET isNOT large enough,(


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BODY EFFECT

Q) What happens if bulk voltage of NFET DROPS below thesource voltage?

So far we presume that S and B are at the same potential. Fig: NMOS with negative bulk voltage. Let VS = VD = 0; VG < VTH. Depletion region is formed but NO INVERSION layer.


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Variation of depletion region charge with bulk voltage

As VB becomes more negative, more holes are attracted towards to subconnection, leaving a large negative charge behind

DEPLETION REGION becomes WIDER.

Threshold voltage is a function of the total charge in the DEPLETION REGIONbecause the gate must mirror Qd before an INVERSION layer is created.

As VB drops and Qd increases then VTH also increases. This called BODY EFFECT or BACK GATE EFFECT .


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Vth with body effect

where Body effect coefficient

γ = 0.3 or 0.4 V1/2 typically.


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Example

Plot the drain current if VX varies from

–infinite to 0.

Assume VTH0=0.6V,gamma=0.4v0.5,2ΦF=0.7V

When VX is sufficiently negative, Vthexceeds 1.2VM1 is OFF

1.2=0.6+0.4{sqrt[0.7-Vx1]-sqrt(0.7)}

Vx1=-4.76V

Vx1< Vx


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Illustration of Body effect

CASE 2 : Substrate is connectedto ground.

As Vin becomes more positive,Vout also becomes more positive(since Id = I1const)

Potential difference betweensource and bulk increases, VTHraises.

Vin – Vout (VGS) must increaseso as to maintain Id constant.

Body Effect is usuallyundesirable.

Change in threshold voltagecomplicates analog design.


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CHANEL LENGTH MODULATION:

Recall, Actual length of INVERTED channelgradually decreases aspotential differencebetween gate and drainincreases.

L’ is a function of VDS.

This effect is calledchannel lengthmodulation.

λ is channel lengthmodulation coefficient.

For longer channels λ issmall


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Sub threshold conduction

For VGS=Vth, aWEAK inversion

layer still existsand some currentflows from D to S.

For VGS


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MOS FET Capacitance

A capacitance existsbetween every two of thefour terminals of a MOSFET.

The value of each capdepends on the biasconditions

Oxide cap:C1 = W L Cox Dep cap between ch and

sub C2 C3 = C3 =Cov Overlap cap

gaate poly-S/D= W LD Cox

C5= Jn cap bet S/D andSub. =bottom plate cap+side wall cap


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Layout for Low Capacitance withfolded structure


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G-S and G-D Capacitances withVGS

CGB is usually neglected in sat and triode regnsbecause the inversion layer acts as “shield”between gate and bulk region

if the gate voltage varies, charge is supplied bythe source and drain, rather than the bulk.


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JUNCTION CAPACITANCE


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LINEARIZING THE JUNCTIONCAPACITANCE


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MOS Small Signal Models

The quadratic eqns discussed sofar are derived fromthe large-signal model of MOSFETs..

Such a model is essential in analyzing circuits inwhich the signal significantly disturbs the bias points,specifically if non non linear effects are of concern.

If the perturbation in bias condition is small, a small-signal model , i.e. an approximation of large signalmodel around the operating point can be employed tosimplify calculations.since in many analog ckts, MOSFETs are employed in SAT, corresponding model isconsidered


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SS model is derived by producing a small increment in abias point and calculating the resulting increment in otherbias parameters.

Recall Drain current is a fn of G-S voltage

a voltage dependent current source equal towing to thegmVGS is employed.

The low frequency impedance between G and S is very high

Owing to the channel length modulation, ID also varies withVDS

This effect can also be modeled by Voltage dependentcurrent source

But a current source whose value depends upon the voltageacross it is equivalent to a linear resistor.

It is modeled by a resistor ‘ro’ or “rds” tied between D and S


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As Vgs rises, the density of the holes at the interface falls

A depletion region begins toform under the oxide

Device enters weak inversionregion

In this mode, the capacitanceconsists of the seriescombination of Cox and Cdep.

As Vgs exceeds Vth, oxidesilicon interface sustains achannel and the unit areacapacitance returns to Cox


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End of session

Than Q

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