Lect5 EQ DFE - Yonsei Universitytera.yonsei.ac.kr/class/2013_1_2/lecture/Lect5_EQ_DFE.pdf · 2013-03-16 · How to implement? • FIR filtering – Zero-forcing can be implemented

March

1

일 월 화 수 목 금 토

2

8 93 76

Lect. 2

54

Lect. 1

15 1610 1413

Lect. 4

1211

Lect. 3

22 2317 2120

No Class

1918

Lect. 5

3024

31

27

SP1

2625

Lect. 6

2928

April

5

일 월 화 수 목 금 토

643

SP1

21

SP1

12 137 1110

Lab. 1

98

Quiz 1

19 2014 1817

Lect. 8

1615

Lect. 7

26 2721 25242322

28 3029

Lect. 9

Mid-Term Exam Period

● Student Presentation (SP)- Remember from the first class,

- Each student is required to study a selected journal paper and present itssummary in English for 25 mins. ~ 10 mins of discussion follows.

- Papers of significant importance related to the topic discussed in the class will beselected. These are of high technical quality and can be difficult for those who arenot working in the area. Students are encourage to present the overall summarywithout worrying too much about the details, especially of circuit implementation.

● Paper List for SP1

(3/27: LE)- “A 0.18-um CMOS 3.5-Gbps Continuous-Time Adaptive Cable Equalizer UsingEnhanced Low-Frequency Gain Control Method”, IEEE JOURNAL OF SOLID-STATECIRCUITS, VOL. 39, NO. 3, p. 419, 2004. (권대현)

- “Equalization and Clock and Data Recovery Techniques for 10-Gbps CMOS Serial-Link Receivers”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE JOURNAL OFSOLID-STATE CIRCUITS, VOL. 42, NO. 9, p. 1999, 2007 (김민형)

(4/1: DFE)- “Edge and Data Adaptive Equalization of Serial-Link Transceivers”, IEEE JOURNALOF SOLID-STATE CIRCUITS, VOL. 43, NO. 9, p. 2157, 2008 (김찬모)

- “A 4-Channel 1.25–10.3 Gbs Backplane Transceiver Macro With 35 dB Equalizer andSign-Based Zero-Forcing Adaptive Control”, IEEE JOURNAL OF SOLID-STATECIRCUITS, VOL. 44, NO. 12, p. 3547, 2009 (박정현)

● Paper List for SP1

(4/3: DFE, Pre-emphasis)

- “Equalizer Design and Performance Trade-Offs in ADC-Based Serial Links”, IEEETRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 58, NO. 9,p. 2096, 2011 (반유진)

- “Phase and amplitude pre-emphasis techniques for low-power serial links”, IEEEJOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 6, p. 1391, 2006 (유병민)

High-speed Serial Interface

Lect. 6 – Channel Equalizer (Decision Feedback Equalizer)

2013-1High-Speed Circuits and Systems Lab., Yonsei University6

Why equalize channel?• Channel causes ISI

– Frequency-dependent loss in channel eye-diagram closure


TxDriver Channel Rx

SamplerRx

Equalizer

Pulse response• Pulse response

– Output of rectangular pulse for a given channel


Channel

0

1

0

1

Bit period

Pulse response• Cursors in pulse response

– Cursor is amplitude component at each sampling edge• Main cursor: amplitude @ present sampling point• Pre-cursor: amplitude @ previous sampling point• Nth post-cursor: amplitude @ following sampling points


C0

C-1 C2

C1

C3

Bit period

Maincursor

Pre-cursor

1st post-cursor

2nd post-cursor

3rd post-cursor

Pulse response• ISI analysis with cursors

– Received signal is superposition of pulse responses.– At sampling points, cursors of pulse responses are summed. Amplitude at a sampling point is affected by adjacent bits ISI


C0

C-1 C2

C1

C3

Bit period

C0

C-1 C2

C1

C-1+C0C0+C1

C1+C2

C2+C3

Maincursor

Pre-cursor

1st post-cursor

2nd post-cursor

3rd post-cursor

How to reject ISI?• Forcing cursors to 0

– In the sampling-based system, amplitude only at sampling point is meaningful.

– By subtracting pre- and post-cursors at sampling points, pulse response can be reshaped.


C0

C-1 C2

C1

C3

Bit period

Maincursor

Pre-cursor

1st post-cursor

2nd post-cursor

3rd post-cursor

How to reject ISI?• Forcing cursors to 0

– After reshaping, superposition of pulse responses results in no ISI at sampling points.


C0

C-1 C2C1 C3

Bit period

Maincursor

Pre-cursor

1st post-cursor

2nd post-cursor

3rd post-cursor

C0

C-1

C2C1

How to implement?• FIR filtering

– Zero-forcing can be implemented by FIR filtering


1-bitPeriodDelay

InputData

(Digital)

+

- --

C-1 C1 C2

1-bitPeriodDelay

1-bitPeriodDelay

Channel1-bit

PeriodDelay

Subtractpre-cursor

Main cursor isnot subtracted

Subtract1st post-cursor

Subtract2nd post-cursor

Assuming no delayIn channel

To subtractpre-cursor

SamplerOutputData

(Digital)

D-1 D1 D2

- RequirementsPulse response for the channel cursor coefficientsPrecise sampling and delay Synchronized clock

Decision feedback equalizer– Pre-cursor cannot be removed– Post-cursors can be removed using previous data


InputData

(Digital)

+

- --

C1C2

1-bitPeriodDelay

1-bitPeriodDelay

C3

Channel Sampler

Decision

Feedback

EqualizationOutputData

(Digital)

D1D2D3

Decision feedback equalizer• Pros

– Applicable to non-linear channel– No noise boosting

• Cons– Clock recovery necessary for data sampling operation– Impossible to open entirely closed eye – Pre-cursor cannot be removed– Timing requirement


Decision feedback equalizer• Example of DFE output

– Difficult to measure DFE output eye-diagram• Sampling-based equalizer produces sampled values• Simulation results shown below


Critical path• Timing requirement

– Decision made in sampler should be fed back into sampler input before next sampling

– Critical path is C1 path– Can be difficult to satisfy in high-speed applications


OutputData

(Digital)

InputData

(Digital)

+

- --

C1C2

1-bitPeriodDelay

1-bitPeriodDelay

C3

Channel Sampler

CLK

CLKCLK

Tperiod >tCK-to-Q,sampler + tprop,amp + tprop,combiner + tsetup,sampler

tCK-to-Q,sampler

tprop,amp

tprop,combiner tsetup,sampler

D1D2D3

Loop unrolling• 1-tap loop unrolling


OutputData

(Digital)

InputData

(Digital)

1-bitPeriodDelay

Channel

CLK

1. Tperiod > tCK-to-Q,sampler + tprop,mux+ tsetup,delay

2. Tperiod > tCK-to-Q,delay + tprop,amp + tprop,combiner + tsetup,sampler

tCK-to-Q,sampler+

- --

C1C2C3

Sampler

CLK

tprop,combiner tsetup,sampler

+

- --

C1C2C3

Sampler

CLK

1-bitPeriodDelay

CLK

HIGH

LOW

D1

D2D3

D2D3

tprop,mux

tprop,amp

tCK-to-Q,delay


– Built-in two different paths for different (H or L) previous data bit– MUX selects the correct path – Sampled data bit for C1 does not have to be fed back since both

cases are already considered– 2 possibilities for the critical path

• After first sampler• C2 feedback path

– Reduces timing requirement, but increases hardware burden (power and area)



– It is possible to implement 2-tap DFE without any feedback


OutputData

(Digital)

InputData

(Digital)Channel

+

-

Sampler

CLK

1-bitPeriodDelay

CLK

D1

C1+C2

+

-

Sampler

CLK-C1+C2

+

-

Sampler

CLKC1-C2

+

-

Sampler

CLK-C1-C2

1-bitPeriodDelay

CLK

D1

Tperiod > tCK-to-Q,sampler + tprop,mux+ tsetup,delay

(H,H)

(L,H)

(H,L)

(L,L)

Reduced sampling rate

– Sampling rate defines the highest operating frequency• Higher the frequency, more power consumption• Reduced sampling rate results in relieved timing requirements

– Reduced sampling rate• Half-rate

– Sampling with 2 samplers using both rising and falling edges of half-rate clock

• Quad-rate– Sampling with 4 samplers using both rising and falling edges of I/Q

quadrature clocks

– Reduced power consumption but increased chip area


Reduced sampling rate• Reducing sampling rate

– Half-rate sampling

– Quad-rate sampling


DATA

CLK

DATA

CLK-I

CLK-Q

Reduced sampling rate• Half-rate sampling implementation

– Sampling with the rising edge of CLK and ~CLK– Consecutive data are alternatively sampled by two samplers


OutputData1

(Digital)

InputData

(Digital)Channel

Sampler#1

CLK

Sampler#2

~CLK

OutputData2

(Digital)

D1

D2

Reduced sampling rate• 2-tap DFE with half-rate sampling


OutputData1

(Digital)

InputData

(Digital)Channel

+

- --

C2C1

Sampler#1

CLK

+

- --

C2C1

Sampler#2

~CLK

OutputData2

(Digital)

D1

D2

Reduced sampling rate• DFE for half-rate sampling

– Output waveform• Input of sampler #1 (Even)• “ODD” region is not

equalized

Complete eye-diagram is difficult to observe


Koon-Lun Jackie Wong, E-Hung Chen, and Chih-Kong Ken Yang, ”Edge and Data Adaptive Equalization of Serial-Link Transceivers”

JSSC2008

Reduced sampling rate• 1-tap unrolled DFE for half-rate sampling

– Block diagram• Very complex!!• Area and power is always trade-off


Koon-Lun Jackie Wong, E-Hung Chen, and Chih-Kong Ken Yang, ”Edge and Data Adaptive Equalization of Serial-Link Transceivers”

JSSC2008

Design example


“A 10-Gb/s Adaptive Look-Ahead Decision FeedbackEqualizer With an Eye-Opening Monitor”

Chang-Kyung Seong, Jinsoo Rhim, and Woo-Young ChoiTCAS2 2012

2-tap loop-unrolling and ¼-rate samplingAdaptation by on-chip eye-diagram monitoring

90nm CMOS technology / COB package11mW dissipation @1.2V power supply

Design example


¼-rate sampling

2-tap loop unrolling

Design example


• Adaptation by on-chip eye-diagram monitoring– Eye-information is extracted and digitally processed on the chip.

Design example


• Post-layout simulation– 10Gb/s data after 2.2-GHz BW channel

Design example



Design example



Design example• Extracted eye-diagram in measurement


Before

Before

After

After

10cm PCBChannel

20cm PCBChannel

Design example


• Extracted eye-diagram in measurementBefore

Before

After

After

30cm PCBChannel

40cm PCBChannel

Documents

Lect5 EQ DFE - Yonsei Universitytera.yonsei.ac.kr/class/2013_1_2/lecture/Lect5_EQ_DFE.pdf · 2013-03-16 · How to implement? • FIR filtering – Zero-forcing can be implemented