Last Years Mission AccomplishedFeature Size (micron)5v3.3v2.5v1.8v1.3vProcess Leadership

Density Leadership

Performance Leadership

Price & Value Leadership

Software Leadership

Process LeadershipTransistor Count (millions)XC40125XVXC40150XVXC40250XV0.25u ProcessVirtex1 Million Gate

samples today

Density LeadershipXC4085XLXC40125XV 1997 1998 1999 2000 2002VirtexDensity (system gates)10M GatesIn 2002Virtex II10 Million System Gates in 2002!XC40250XV

Architecture Innovation Leadership Distributed Dual Port RAM I/O Registers Internal Bussing 5V Tolerant I/O 3.3V and 5V PCIFeatures 133 MHz Block Dual Port RAM System I/O (LVTTL, SSTL, GTL) Vector Based Interconnect Phase Locked Loops 66 MHz 64-Bit PCI1998 1999 2000 2001 2002 Reconfigurable Logic On-Chip A/D-D/A Embedded Functions 1GHz Diff. Interface Built-in Logic Analyzer

Performance LeadershipEnabling high performance solutions first* 1/(Tsetup+Tclock-to-out)System Clock Rate* (MHz)PC 100 SDRAM Compliant100 MHz DSP for Wireless Base Station33 MHz PCI2002 System Standards233 MHz uP300 MHz RAM I/F133 MHz SDRAM I/F155 MHz SONET 66 MHz PCI

Packaging LeadershipChip ScaleFine Pitch BGAFlip ChipTechnologySBGA1998 2000 20021.0mm

CPLD Price LeadershipPriceXC9536/XL$0.80$7$1.80$15XC95216/XLWithout CompromisesFlexible ISPtPD = 4nsBest Pin-LockingIndustry Standard JTAG* Prices are based on 100Ku+, slowest speed grade, lowest cost package

Software Leadership 1998 2000 2002 Team Based Design Modular Guide Modular Compile HDL- Centric Flows

Largest Installed BaseHighest Circuit Performance with M1Fastest Timing Driven Compile TimesShrink-Wrapped FPGA ExpressBest flows & QOR with leading EDA vendorsPush Button Design

Compile Time Leadership1999 Goal:1 Million Gates in 45 minutes! Faster CPUs Faster Compile Times Modular Compile0204050607080901001.41.52.12.2

Minutes** 100k System gate designs (200MHz Pentium)ReleaseUp to 2.1X faster than 1.53010And with ...

Simple & Fast Low Cost CPLD SolutionsIsolates User From Interface IssuesCritical Signal TimingElectrical InterfacingControl Signal Sequencing (State Machine Design)Variances In InterfacesSDRAM (i.e. Bank vs. SIMM)Unique System Back-End

Flexible High Density FPGA SolutionsJPEG Compression (70k ASIC Gates + RAM)FPGA Advantages over ChipsetsCan specify Non-Standard Data-Rate & Pixel DepthIndustrial Temp RangeHigh Performance2x NTSC Video Resolution1.5x NTSC Pixel Depth

Xilinx DeliversCommitted to Product LeadershipFocused on Complete SolutionsDriving New Applications With CoresDelivering the VisionReal Technology Partnerships

Introduction to Xilinx

PLD Industry Growth

Programmable Logic vs. Semi-Custom ASIC MarketMask Programmed Gate Arrays $7.4BProgrammableLogic Share $5.8BStandard Logic $2.6B37%16%47%Total 1996 Market $9.5BTotal 2001 Market $15.8BMask Programmed Gate Arrays $5.6BProgrammable Logic Share$1.9BStandard Logic $2.0B20%21%59%Source: Dataquest, May 1997

Who is Xilinx?Worlds leading innovator of complete programmable logic solutions

Inventor of the Field Programmable Gate Array$650M Annual Revenues; 35+% annual growthFabless* Semiconductor and Software CompanyUMC (Taiwan) {*Xilinx acquired an equity stake in UMC in 1996}Yamaha (Japan)Seiko Epson (Japan)

Foundation and Alliance SeriesDesign Software

Company Milestones1984Xilinx Founded1985Introduced first field programmable gate array (FPGA)1987Introduced second family of FPGAs1988Established subsidiary in Japan1989More than one million devices sold1990Initial public offering1991Introduced third family of FPGAs1992Expanded into complex programmable logic (CPLDs)1993Established Xilinx Hong Kong1995Xilinx ranked 10th largest ASIC supplier; Xilinx Ireland opens1996Xilinx ranked 8th largest ASIC supplier1997Industrys first advanced 0.35 & 0.25 micron FPGAs1998Introduced low-cost Spartan FPGAs with RAM & cores1998 Industrys first provide system solution FPGA with Virtex

Why Xilinx?SiliconLargest, fastest, lowest power FPGAsLowest cost CPLDsSoftwareAlliance Series: HDL, synthesis, EDA integration, optimizationFoundation Series: ready to use, complete solutionsLogiCORES & AllianceCORES: optimized and supportedServiceMost comprehensive field and on-line technical supportAdvanced Internet Web solutionsProcess TechnologyDeep submicron capacity Sampling 0.22 micron nowBetter price, performance, density

Whos Using XilinxIndustrial &InstrumentationCommunications12%16%35%Military, High Reliability4%1% Misc32%NetworkingData ProcessingSource: Xilinx

How Customers UseProgrammable LogicXilinx Provides Standard Parts Blank Integrated CircuitsCustomers Create Custom Circuits with Xilinx Software ToolsWhen Design Is Final, Customers Go into Immediate Production

Introduction to Programmable Logic Device Solution

Programmable Logic FamiliesCommon ResourcesConfigurable Logic Blocks (CLB)Memory Look-Up TableAND-OR planesSimple gatesInput / Output Blocks (IOB)In/Out, latches, inverters, pullup/downsInterconnect or RoutingLocal, internal feedback, and globalSource: DataquestProgrammableLogic Devices(PLDs)GateArraysCell-BasedICsFull CustomICsSPLDs(PALs)FPGAsAcronymsSPLD = Simple Prog. Logic Device PAL = Prog. Array of LogicCPLD = Complex PLDFPGA = Field Prog. Gate Array

CPLD and FPGACPLD FPGAArchitecture PAL/22V10-like Gate array-like More Combinational More Registers + RAMBasic Cell Product Term CLB & LUT

Density Low-to-medium Medium-to-high 0.5-10K logic gates 1K to 1M system gatesApplication Combination based Register BasedTiming Delay Predictable timing Application dependent

Performance Predictable timing Application dependent Up to 250 MHz today Up to 150MHz today

Interconnect Crossbar Switch Incremental Complex Programmable Logic Device Field-Programmable Gate Array

FPGAs and CPLDs OftenCo-Exist in the Same SystemFPGAs excel at:higher densitypipelined logicFIFOs, register filesusing RAMCPLDs excel at:deterministic performancefast pin-to-pin speedstate machineswide decoding

Why Programmable Logic ?Faster Time to MarketImmediate PrototypesFaster DebugLower Risk PCB DevelopmentFaster Access to Hardware for Firmware/Software DevelopmentTest Marketing CapabilityField Upgrade PotentialSolve Gate Array Obsolescence Problems

Whats Going on XilinxDeep submicron arrived unexpectedly early0.5-0.35-0.25-0.18-?Deep submicron technology provides for freespeed, density, low costBut it requires voltage migration5 V - 3.3 V - 2.5 V - 1.8 V - 1.5 V - ?

Design AlternativesMicroprocessorsIdeal, if fast enoughGates, MSI, PALsOutdated, inefficient inflexibleDedicated Standard Chip SetsCheap, but no product differentiationASICsOnly for rock-stable, high-volume designsProgrammable LogicFor flexibility and performance

ASICs become less attractiveNon-recurring engineering cost increasesmore masking steps, more expensive masksMinimum order quantity riseslarger wafers, smaller dieSilicon capability exceeds user equirementsSuppliers are leaving this overly competitive market

FPGAs Are Gaining Acceptance> 20x Bigger

> 5x Faster

> 50x Cheaper1/911/921/931/941/951/961/971/981/99YearCapacitySpeedPrice110100

FPGAs Are Good EnoughAdequate capacity, performance, price200,000 gates, 85 MHz in 19981,000,000 gates, 200 MHz in 1999Standard product advantagessteep learning curve, cost declineperformance gain, speed binningIC manufacturing is best at mass-productioncustom devices have an inherent disadvantage

FPGAs are Good Enough BetterDeep submicron ASIC design is difficultsecond-order effects burden the traditional logic abstractionsystem designer needs help from EEVerification is very time consumingHardware/software integration is delayeduntil a working chip is delivered.

FPGAs Are BetterUser can focus on logic, not circuitsXilinx solves all circuit problemsclock delay and skewinterconnect delaycrosstalkI/O standardsFPGAs are 100% tested by generic test methodsEasy verification, incremental designEarly hardware/software integration

FPGAs Are Better Vastly SuperiorAvoid the ASIC re-spin costdesign error or market changeAvoid the ASIC inventory riskover- or under-inventoryobsolescenceReprogrammabilitylast-minute design modificationslast-step system customizationfield hardware upgradesreconfiguration per applicationreconfiguration per taskASICs will never offer these features

CPLDs Complement FPGAsCPLD strengthsWide address decodingSynchronous state machinesShort combinatorial pin-to-pin delaysIdeal for glue logicLow-costSingle-chipNon-volatileIn-System ProgrammableQuick and easy to use

Simple, Low-cost SolutionsXilinx offers low-cost CPLD and FPGA devices and a low-cost Foundation software packageThe devices are fast and have systems-oriented featuresThe software is powerful and easy to use.

You need not be rich or a geniusto use our programmable logic

100+MHz System SolutionsThe Virtex family provides efficient solutions for:Electrical and thermal issuesI/O, logic, and memory designAlliance software provides powerful tools for a variety of design styles

You can achieve reliable and predictable performance automatically

Three new Xilinx familiesSpartanXL3.3-V low-cost FPGA5,000 to 40,000 gatesXC9500XL3.3-V In-System Programmable CPLDup to 200 MHzVirtexnext-generation FPGA with system featuresup to a million gates

More Xilinx FamiliesXC3000A, XC3100Afor existing designsXC4000E, EX, XL, XLA, XVthe industrys most successful FPGAsXC5200for existing designsXC1700Serial configuration PROMs for all families

Xilinx FPGA Architecture Story199711,000 Logic Cells (125k gates)fastest RAM5 volt tolerant IOsbuffered quad lineVersaRing IOs6ns pin-to-pin

efficient segmented routinglowest power200065,000 Logic Cells (800k gates)built-in logic analyzerD/A & A/D supportcustom coreshigh speed differential interface (500MHz)199832,000 Logic Cells (400k gates)programmable IOsAdvanced Clocking100MHz system speedfast re-configurehierarchical memory solution

Ram Base Reconfigurable LogicAdvantages

Testability, incremental design, fast redesign

Experimentation with novel architectures

Easy upgrade or design modifications in production / field

Applications

Multi-purpose hardware - one card for several applications:Video formats, telecom standards, bus protocols,Intel vs Motorola CPU, printer resolution, ...

Time-shared hardwareDiagnostics, instrumentation

Xilinx FPGA ArchitectureProgrammableInterconnect I/O Blocks (IOBs)High Density -> 1M System GatesSRAM Based LUT for Synchronous Dual Port RAM or LogicASIC-like array structureBuilt-in Tri-StatesInfinite reconfigurations, downloaded from PC or workstation in ~1 secondConfigurableLogic Blocks (CLBs)

Logic in FPGAsLogic is implemented in Look-up-Tables - not gatesArchitecture is very rich in Flip-FlopsClock

I/O Block (IOB)Identical I/O Blocks line the periphery of die

Input, output, or bi-directionalRegistered, latched, or combinatorial Three-state outputProgrammable output slew rate

CLB (Configurable Logic Block)2 4-input LUTs and 1 3-input LUT muxes feed F/G LUTs or independent inputs to H LUT2 edge-triggered FFsDINECSR4 outputsFed by B muxes

Programmable InterconnectResources to create arbitrary interconnection networksHierarchy of interconnect resourcesdirectlocallong-lineglobalConnections are made by the use of programmable switches

CLBCLBCLBCLBSwitchMatrix

Whats CPLD ArchitectureSimilar to having multiple PAL devices inter connected in one chipBest applicationsWide functions Fast arithmeticComplex countersComplex state machinesPAL/GAL or TTL integrationNon-volatilePALPALPALPALSwi-tch

Mat-rixProg.ANDarrayFixedORarrayFF/Macro-cellFF/Macro-cell

Why FLASH Technology?Product benefits due to 67% smaller FLASH cellMore routing switches in the same area supports pinlockingLower parasitic capacitance improves performanceLong term cost improvements due to scalabilityGreatly improved endurance with FLASHLower program/erase voltages3XRoutingSwitchesTypical E2 CPLD CellFastFLASH CellSourceDataWord LineControlS1S2S3S1

Flash vs E2 EnduranceFlash delivers:-highest quality-no speed degradation-20 year retention-reliable reprogramming-worry free field upgrade

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Relative Endurance (#programming cycles)

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10010000

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Reprogramming Cycles

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Sheet2

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ISP Market Growth

Functions of 5 Product Term are fastestXilinx CPLDs use a Sum of Products ArchitectureFrom 5 P-terms to 15 P-terms cost under 1ns of tpdAND functions are free, Ors are not. An OR gate equals a MacrocellInverters are free36/54 Input5 Product Term

Naming ConventionsXilinx Component naming convention: Part name -speed -package. Example:

The speed grade is a relative measure of internal delay. Smaller numbers mean faster parts for all families EXCEPT Spartan. For Spartan, larger numbers mean faster parts.Speed GradeXC4028XL-3-BG256CPackageSub-family (3V = XL, no XL = 5V)Family (4000, 9500 )Spartan names start with XCSMaximum number of gates (thousands)Operation condition(C:Com, I:Indst, M:Mil)

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