klu communications (theory)

Basics of Digital Systems Dept. of ECE

KL University, Guntur

COMBINATIONAL LOGIC FUNCTIONS

Digital logic circuits can be classified as either combinational or sequential circuits. A

combinational circuit is one where the output at any time depends only on the present

combination of inputs at that point of time with total disregard to the past state of the inputs.

The logic gate is the most basic building block of combinational logic. The logical function

performed by a combinational circuit is fully defined by a set of Boolean expressions. The

other category of logic circuits, called sequential logic circuits, comprises both logic gates

and memory elements such as flip-flops. Owing to the presence of memory elements, the

output in a sequential circuit depends upon not only the present but also the past state of

inputs.

Block diagram of combinational logic circuit

Above figure shows the block schematic representation of a generalized combinational circuit

having n input variables and m output variables or simply outputs. Since the number of input

variables is n, there are 2n possible combinations of bits at the input. Each output can be

expressed in terms of input variables by a Boolean expression, with the result that the

generalized system can be expressed by m Boolean expressions.

General Design procedure for combinational logic circuits:

The design of combinational circuits starts from verbal outline of the problem and ends in a

logic circuit diagram, or a set of Boolean functions from which the logic diagram can be

easily obtained.

The different steps involved in the design of a combinational logic circuit are as follows:

1. Statement of the problem.

2. Identification of input and output variables.

3. Expressing the relationship between the input and output variables.

4. Construction of a truth table to meet inputoutput requirements.



5. Writing Boolean expressions for various output variables in terms of input variables.

6. Minimization of Boolean expressions.

7. Implementation of minimized Boolean expressions.

Design and applications of Binary adders:

Half Adder:

A half adder is a combinational logic circuit that performs the arithmetic addition of two bits.

Such a circuit thus has two inputs that represent the two bits to be added and two outputs,

with one producing the SUM output and the other producing the CARRY.

For Sum S: For Carry C:

The Boolean expressions for the SUM and CARRY outputs are given by the equations

Half Adder using NAND gates:



Full Adder:

A full adder circuit is an arithmetic circuit block that can be used to add three bits to produce

a SUM and a CARRY output. Two of the input variables and represent the two

significant bits to be added and the third input represents the carry from the previous lower

significant position.

( )

( )

Full adder using SOP expressions:

For Sum S: For Carry C:

X Y Z S C

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1



Full adder with two Half adders:

( ) ( )

From the truth table,

( ) ( ) ( )

Full adder using NAND gates:



Subtractors:

In the method of subtraction, each subtrahend bit of the number is subtracted from its

corresponding minuend bit to form a difference bit. If the minuend bit is smaller than the

subtrahend bit, a 1 is borrowed from the next significant position.

Half-Subtractor:

A Half-Subtractor is a combinational circuit that can be used to subtract one binary digit

from another to produce a DIFFERENCE output and a BORROW output. The BORROW

output here specifies whether a 1 has been borrowed to perform the subtraction.

Half-Subtractor using NAND gates:

Full-Subtractor:

A full subtractor performs subtraction operation on two bits, a minuend and a subtrahend,

and also takes into consideration whether a 1 has already been borrowed by the previous

adjacent lower minuend bit or not. This circuit has three inputs and two outputs. The three

X Y D B

0 0 0 0

0 1 1 1

1 0 1 0

1 1 0 0



inputs, denote the minuend, subtrahend, and previous borrow, respectively. The

two outputs, D and B represent the difference and output borrow, respectively.

( ) ( )

For Difference D: For Borrow B:

Full-Subtractor using two Half-subtractors:

( ) ( )

From truth table,

( )

X Y Z D B

0 0 0 0 0

0 0 1 1 1

0 1 0 1 1

0 1 1 0 1

1 0 0 1 0

1 0 1 0 0

1 1 0 0 0

1 1 1 1 1



Full-Subtractor using NAND gates:

Binary Parallel Adder:

A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It

can be constructed with full adders connected in cascade, with the output carry from each full

adder connected to the input carry of the next full adder in the chain.

Binary Adder/Subtractor:

A Binary Adder/Subtractor is used to perform both addition and subtraction using a single

circuit. Subtraction of two binary numbers can be accomplished by adding 2s complement of

the subtrahend to the minuend and disregarding the final carry, if any. Full adders can be used

to perform subtraction provided we have the necessary additional hardware to generate 2s

complement of the subtrahend and disregard the final carry or overflow. For addition, the

addend bits must be added with augend bits and for subtraction, 2s complement of B is

added with A. Hence Ex-OR gate is used as controlled inverter to achieve this operation.

FA

FA

FA

FA



The mode input determines the operation. With , the circuit acts as an adder and the

outputs provide sum of the two numbers. When , the circuit acts as a subtractor and the

output bits provide the difference of the two inputs.

Comparators:

The comparison of two numbers is an operation that determines if one number is greater than,

less than, or equal to the other number. A magnitude comparator is a combinational circuit

that compares two numbers, and , and determines their relative magnitudes. The outcome

of the comparison is specified by three binary variables that indicate whether

One Bit Comparator:

The 1-bit comparator compares two 1 bit numbers and gives an output based on the

magnitude of two bits. The truth table for the circuit is as shown:

( )

( ) ( )

( )

4 Bit Magnitude Comparator:

0 0 0 1 0

0 1 0 0 1

1 0 1 0 0

1 1 0 1 0



Consider two numbers, with four digits each.

The two numbers are equal if all pairs of significant digits are equal, i.e., if and

and and .The equality of the two numbers , is displayed in

a combinational circuit by an output variable that is designated as ( ). This binary

variable is equal to 1 if the two input numbers are equal, and it is equal to 0,

otherwise.

( )

The binary variable ( ) is equal to 1 if all pairs of digits of the two numbers are equal.

To determine if is greater than or less than , the relative magnitudes of pairs of significant

digits is inspected starting from the most significant position.

If the two digits are equal, the next lower significant pair of digits is compared. This

comparison continues until a pair of unequal digits is reached. If the corresponding digit of

is 1 and that of is 0, we conclude that . If the corresponding digit of is 0 and that of

is 1, we have that . The sequential comparison can be expressed logically by the

following Boolean functions:

( )



( )

The symbols ( ) and ( ) are binary output variables that are equal to 1 when

or , respectively.

Magnitude Comparator using 7485:

Magnitude comparators are available in IC form. For example, 7485 is a four-bit magnitude

comparator of the TTL logic family. The logic circuit inside these devices determines

whether one four-bit number, binary or BCD, is less than, equal to or greater than a second

four-bit number. It can perform comparison of straight binary and straight BCD (8-4-2-1)

codes. These devices can be cascaded together to perform operations on larger bit numbers

without the help of any external gates. This is facilitated by three additional inputs called

cascading or expansion inputs available on the IC. These cascading inputs are also designated

as A = B, A > B and A < B inputs.

The functional table for 7485 is as shown below:



Cascading of Magnitude Comparators:

Magnitude comparators available in IC form are designed in such a way that they can be

connected in a cascade arrangement to perform comparison operations on numbers of longer

lengths. In cascade arrangement, the A = B, A > B and A < B outputs of a stage handling less

significant bits are connected to corresponding inputs of the next adjacent stage handling

more significant bits. Also, the stage handling least significant bits must have a HIGH level at

the A = B input. The other two cascading inputs (A > B and A < B) may be connected to a

LOW level.

Ex: Design an 8 bit magnitude comparator using 7485.

Decoders:

A decoder is a combinational circuit that converts binary information from input lines to a

maximum of unique output lines. If the -bit decoded information has unused or dont

care combinations, the decoder output will have fewer than outputs. The decoders are

called -to- line decoders, where . Their purpose is to generate the (or fewer)

minterms of input variables.

Decoder:

In decoder or -to- line decoder, the three inputs are decoded into eight outputs, each

output representing one of the minterms of the 3 input variables. It is also known as binary to

octal converter. The input variables may represent a binary number, and the outputs will then

represent the eight digits in the octal number system.



Combinational Logic Implementation:

A decoder provides the minterms of input variables. Since any Boolean function can be

expressed in sum of minterms, one can use a decoder to generate the minterms and an

external OR gate to form the sum. In this way, any combinational circuit with inputs and

outputs can be implemented with an -to- line decoder and OR gates.

Example: Implement a Full adder using a decoder and OR gates.

From the truth table of Full adder: ( ) ( )

0 0 0 1 0 0 0 0 0 0 0

0 0 1 0 1 0 0 0 0 0 0

0 1 0 0 0 1 0 0 0 0 0

0 1 1 0 0 0 1 0 0 0 0

1 0 0 0 0 0 0 1 0 0 0

1 0 1 0 0 0 0 0 1 0 0

1 1 0 0 0 0 0 0 0 1 0

1 1 1 0 0 0 0 0 0 0 1



Decoder with Enable Input:

Decoder using decoders:

Decoder circuits can be connected to form a larger decoder circuit. When the top

decoder is enabled and the other is disabled. The bottom decoder outputs are all 0s, and the

1 1 1 1 1 0 0 0 0 1 1 1

0 0 1 1 0 1 1

0 1 0 1 1 0 1

0 1 1 1 1 1 0



top eight outputs generate minterms 0000 to 0111. When the bottom decoder is

enabled and generate minterms 1000 to 1111, while the outputs of the top decoder are all 0s.

Encoders:

An encoder is a digital circuit that performs the inverse operation of a decoder. An encoder

has (or fewer) input lines and output lines. The output lines generate the binary code

corresponding to the input value.

Octal to Binary Encoder:

Priority Encoder:

A priority encoder is a practical form of an encoder. The encoders available in IC form are all

priority encoders. In this type of encoder, a priority is assigned to each input so that, when

more than one input is simultaneously active, the input with the highest priority is encoded.

1 0 0 0 0 0 0 0 0 0 0

0 1 0 0 0 0 0 0 0 0 1

0 0 1 0 0 0 0 0 0 1 0

0 0 0 1 0 0 0 0 0 1 1

0 0 0 0 1 0 0 0 1 0 0

0 0 0 0 0 1 0 0 1 0 1

0 0 0 0 0 0 1 0 1 1 0

0 0 0 0 0 0 0 1 1 1 1



-to- line Priority Encoder:

K-map for : K-map for :

1 0 0 0 0 0

1 0 0 0 1 1 0 1 0 1 1 1

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