J.O.B. Technologies (Strategic Marketing, Sales & Technology) 1 32nm Node USJ Formation Using Rapid Process Optimization Metrology & Updates From March

J.O.B. Technologies (Strategic Marketing, Sales & Technology)

1

32nm Node USJ Formation Using Rapid Process Optimization

Metrology&

Updates From March MRS, May IWJT, May ECS, June IIT and June

VLSI Sym John O. Borland, J.O.B. Technologies, Aiea, HI

Yoji Kawasaki, Renesas Technology, Itami, Japan

Brian Chung, KLA-Tencor, San Jose, CA

Jeffri Halim, Frontier Semiconductor, San Jose, CA

Solid State Technology July 2008

Outline• Introduction

– <10nm Ultra-Shallow Junction– Junction “Quality” (Rs dopant activation, junction leakage and

residual implant damage after annealing)– Micro-uniformity variation

• USJ Implantation• USJ Annealing• Process Integration Issues• FinFET Doping• Summary

J.O.B. Technology (Strategic Marketing, Sales & Technology)

2

Design For Manufacturing: Controlling Process Variability Key For sub-45nm Node Manufacturing!

T.C. Chen, IBM, IEEE Solid State Circuits Society Newsletter, Vol. 20, No. 3, Sept 2006, p.5

Delta Vt=>100mV (0.1V)!-Process proximity effects-Layout loading effects-Gate line edge roughness effects-Implant dopant positioning-Thermally induced variation by RTA (& msec anneal)Key will be Characterization, Reduction & Accommodation

3 Main Sources Areas Of Device Leakage• Gate Leakage

– High-k/Metal Gate reduce gate leakage by >1,000x

• Source Drain Leakage– Engineer the location of EOR

damage to reduce junction leakage

• Gate Edge Leakage– Extension/HALO junction leakage

influenced by band to band tunneling, HALO dose, extension abruptness and shallow EOR damage


4

Surdeanu et al, Philips/IMEC, SSDM 2004, Sept. 04

Advanced USJ RequirementsC.-H. Jan et al., IEDM 2005, p.65• Minimize Dopant Diffusion

• Maximize electrical activation

• “Enough” defect annealing– Junction leakage: Small part of

total power, but significant for low power CMOS

– High channel/halo doping greatly increases leakage

• Need to optimize all 3 “dimensions”• Damage metrology:

– Traditional - TEM, devices– Non-Contact:

• RsL – RS & Junction Leakage• Thermal-wave

Rapid Process

Optimization

P. Timans et al., MRS 2008

Slow and costly!


6

MRS March 2008

32nm Node Xj= 8-20nm so B (150eV-600eV)!25 (IBM)

NO due to MSA micro-uniformity & unstable defects needs post diffusion-less spike/RTA!


7

IMEC, VLSI Sym 2008, paper 19.1

(A/cm2)E-0

E-1

E-2

E-3

E-4

E-5

8

Borland, IWJT 2008

E-2

E-4

E-6

9

Spike

SPE:Si-PAI

SPE:Ge-PAI

Spike:RsL

Flash:RsL

SPE:Ge-PAI

Flash:Ge-PAI RsL

RsL Leakage Range

HALO Dose Effects On RsL & Diode Leakage

Borland, IWJT 2008

Outline• Introduction• USJ Implantation

– Single wafer implanter design– Elemental species (energy, dose)

• USJ Annealing• Process Integration Issues• FinFET Doping• Summary


10


11

Kuroi & Kawasaki, USJ 2005

Greatest TW Change Is In Diagonal Scan!


12

JOB/IMEC USJ Study


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B 500eVTW=667

5keV Ge-PAI+BTW=1520

20keV Ge-PAI+BTW=2900

DSA 1210CTW=24

Stable DefectsRs=579

DSA+Levitor 900C Spike

TW=19Stable Defects

Rs=627

DSA 1210CTW=140

Unstable defectsRs=521

DSA+Levitor900 SpikeTW=130

Unstable DefectsRs=616

MRS March 2008

Selete Demonstration of SDE Tilt


15

Ootsuka et al., IEEE Trans Electron Devices, April 2008, p.1042

~15%

7% Improvement Due To Gate Overlap Control


16

Fujitsu, VLSI Sym 2008, paper 19.2


Borland, Moroz, Wang, Maszara & Iwai, Solid State Technology, June 2003

A4 A2

A1

A3

(B) Terraced double SS/D formed by 45 degree twist quad-mode implant

(A) Terraced triple SS/D formed by 0 degree twist quad-mode implant

1&3, 2&4

2x dose4x dose

3x dose 1x dose4x dose

Sel. Epi

Sel. Poly Sel. PolySel. Poly

Use Selective Poly To Eliminate Facet IssuesB1

B2B3

B4

Sel. Poly

Sel. Epi

(A&B) Terraced penta SS/D formed by 0 & 45 degree twist octa (8)-mode implant

8x dose

1x dose

5x dose7x dose

3x dose

SOI

SOI

SOI

Lateral Graded Single-S/D


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Gate OverLap Control: Tilt nSDE & PAI (0o-vs-30o)

Rp=3.7nmXj=14.7nmYj=0-3.3nmYj/Xj=0-0.22

Rp=3.3nmXj=15.3nmYj=8.3nmYj/Xj=0.54

Borland & Moroz, Semiconductor International, p.72, Apr. 03

BoxShape

Sin20o=0.34xSin30o=0.5xSin45o=0.71x

Future: Phosphorus Replacing Arsenic? (1keV/1E15/cm2, 0 & 30 Degree Tilt)

0o Tilt 30o Quad Tilt Ge-PAI & 30o Quad Tilt

Xj=12nmYj=3-5nmYj/Xj=0.42

Xj=13nmYj=7nm

Yj/Xj=0.53

Xj=9nmYj=7nm

Yj/Xj=0.78 V. Moroz, Synopsys (Mar. 03)

BoxShape

• Annealing Companies– US

• Mattson fRTP• Applied laser DSA• UltraTech laser LSA

– Japan• DNS Flash lamp (FLA)

• Metrology For Rapid Process Optimization

• KT– Thermal-Probe (TW) for implant damage

and after anneal damage recovery (residual implant damage)

• Frontier– RsL sheet resistance and junction leakage

current

• Equipment Companies– US

• Varian (VIISta-HCS & -PLAD)– Carborane option

• Axcelis (Optima-HD)– Imax (molecular dopant)

• AIBT (i-Pulsar)– EC filter so >10/1 decel ratio with no energy contamination

• SemEquip (molecular dopant)– B18, C7, C14, P4, etc.

• TEL-Epion (infusion doping)– B2H6, GeH4

– Japan• SEN/Axcelis (SHX)

– 40/1 decel!

• Nissin & SemEquip


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Outline• Introduction• USJ Implantation• USJ Annealing

– Diffusion-less dopant activation and implant damage recovery– Spike+msec, msec+spike or msec+spike+msec annealing

sequences

• Process Integration Issues• FinFET Doping• Summary


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DSA Laser Stitching Pattern Effect On Device Variation!


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IMEC, VLS I Sym 2008, paper 19.1

23

600

605

610

615

620

625

630

635

-30 -20 -10 0 10 20 30

Y-axis (mm)

Rs

(O

hm

/sq

)

600

605

610

615

620

625

630

635

0 1 2 3 4 5 6 7 8 9

Y-axis (mm)

Rs

(Oh

m/s

q)

50mm

300mm

JOB/IMEC DSA USJ Analysis

3.6mm

3.6mm

25mm

3.6mm


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DSA: 5keV Ge-PAI+B

DSA+Spike: 5keV Ge-PAI+B


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fRTP RsL & TW Wafer Map & Line Scan

Line Scan Y - Axis

Line Scan X - Axis

Rs=1.5%TW=3.6%


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200mm High Resolution Map - 0.5mm step

RsL & TW Map & Line Scan of Sweeping Laser

Peak to peakRs=+/-7.5%

Rs=2456 (1.8%)


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Rs=8.5% global and 1.5% local


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TW=26%, Rs=8.5% Rs=2.8%

NEC & Selete IWJT 2007:Differences For Flash & Spike Results Temperature?


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Bss (atoms/cm3)

Borland’s IWJT 2007 Joint NEC (S4-8) and Joint Selete (S4-7) papers


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PAI Enhanced Activation At Lower Flash Temperatures But EOR Damage/Leakage

J. GelpyKato et al., Selete, IWJT 2007, p.143

1175C!

DSA Laser Requires Deep Ge-PAI So USJ Will Be Leaky!


31

T. Noda et al., SSDM 2007, paper A-5-1, p. 712

1225C!

IMEC agrees DSA -75C!March 2008

0

500

1000

1500

2000

2500

Low LSAPower

Medium LSAPower

High LSAPower

B500eV

5keVGe+B

10keVGe+B

20keVGe+B

B18H22

BF2

RsL Sheet Resistance (ohms/sq.)

<1150C? >1325C?

Borland et al., JOB Tech/Renesas/FSM/KT, Solid State Technology July 2008


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Nara et al., Selete,ECS May 2008

1.2E20/cm3

1.2E20/cm3

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Borland et al., JOB/Renesas/FSM/KT, Solid State Technology, July 2008

LSA power level 6

LSA power level 5

LSA power level 4

LSA power level 3

LSA powerr level 2

LSA power level 1

1.00E-08

1.00E-07

1.00E-06

1.00E-05

1.00E-04

1.00E-03

SPE Low LSAPower

MediumLSA Power

High LSAPower

B500eV

5keVGe+B

10keVGe+B

20keVGe+B

B18H22

BF2

RsL Junction Leakage Current (A/cm2)

Borland et al., JOB Tech/Renesas/FSM/KT, Solid State Technology, July 2008


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37

B

5keVGe+B

20keVGe+B

<1150C----------------------------------------->1350C


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10

100

1000

10000

Control Low LSAPower

MediumLSA

Power

High LSAPower

SPE

B500eV

5keVGe+B

10keVGe+B

20keVGe+B

B18H22

BF2

Thermal-wave Units

Stable Defects


No anneal <1150C <1250C >1325C <650C

No Ge-PAI Residual EOR Damage

At <7nm

Mineji et al., Selete, SSDM 2004,Sept. 04

Surdeanu et al, Philips/IMEC, SSDM 2004, Sept. 04

700oC iRTP, 1100oC fRTP + 950oC Spike RTA

700oC iRTP, 1300oC fRTP



66nm66nm66nm66nm

R. Camillo-Castillo et al., U of F, MRS Spring meeting 2008, paper E6.9

Lower Energy Ge-PAI & Higher MSA Peak Temp or Post 950C Spike RTA Reduces EOR Defects Density!


41J.O.B. Technology (Strategic Marketing, Sales & Technology)

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V. Moroz et al., MRS Spring meeting, paper E6.6


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Yeong et al., CSM, IIT-2008


430.00000001

0.00000010

0.00000100

0.00001000

0.00010000

0.00100000

SPE Flash 900C+FLA 1000C+FLA 1000C Spike

B500eV

10keVGe-PAI+B

B18H22

RsL

Ju

nc

tio

n L

eaka

ge

Cu

rre

nt

(A/c

m2) 0.00

500.00

1000.00

1500.00

2000.00

2500.00

SPE Flash 900C+FLA 1000C+FLA 1000CSpike

B500eV

10keVGe-PAI+B

B18H22R

sL S

hee

t R

esis

tan

ce (

oh

ms/

sq.)

Borland et al., JOB Tech/Selete/Nanometrics, IWJT 2007

900C Spike 1st+FLA For Low Leakage & Complete Damage Annealing With 10keV Ge-PAI


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Extension Results (Leakage)

1.00E-08

1.00E-07

1.00E-06

1.00E-05

1.00E-04

1.00E-03

1.00E-02

900C spike Spike+FLA FLA+Spike Flash SPE SPE+FLA FLA+SPE

B200eV

5keVGe+B

890eVBF2

5keVGe+BF2

4keVB18H22

RsL Junction Leakage Current (A/cm2)

F effect: Noda (MRS 2008), Yamamoto (IWJT 2008), England (IIT 2008 P41)

Yamamoto et al., IWJT 2008, MSA pins F in substitutional site and degrades leakage!

>1200C?


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Extension Results (TW)

0

20

40

60

80

100

120

140

160

180

200


B200eV

5keVGe+B

890eVBF2

5keVGe+BF2

4keVB18H22

Thermal-wave (TW units)

Stable Defects

PAI-EOR Damage

Borland & Kiyama, JOB/DNS, IIT-2008


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Ge+BBGe+BF2

SPE

SPE+FlashFlash

Flash+SPE

Stable Defects Unstable Defects

Good leakage with EOR damage

SpikeSpike+FlashFlash+Spike

TW >100 Reveals Residual Implant Damage After Diffusion-less Flash & SPE Anneals

Borland & Kiyama, JOB/DNS, IIT-2008


47

HALO Results (Rs)

0

5000

10000

15000

20000

25000

30000

35000

40000

45000

50000

55000

60000

65000

70000


20keVBF2

45keVIndium

80keVB18H22

Rs Sheet Resistance (ohms/square)

In dopant activation limited by solid solubilityB dopant activation limited by dose

P-Halo (In, B10, BF2)

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In case of indium I/I, a leakage current was detected by RsL.The leakage current depend on the anneal condition.

⇒ High temperature annealing can reduce the leakage.

Leakage current density

Mienji, Borland et al., NEC/JOB/Nissin, IWJT 2007

RsL Leakage Correlation To Diode Leakage

49

Hatem et al., VSEA, IIT-2008


50J.O.B. Technologies (Strategic Marketing, Sales & Technology)

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RsL LSA-1 power RsL SPE RsL LSA-6 power

Borland, Matsuda & Sakamoto, joint NEC paper, Solid State Technology, June 2002,Borland et al., JOB Tech/Renesas/FSM/KT, Solid State Technology, July 2008& Kawasaki et al., IIT 2008

5keVGe-PAI

20keVGe-PAI

10keVGe-PAI

No PAI

Leaky! Good!

<1150C<650C>1350C

C. Hatem, VSEAIIT 2008 RsL(PR1-vs-Ge-PAI+C)


51

P. Timans et al., Mattson, IIT-2008


52

P. Timans et al., Mattson, IIT-2008

Mattson fRTP (>1300C) Leakage Results From IMEC & FSM For Stable Defects (diode & RsL leakage)


53

Spike 1250 FLA 1300 FLA 800int lower HALO SPE +FLA FLA

IMEC

IMEC:HALO

PAI

HALO+PAI

HALO+Anneal

Borland, IWJT 2008, paper 3.2


54

Spike

SPE:Si-PAI

SPE:Ge-PAI

Spike:RsL

Flash:RsL

SPE:Ge-PAI

Flash:Ge-PAI RsL

RsL Leakage Range

Uejima et al., NEC, IWJT 2008

Borland, IWJT 2008

5keV Ge-PAI EOR+HALO >100x Leakage

Outline• Introduction• USJ Implantation• USJ Annealing• Process Integration Issues

– Gate Stack Electrode Material (poly or metal) & Process Flow– eSiGe strain-Si relaxation

• FinFET Doping• Summary


55

Borland’s Updated Gate & Anneal Roadmap(MSA 1st or Spike 1st?)


56

Borland, Solid State Technology, Jan. 2008, p.38

Intel

IBM/AMD

IBM attacked TSMC for still using SiON/poly with eSiGe at 32nm node at VLSI Sym 2008

Only Intel & AMD Use eSiGe at 65nm Node! How Many at 45nm Node? TI Still Says NO! Also High-k? IBM LSTP32nm Node No eSiGe


57

SI news editorial 2/7/08: No eSiGe, no high-k/metal gate, yes immersion lithography, yes msec annealing


58

• P+ Poly Gate Doping To Reduce Tox(inv), Every 0.1nm Counts– Need B diffusion so RTA 1st then msec annealing or opposite?– Poly gate pre-doping– Disposable spacer (reverse S/D)– Metal gate electrode– Gate last (replacement gate)

Ito et al., VLSI Sym. 2003

Spike 1st & msec Last Best For Poly Doping While For SDE msec 1st then Spike Best For Rs


59

T. Sanuki et al., Toshiba/NEC/Sony, IEDM 2007 paper 11.3


60

Poly Gate Pre-doping With LSA Only

Narihiro et al., NEC, IEEE/RTP 2006, p.147

But 45nm Node Process Integration Requires Disposable Spacer And Then msec Annealing Last!


61

Toshiba/NEC/Sony, VLSI Sym. 2007, 12A-3

LSA Strain Relaxation Limits?


62

C. Cheirigh et al., MIT, ECS Trans., vol.3, no. 2, p.355, Oct. 2006

But Fujitsu and others have reported eSiGe with LSA on bulk wafer (non-SOI) at VLSI Sym 2007

Must keep msec anneal <1200C with eSiGe!

Leakage By Ge-PAI & C co-implants into Bulk & SiGe

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Outline• Introduction• USJ Implantation• USJ Annealing• Process Integration Issues• FinFET Doping

– Avoid Amorphization– Retained Dose Limit

• Summary


64

Intel Bulk FinFET& Toshiba eSRAM Bulk FinFET for sub-22nm Node


65

Intel, VLSI Sym 2008 short course

Toshiba, VLSI Sym 2006, paper 9.2

Beam-line Versus Plasma Retained Dose Study For FinFET Devices (Xj=6nm & 15nm)Intel Tri-gate H/W=1 so 45 degree tilt• Beam-line (B, BF2, B18, As,

As4, P, Sb) at 1E15/cm2– Zero tilt– Top=30 degree tilt (side wall=60

degree tilt)– Top=45 degree tilt (side wall=45

degree tilt)– Top=60 degree tilt (side wall=30

degree tilt)– FinFET 30 degree tilt– Intel Tri-gate 45degree tilt

• Plasma (BF3 & B2H6) at 1E15/cm2


66

JOB Technologies working with Nissin & IMEC on this

Duffy et al.,Appl. Phys. Lett. 90,241912 (2007)

Poly-Si

c-Si

Width

Height


67

Enhanced SDE & HALO Dopant Activation

• pMOS– pSDE (1E15/cm2 dose limited by Bss so for FLA

and LSA 6E14/cm2 is OK)• B: 200eV/1E15• BF2: 1keV/1E15• B18: 4keV/5E13

– HALO (3E13/cm2 dose)• As: 20keV/3E13• As2: 40keV/1.5E13• As4: 80keV/7.5E12• Sb: 35keV/3E13

• nMOS – nSDE (1E15/cm2 or > dose)

• As: 1keV/1E15• As2: 2keV/5E14• As4: 4keV/2.5E14• P: 500eV/1E15• P2: 1keV/5E14• P4: 2keV/2.5E14• Sb: 1.7keV/1E15

– HALO (3E13/cm2 dose)• BF2: 20keV/3E13• In: 45keV/3E13 dose limited by Inss?• B18: 80keV/1.5E12

<900C Spike/RTA<700C SPE<1200C Flash

NEC/JOB/NissinIWJT 2007

JOB/DNS IIT 2008

32nm Node (Xj<10nm)• B: 150-350eV/1E15

– Ge-PAI+B (Xe-PAI?)• Ge-PAI <5keV/5E14 (optional if channeling and <1300C msec annealing)

• BF2: 890eV/1E15– Ge-PAI+BF2 (Xe-PAI?)

• Ge-PAI <5keV/5E14 (optional if channeling and <1300C msec annealing)

• B18H22: 4keV/1E15• As: <1.5keV/1E15

• Ge-PAI <5keV/5E14 (optional <1300C msec annealing)

• P: <1keV/1E15 (is PAI needed?)• Sb: <2keV/1E15


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Summary: Reduce Device & Process Variation• USJ Implantation

– Improved single wafer implanter micro-uniformity• Molecular dopant species for Extension & HALO (B18H22, Sb and P4)

• USJ Annealing– Diffusion-less activation with improved micro-uniformity and defect stability

(how best to integrate msec 1st or 2nd ?)• High temperature msec annealing in combination with diffusion-less spike/RTA (900C)

– Metrology for rapid process optimization including micro-uniformity and junction “Quality” detection

• New Thermal-wave for after anneal defect stability and residual implant damage• RsL for sheet resistance and junction leakage measurements with and without HALO

• Process Integration Issues– Gate 1st poly pre-doping or disposable spacer– Gate last no issue– Complete implant damage annealing/stable residual implant damage for

extension and HALO implants together requires post diffusion-less spike

• FinFET Doping– Retained dose issue and molecular dopants for highest quality junctions

Documents

J.O.B. Technologies (Strategic Marketing, Sales & Technology) 1 32nm Node USJ Formation Using Rapid Process Optimization Metrology & Updates From March