Sand to Silicon 32nm Version

8/13/2019 Sand to Silicon 32nm Version

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Copyright 2011, Intel Corporation. All rights reserved.

Intel, Intel logo and Intel Core are trademarks of Intel Corporation in the U.S. and other countries.1

From Sand to SiliconMaking of a Chip

Illustrations

32nm High-K/Metal Gate VersionIncluding 2nd Generation Intel Core processor family

April 2011


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The illustrations on the following foils are low

resolution images that visually support theexplanations of the individual steps.

For publishing purposes there are highresolution JPEG files posted to the Intel website:

www.intel.com/pressroom/kits/chipmaking

Optionally high resolution images are availableas well. Please request them [email protected]
http://www.intel.com/pressroom/kits/chipmakingmailto:[email protected]:[email protected]://www.intel.com/pressroom/kits/chipmaking


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Sand / Ingot

SandWith about 25% (mass) Silicon is afterOxygen the second most frequent chemicalelement in the earths crust. Sand

especially Quartz - has high percentages ofSilicon in the form of Silicon dioxide (SiO2)and is the base ingredient for semiconductormanufacturing.

Melted Silicon scale: wafer level (~300mm / 12 inch)

Silicon is purified in multiple steps tofinally reach semiconductor manufacturing

quality which is called Electronic GradeSilicon. Electronic Grade Silicon may onlyhave one alien atom every one billionSilicon atoms. In this picture you can seehow one big crystal is grown from thepurified silicon melt. The resulting monocrystal is called an Ingot.

Mono crystal Silicon Ingot scale: wafer level (~300mm / 12 inch)

An ingot has been produced fromElectronic Grade Silicon. One ingot

weights about 100 kilograms (=220pounds) and has a Silicon purity of99.9999999%


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Ingot / Wafer

Ingot Slicing scale: wafer level (~300mm / 12 inch)

The Ingot is cut into individual silicon discscalled wafers. The thickness of a wafer isabout 1mm.

fer scale: wafer level (~300mm / 12 inch)

The wafers are polished until they haveflawless, mirror-smooth surfaces. Intel buysthose manufacturing ready wafers fromthird party companies. Intels highly

advanced 32nm High-K/Metal Gate processuses wafers with a diameter of 300millimeter (~12 inches). When Intel firstbegan making chips, the company printedcircuits on 2-inch (50mm) wafers. Now thecompany uses 300mm wafers, resulting indecreased costs per chip.


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Fabrication of chips on a wafer consists of

hundreds of precisely controlled steps whichresult in a series of patterned layers of variousmaterials one on top of another.

What follows is a sample of the most important

steps in this complex process.


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Ion Implantation

Applying Photo Resist scale: wafer level (~300mm / 12 inch)

Fabrication of chips on a wafer consists ofhundreds of precisely controlled steps whichresult in a series of patterned layers ofvarious materials one on top of another.What follows is a sample of the most

important steps in this complex process. Inthis image theres photo resist (blue color)applied, exposed and exposed photo resist isbeing washed off before the next step(more details later). The remaining photoresist (blue shine on wafer) will protectmaterial that should not get ions implanted.

Ion Implantation scale: wafer level (~300mm / 12 inch)

The wafer is patterned using photolithography(details of how this is done will be described later).

The wafer is bombarded with a beam of ions(positively or negatively charged atoms) whichembed themselves beneath the surface of thewafer to alter the conductive properties of thesilicon in selected locations. The green regions inthe image to the right have these implanted alienatoms.

Removing Photo Resist scale: wafer level (~300mm / 12 inch)

After the ion implantation the photo

resist will be removed and the materialthat should have been doped (green)has alien atoms implanted now (noticeslight variations in color)


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High-k Dielectric Deposition

Applying High k Dielectric scale: wafer level (~300mm / 12 inch)

Instead of a traditional insulatorbetween a transistors gate and its

channel, Intel applies multiple layers ofHigh-K dielectric material to thesurface of the wafer. This material isapplied one atomic layer at a time(yellow in the image). This reduceselectrical leakage and enables moreenergy-efficient processors.

Applying High k dielectric scale: wafer level (~300mm / 12 inch)

There are multiple layers of individual moleculelayers being applied to the surface of the wafer. Thetwo yellow layers shown here represent two ofthese layers.

High k Dielectric scale: transistor level (~50-200nm)

This step shows how the High-k insulatorhas been applied to the whole wafer. TheHigh-k material is thicker than thetraditional Silicon-Dioxide layer while it hasthe same capacitive properties to maximizeperformance. Due to the increasedthickness less current leaks through thisinnovative insulator.


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Photo Lithography

Applying Photo Resist scale: wafer level (~300mm / 12 inch)

The liquid (dark color here) thatspoured onto the wafer while it spins is

a photo resist finish similar as the oneknown from film photography. Thewafer spins during this step to allowvery thin and even application of thisphoto resist layer.

Exposure scale: wafer level (~300mm / 12 inch)

The photo resist finish is exposed to ultra violet (UV)light. The chemical reaction triggered by that processstep is similar to what happens to film material in afilm camera the moment you press the shutterbutton. The photo resist finish thats exposed to UV

light will become soluble. The exposure is done usingmasks that act like stencils in this process step. Whenused with UV light, masks create the various circuitpatterns on each layer of the microprocessor. A lens(middle) reduces the masks image. So what getsprinted on the wafer is typically four times smallerlinearly than the masks pattern.

Exposure scale: transistor level (~50-200nm)

Although usually hundreds ofmicroprocessors are built on a single wafer,this picture story will only focus on a small

piece of a microprocessor from now on ona transistor or parts thereof. A transistoracts as a switch, controlling the flow ofelectrical current in a computer chip. Intelresearchers have developed transistors sosmall that about 30 million of them could fiton the head of a pin.


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Etching

Washing off of Photo Resist scale: transistor level (~50-200nm)

The gooey photo resist is completelydissolved by a solvent. This reveals apattern of photo resist made by themask (dark rectangle here).

Etching scale: transistor level (~50-200nm)

The photo resist is protecting the high-k

dielectric that should not be etched away.Revealed material will be etched awaywith chemicals.

Removing Photo Resist scale: transistor level (~50-200nm)

After the etching the photo resist is

removed and the desired shape becomesvisible.


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Metal Deposition

After Electroplating scale: transistor level (~50-200nm)

On the wafer surface the copper ions

settle as a thin layer of copper.

Electroplating scale: transistor level (~50-200nm)

The wafers are put into a copper sulphatesolution at this stage. The copper ions are

deposited onto the transistor thru aprocess called electroplating. The copperions travel from the positive terminal(anode) to the negative terminal (cathode)which is represented by the wafer.

Ready Transistor scale: transistor level (~50-200nm)

This transistor is close to being finished.

Three holes have been etched into theinsulation layer (red color) above thetransistor. These three holes will befilled with copper or other materialwhich will make up the connections toother transistors.


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Metal Layers

Polishing

scale: transistor level (~50-200nm)

The excess material is polished off.

Metal Layers scale: transistor level (six transistors combined ~500nm)Multiple metal layers are created to interconnect (think: wires) in between thevarious transistors. How these connections have to be wired is determined by thearchitecture and design teams that develop the functionality of the respectiveprocessor (e.g. Intel Core i5 Processor ). While computer chips look extremely flat,they may actually have over 30 layers to form complex circuitry. If you look at amagnified view of a chip, you will see an intricate network of circuit lines andtransistors that look like a futuristic, multi-layered highway system.


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When wafer processing is complete, the wafers

are transferred from the fab to an assembly/testfacility.

There, the individual die are first tested, then thethey are singulated and the ones that passed

their test are packaged. Finally, a thorough testof the packaged part is conducted before thefinished product is shipped.


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Wafer Sort Test / Slicing

Wafer Sort Test scale: die level (~10mm / ~0.5 inch)

This fraction of a ready wafer is beingput to a first functionality test. In thisstage test patterns are fed into everysingle chip and the response from thechip monitored and compared to theright answer.

Wafer Slicing

scale: wafer level (~300mm / 12 inch)

The wafer is cut into pieces (called dies).The above wafer contains 2ndgeneration Intel Core i5 processorswith integrated Intel HD Graphics.

Discarding faulty Dies scale: wafer level (~300mm / 12 inch)

The dies that responded with the right

answer to the test pattern will be putforward for the next step (packaging).


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Packaging

Packaging scale: package level (~20mm / ~1 inch)

The substrate, the die and theheatspreader are put together to form a

completed processor. The green substratebuilds the electrical and mechanicalinterface for the processor to interact withthe rest of the PC system. The silverheatspreader is a thermal interface wherea cooling solution will be put on to. This willkeep the processor cool during operation.

Individual Die scale: die level (~10mm / ~0.5 inch)

These are individual dies which havebeen cut out in the previous step

(slicing). The dies shown here are dies ofa 2nd generation Intel Core i5Processor.

Processor scale: package level (~20mm / ~1 inch)

Completed processor (2nd generationIntel Core i5 Processor in this case). A

microprocessor is the most complexmanufactured product on earth. In fact, ittakes hundreds of steps only the mostimportant ones have been visualized inthis picture story - in the world's cleanestenvironment (a microprocessor fab) tomake microprocessors.


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Class Testing / Completed Processor

Class Testing scale: package level (~20mm / ~1 inch)

During this final test the processors willbe tested for their key characteristics(among the tested characteristics arepower dissipation and maximumfrequency).

Binning scale: package level (~20mm / ~1 inch)

Based on the test result of class testingprocessors with the same capabilities areput into the same transporting trays.

Retail Package scale: package level (~20mm / ~1 inch)

The readily manufactured and testedprocessors (again 2nd generationIntel Core i5 Processor is shown here)either go to system manufacturers intrays or into retail stores in a box such asthat shown here.


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Sand to Silicon 32nm Version